 Hello, and welcome to this presentation of the STM32G4 Reset and Clock Controller, or RCC. The STM32G4 Reset and Clock Controller manages system and peripheral clocks. STM32G4 microcontrollers embed three internal oscillators, two oscillators for an external crystal or resonator, and one phase locked loop, or PLL. Many peripherals have their own clock, independent of the system clock. The RCC also manages the various resets present in the device. The STM32G4 RCC provides high flexibility in the choice of clock sources, which allows the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication baud rates, and also to keep some peripherals active in low power modes. Finally, the RCC provides safe and flexible reset management. Safe and flexible reset management without any need for external components reduces application costs. The RCC manages three types of resets. The system reset, the power reset, and the backup domain reset. The peripherals have individual reset control bits. The first type of reset is the system reset, which resets all the registers except certain registers for the reset and clock controller and power controller. It also does not reset the backup domain. The system reset sources are the external reset generated by a low level on an NRST pin, a window watchdog event, an independent watchdog event, a firewall event, a software event through the nested vectored interrupt controller, a low power mode security reset, which is generated when stop, standby, or shutdown mode is entered, but prohibited by the option byte configuration, an option byte loader reset, and a brownout reset. The reset source flag can be found in the RCC control and status register. Here is the simplified block diagram of the system reset. All internal reset sources provide a reset signal on the NRST pin, which can be used to reset other components of the application board. In addition, no external reset circuitry is needed due to the internal glitch filter and the safe power monitoring feature, which guarantees the reset of the application when VDD is below the selected threshold. The internal pull-up on the NRST pin, which maintains a high level when no reset signal is driven low, is deactivated when an internal reset is driven in order to reduce power consumption under reset. Additionally, all IO pins are placed in analog mode during and after reset to eliminate power consumption through the Schmidt trigger when the IOs are floating under reset and before software initialization. The second type of reset is the power reset. The brownout reset, or BOR, resets all registers except those in the backup domain powered by VBAT, which contains the RTC and the external low-speed oscillator. When exiting standby mode, all registers powered by the regulator are reset. When exiting shutdown mode, a brownout reset is generated. The third type of reset is the backup domain reset, which resets the RTC registers, the backup registers, and the RCC backup domain control register. This reset occurs when the BDRST bit is set in the RCC backup domain control register. It also occurs when VDD and VBAT are powered on if both supplies have previously been powered off. Through specific option bits, the NRST pin is configurable for operating as, in first mode, a reset input output. This is the default at device delivery. Any valid reset signal on the pin is propagated to device internal logic and all internal reset sources are externally driven through a pulse generator to this pin. The GPIO functionality on PG-10 is not available. The pulse generator guarantees a minimum reset pulse duration of 20 microseconds for each internal reset source to be output on the NRST pin. An internal reset holder option can be used if enabled in the option bytes to ensure that the pin is pulled low until its voltage meets the VIL threshold. This function guarantees the detection of internal reset sources by external components when the line faces a significant capacitive load. In case an internal reset, the internal pull-up RPU is deactivated in order to save power consumption through the pull-up resistor. In second mode, a reset input. In this mode, an invalid reset signal on the NRST pin is propagated to device internal logic but resets generated internally by the device are not visible on the pin. In this configuration, GPIO functionality on PG-10 is not available. In third mode, a GPIO. In this mode, the pin can be used as PG-10, standard GPIO. The reset function of the pin is not available. Reset is only possible from device internal reset sources and is not propagated to the pin. The RCC offers a large choice of clock sources, which can be selected depending on the low power, accuracy, and performance requirements. STM32G4 devices embed three internal clock sources, a high-speed internal 16 MHz RC oscillator or HSI16, a high-speed internal 48 MHz oscillator or HSI48, and a low-speed internal 32 kHz RC oscillator or LSI. STM32G4 devices embed two oscillators for use with an external crystal or resonator, a high-speed external 4 to 48 MHz oscillator or HSI with a clock security system and a low-speed external 32.768 kHz oscillator or LSE, also with a clock security system. When enabled, the clock security system can detect failures on external clock sources and an automatic switch to an internal oscillator is performed. HSI16, in case of HSE failure, and LSI, in case of LSE failure. If a failure is detected on the HSE clock, a clock failure event is sent to the break input of the advanced control timers and to the HRTIM system fault input at an interrupt is generated to inform the software about the failure. The PLL present in the STM32G4 has three independent outputs in order to offer different frequency options to CPU and peripherals. This table highlights the differences between the STM32F3 and the STM32G4 clock sources. Both support the HSI16 and the LSE oscillators. The low-speed internal oscillator or LSI frequency is 40 kHz for the STM32F3. 32 kHz for the STM32G4 microcontroller. The HSI48 is not supported by the STM32F3. The maximum frequency for the HSE is 32 MHz for the STM32F3, 48 MHz for the STM32G4 microcontroller. At last, the STM32G4 PLL has three outputs instead of one in the STM32F3 microcontroller. The system clock can be derived from the high-speed internal 16 MHz RC oscillator or HSI16 or from the high-speed external 4 to 48 MHz oscillator or HSE. The AHB clock, called H-Clock, is derived by dividing the system clock by a programmable prescalar. The APB clocks, called P-Clock 1 and P-Clock 2, are generated by dividing the AHB clock by programmable prescalars. The RTC clock is generated by the low-speed external 32.768 kHz oscillator or LSE, the low-speed internal 32 kHz RC oscillator or LSI or the HSE divided by 32. The LSE can remain enabled in all low-power modes and in VBAT mode. The LSI can remain enabled in all modes except shutdown and VBAT modes. The high-speed internal oscillator is a 16 MHz RC oscillator which provides 1% accuracy and fast wake-up times. The HSI16 is trimmed during production testing and can also be user-trimmed. The HSI16 can be selected as the clock at wake-up from stop 0, stop 1 or stop 2 modes and as the backup clock if an HSE failure is detected by the clock security system. The HSI16 can be automatically awoken when exiting stop mode in order to make it available for peripherals when it is not used as the system clock. The HSI16 is requested by the I2C, the USART and LPUART peripherals to support wake-up from stop 0, stop 1 or stop 2 modes. HSI16 is enabled only for the wake-up sequence detection and remains disabled outside of this wake-up sequence. The high-speed external oscillator provides a safe crystal system clock. The HSE supports a 4-48 MHz external crystal or ceramic resonator and also an external source in bypass mode. A clock security system allows an automatic detection of an HSE failure. In this case, a non-mascable interrupt is generated and a break input can be sent to timers in order to put critical applications, such as motor control, in a safe state. When an HSE failure is detected, the system clock is automatically switched to an internal oscillator, the HSI16, so the application software does not stop in case of crystal failure. The 32.768 kHz low-speed external oscillator can be used with an external quartz or resonator or with an external clock source in bypass mode. The oscillator driving capability is programmable. Four modes are available, from ultra-low power mode with a consumption of only 250 nanoamps to high driving mode. A clock security system monitors for failure of the LSE oscillator. In case of failure, the application can switch the RTC clock to the LSI. The CSS is functional in all modes except shutdown and VBAT. It is also functional under reset. The LSE can be used to clock the RTC, the USARTS or low-power UART peripherals, and the low-power timers. The input clock of the PLL can be HSI16 or HSE. The PLL output called PLLR clock can provide the system clock. The PLL output called PLLQ clock can be selected as the root clock of USB device, RNG, SAI1, QSPI, and FD CAN. The PLL output called PLLP clock can be selected as the root clock of ADCs. The system clock is selected between the HSI16, HSE, and PLLR output. The maximum system clock frequency is 170 MHz. The APB1 and APB2 bus frequencies are also up to 170 MHz. The maximum clock source frequency depends on the voltage scaling and power mode. The system clock is limited to 170 MHz in range 1 boost mode, 150 MHz in range 1 normal mode, 26 MHz in range 2, and 2 MHz in low-power run and low-power sleep modes. In STM32G4 devices, it is recommended to use a transition state while switching from low to high speed or from high to low-speed system clock. This slide presents the recommended sequence for the transition state. To increase the frequency, the AHB clock frequency has to be divided by 2 prior to switching the system clock to PLL. After a 1-microsecond delay, the pre-scaler providing the AHB clock can be set to the targeted frequency. This is needed when switching from HSE or HSI to PLL and the system frequency becomes higher than 80 MHz. The AHB pre-scaler divides the system clock to obtain the AHB clock or H-clock. APB clocks called P-clock 1 and P-clock 2 are obtained by applying a programmable pre-scaler ratio to H-clock. This slide also describes the multiplexers in charge of selecting the clock of various peripherals. The ADC clock is derived from the system clock or from the PLL P-output. This PLL P-clock has no other usage. The various clocks can be output on an IOPAD. The microcontroller clock output feature enables the external output of one of these 7 clocks. HSI 16, HSI 48, HSE, LSI, LSE, CIS clock and PLL clock. The low-speed clock output feature enables the external output of the LSI or LSE clock. The low-speed clock output is available in stop 0, stop 1, standby and shutdown modes. It is possible to indirectly measure the frequency of all on-board clock sources by means of the TIM-5, TIM-15, TIM-16 or TIM-17 channel 1 input capture. These measurements can be used to calibrate the LSI and HSI 16 frequencies. Regarding HSI 16, RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. This is why each device is calibrated at the ST factory for 1% accuracy at the ambient temperature of 25 degrees Celsius. After reset, the HSI 16 factory calibration value is automatically loaded. If the application is subject to voltage or temperature variations, software can perform a clock trimming. The dynamic power consumption can be optimized by using peripheral clock gating. Each peripheral clock can be gated on or off in run and low power run mode except SRAM 1, SRAM 2 and CCM SRAM internal memories which are always clocked in run and low power run modes. By default, the peripherals clock is disabled except the flash memory clock which is enabled. When a peripherals clock is disabled, the peripherals registers cannot be read or written. Other registers allow the configuration of the peripherals clock during the sleep and low power sleep modes. This also affects stop 0 and stop 1 modes for peripherals with an independent clock active in stop modes. These control bits have no effect if the corresponding peripheral clock enable bit is cleared. By default, the SRAM 1, SRAM 2 and CCM SRAM clocks are enabled in sleep and low power sleep modes. If they are not needed, the SRAM clock enable bits should be disabled to reduce power consumption. This slide lists the RCC interrupts, the LSE and HSE clock security systems, the PLL ready and all five oscillator ready signals can generate an interrupt. In addition to this training, you may find the power control and interrupt controller trainings useful. For more details, please refer to application note AN2867, an oscillator design guide for STM8S, STM8A and STM32 microcontrollers and application note AN4736, which explains how to calibrate STM32L for internal RC oscillators.