 My name is Marik Vashu then today I'm going to talk about these open source tools for fpga development So let me do a quick introduction with myself first. I work for this company. Thanks after engineering. We do all sorts of embedded real-time systems Development we work on you boot Linux open and be did and we provide trainings Me I mostly work on the Linux kernel on the you boot loader open and be did these sorts of things and I'm also an fpga hobbyists Although this is starting to be like a bigger thing for me. So that's who I am. No, let's get to the talk I'll structure it in the following way First of all, I would like to introduce the fpga technology itself What are what the fpgs are how they work on the inside a little so that you have an idea of what that is all about and Then I'll go through the entire process of generating the bit stream, which is the File which goes into the fpga From the source files and each in each step. I would like to show you a couple of tools which are available which are open source After that we will have a demo which is great But I don't have a board with me which I forgot in in my hometown which blows But I'll show you a simulation. So you will at least be able to believe me that I'm doing something there And finally, I would like to have a bit of a discussion why this is hard Although I kind of hope that this talk will give you an idea why there are so little open source tools for the fpgas Okay, let's get right into the fpga start fpj part What is an fpga? Let me just ask you how many of you know what the fpga is and That's excellent great and how many of you did ever work with an fpga Oh, wow, excellent. I guess I can skip the first part even But just for the recording Fpga is a field programmable gate array So think of it as a chip where you can synthesize your custom logic design your model of logic it has a lot of Ios which you can bind to to this this logic design and It is relatively high speed The the insides of the fpga are clocked at like hundreds of megahertz and you can put a lot of logic gates in there in the order of thousands to millions and and more so that's the sort of thing it is and it's fully programmable so you can Fully configure the logic on the inside now What is used for? Basically DSP digital signal processing so we can pipe the signal basically through the fpga You can assemble the signal on one side connected to the pins of the fpga then do some transformation on the inside In a pipeline fashion and then just output it on the other side of the fpga Maybe in some different format. It's also often used for bus adapters for example You have some sort of weird let's say aviation buzzer some sort of Obscure thing so you can use an fpga in case there is no dedicated converter chip and pull out something Saying like an SPI from it And then there's the ASIC prototyping part. So I mean building chip is chips is expensive, right? so You design the chip and the HDL language put it into an fpga it will run at a really slow speed But you can debug the chip and then when you are reasonably sure that the chip is okay ish without any Horrible box then then you spin out the buffer and build a real chip and then do some more debugging and so So this is what the FPGAs are used for Now contemporary FPGAs are made by a couple of vendors, you know Xilinx Altera now part of Intel Latest micro-semi and so So let's take a look on the inside of the fpga. I'm sure you can pardon my graphics. It's not awesome But it will do On the left side here. You can see a top-level diagram of the fpga Now on the edge of this diagram, you can see the eye opens This is what connects the fpga logic to the ins to the outside world This is where you connect your whatever LED or high-speed ADC in this sort of stuff and This is rooted into the chip now the the red stuff in the middle of the chip This is where you Configure the programmable logic. This is where you put your logic models. This is called the Logic array block and in Altera parlance It's also called adaptive logic module in the in the newer Altera chips. I believe it's clb in the Xilinx chips and so on So this is where you put your logic stuff and obviously there in the FPGA there is a little more of these this kind of red clusters of logic blobs and All of this is connected together by this blue stuff, which is the global interconnect So you model your logic in the red stuff connected together Using the blue stuff that they'll interconnect and then connect it to the outside again using the blue stuff And the IO blocks which are on the side Now if you look at the red cluster that the logic cluster the logic array block You can see there and at the top how it looks on the inside now It's a little bit more complicated, but not so much the Logic array blog is consisting of logic elements, which are the smallest logic building blocks in the FPGA And these logic elements are connected through a local interconnect together so that they can communicate quickly with one another And this is sort of micro optimization, but but it allows you to build a slightly faster designs the local interconnect the green stuff is then connected to the global interconnect and Yeah, this is how it works now if you zoom in a little bit more even at the logic element Which is the really smallest building block you'll see there is just a lookup table and a register in there and this is really what allows you to build both combinatorial and then sequential logic and By combining these together You can build large logic designs Now are there any questions to the architecture of the FPGA or any corrections possibly Yeah, no, okay, so I can move on right Now let's take a look at how we program the FPGA how we put the content into it Each vendor will provide you a tool chain These are typically proprietary closed source big packages of stuff Typically in the in the ballpark of tens of gigabytes download There are this this quarters silence is Vivado ISE But yeah, the problem is that that's there's a lot of stuff most of it is not needed really if you are working with a small project Of course, if you are working with something big then you still use a lot of these these vendor tools but if you look at the vendor tools and Analyze what they are really doing to get from the source of the design all the way to The bit stream you can kind of divide it into three steps basically One of them is analysis synthesis and there is place and route and finally assembler and On the side there are two more steps, which is timing analysis. This is important for high-speed designs and Then completely on the side is simulation visualization now I would like to go through all these steps and show you the tools Just to give you a kind of high-level overview of what each of these step does The first step that the analysis synthesis You can think of it as it reads the source HDL files and converts them into a sort of schematic of the circuit That's the netlist Then during the big place and route This the sort of schematic of the circuit is combined with the knowledge of the actual FPGA Which you are targeting and you get a technology map netlist So sort of netlist augmented with the placement information of where each of these elements goes into the actual FPGA chip and Then finally the assembler transcribes this this augmented netlist and produces Whatever bit stream file from from this information The timing analysis thing is important the high-speed designs the idea is that speed of light matters right and It might just so happen that some signal is too slow to get to a certain latch in the design at higher speeds And if this were to happen then your design would just not work and there are software tools Which are part of the vendor tools Which allow you to check for this and eventually indicate that there is a problem and Finally the simulation visualization just allows you to Check whether your design Matches some criterion so we can build some sort of test benches test cases for their design run the simulation and check for The result whether this is this is okay or not Okay, so analysis and synthesis is a little bit more in detail I just mentioned that this goes from HDL to netlist that means from the source hardware description language files To a sort of a schematic during the analysis step The source files are loaded into the memory checked whether they are even a valid, you know, better log VHDL or Other high-level synthesis files In this step, we also check whether all the logic is reachable or if you can just drop any piece of the HDL files because it's just not reachable and Build some sort of in memory representation of the circuit and during the synthesis step you dump this into the netlist Usually storing it on to on to drive or storage Now there's sort of an in kind of intermediate step in this process There's a lot of intermediate steps But one is kind of particularly interesting is that there is a logic minimization also in that so when you have this sort of circuit schematic in in the Memory you do equivalent changes on that Representation and try to minimize the logic as much as possible so you don't you don't waste space in the FPGA There are open source tools for that by the way So I'd like to show you three tools in in this chapter in the analysis and synthesis and One of them is Icarus this this is great tool then there is Odin 2 and Yosses this one is also awesome So Icarus I have it here because it used to be able to do synthesis into gate level netlist it cannot do that anymore, but Icarus is a has a great Vettelok parser and it is really pedantic So even if you have a proprietary Flow if you want to verify your Vettelok Vettelok Just let Icarus parse it and it will poke holes into into your design and tell you like yeah There there are some warnings your Vettelok is not completely perfect this sort of thing so yeah It has limited VHDL support although Given the name it's it's not really the target right it also can Generate the other simplified Vettelok as an output and so on It's also a simulation tool and I would like to show you a demo of using the Icarus Vettelok for circuit simulation So yeah, definitely check this tool It's it's it's a great one and we will get to the simulation part shortly now another tool which is used mostly in academia is Odin 2 this works also on Vettelok and It emits usually B-Lift netlist the Odin 2 has been used for both asyc synthesis as well as FPGA synthesis It works greatly with VPR in fact Odin 2 is Now bundled with VPR into Vettelok to routing tool set Which you can I believe find in yeah in in the web in the github there and It's been actually used for asyc synthesis and it's not really that often used for FPGA synthesis What is used for FPGA synthesis is Josses, right So Josses is rather a newcomer But it's written in a really great way the osys and it's it's modern code. It doesn't have any legacy in that and the other thing which is great about the osys is that it can take chip libraries and Generate netlist with chip elements for Asyx a library so it can be used in asyx synthesis It can use the Xion 7 series libraries So you can use it instead of I believe the analysis and synthesis tab in Vivado And then it can generate the latest for the FPG then can use the latest for the series Chip libraries to generate the bits to generate augmented netlist for Further processing in the in the ice storm project So that's that Alright Yeah, one thing which is kind of important is that this works only on verilog now, but the VHDL is being worked on So the osys will eventually support even VHDL if that's your thing So that's the analysis synthesis. Are there any questions regarding these tools for analysis and synthesis? Yes Yeah, well Odin 2 I didn't really study the Odin 2 one But regarding the osys, this is a high quality code. It's being actually actively worked on There is a community around that one So this would be a tool of choice if if you want to to look into things The Icarus verilog is I believe almost one-man show sort of thing, but the the verilog parser is excellent Does this answer your question? Yes, I will get to that in the simulation part. So yes, thanks There is a verilator as well Okay, let's move on place and truth this in this step of the of the build process You take the netlist and convert it into a technology map netlist So basically in this step the the knowledge of the target FPGA enters the picture You take the netlist and Kind of place it into the FPGA or compute the the placement of the elements from the netlist in the target FPGA Now this has multiple sub steps One of them is packed So if you remember the the logic array blocks at the beginning the clusters of the logic Then these are created in the pack step. It puts the logic which is close by in the design Which should be close by in the design close together packs it into these clusters so that There are no long Connections in the FPGA itself because again speed of light matters and then there's place So it computes where these clusters go in in the final FPGA and then there is route Which connects the interconnect between these these clusters Now there are two tools one of them is Arachna PNR Which is kind of specific to to I see for the FPGA from latest and then there is a really generic one VPR Very quickly the Arachna PNR this is specifically written for the IC for the FPGA. It works together with with the YOSIS tool It takes this kind of technology map netlist from from the YOSIS Does the place on the root step on that and produces? Textual representation of what goes into the IC for the FPGA So when you look at the Arachna PNR you'll kind of notice that the the boundary between the analysis and synthesis and The place on the root is not really that sharp and also between the place on the root and assembler But there is a sort of distinction. So it's not like completely ad hoc You can find the sources here. It's not actually Entirely part of the project ice storm. It's kind of outside, but it's used together with you know, the YOSIS and The other ice storm tools now VPR is another tool. This is generally a research tool, but it's extremely flexible It's now part of the vera look to rooting together with the Odin 2 analysis and synthesis tool the thing about this is that you can build any sort of FPGA model and Load it into the VPR and it will use that model. So it gives you that flexibility I believe the FPGA vendors are actually providing some sort of let's say inaccurate and inaccurate models which kind of matched their FPGA without revealing too much about that technology so that the researchers can actually use the the VPR for Doing routing research Also, this one works with the vendor tools so you can use this instead of the place on the root step in the in the vendor tools You can find the original VPR at the website of University of Toronto Which is a big research hub for FPGAs and Then also check the Odin 2 if there is no newer version in the ad repos story So that's placing through then now finally assembler as you can see is we are coming closer to the hardware My voice is starting to fail and Also, the amount of tools is getting lower and lower. This is kind of the set through it So they the closer you get to the hardware the amount of tools is just decreasing because there is this Increasing amount of low-level knowledge, which you need to have to implement these tools now What assembler does is it takes the the place through to the netlist that the augmented netlist with the information of Where each part goes into FPGA and just transcribes it into some sort of binary format Which is the bit stream there can be multiple formats of bit stream that the assembler supports depending on let's say on the programming type of the FPGA so in case you are programming the FPGA over JTAG That might require different bit stream format than for example programming from an SPI flash and The problem with open source assemblers is that the FPGA technology the bit stream format is like The family gold of the FPGA vendors. It's just not going to be released ever unfortunately and Yeah, let's just take a quick look at the ice pack. So the ice peg is again specific to the IC for the FPGA It's part of the ice storm project It takes the outpad from the arachna PNR the textual representation of what goes into the FPGA into the IC for the FPGA and Just transcribes it into binary You can find the the ice storm tools at that website There's also a tool which goes the other way which is called the ice on peg It's also part of the project ice storm all the ice storm tools so Let's just do a quick recap. There are Full design flows. I actually had multiple ones here, but they were ASIC tools So in case we talk about FPGA's we only find this this ice storm project So the ice storm project is specific to the IC for the FPGA it contains consists of three tools implementing this these three steps jose or arachna PNR and ice pack for analysis synthesis place on the root end Bitstream generation. It is actually a complete open source flow for this IC for the FPGA and It's so far the only one There are additional tools ice proc for a programmer So you don't need the latest tools at all you can use completely open source tools to program the FPGA and There is now even newer ice time which allows you to perform timing analysis for the IC 40 without the latest tools Okay now I have a demo how to use the ice storm project. Yes No, the only thing missing from an open source tool chain for any FPGA is a model for possibly with the vpr So for the place on the route and then the assembler So the analysis and synthesis tools are available The framework for place on the route is available, but not the model for it for the vpr and the assembler is not available But if this became available, then yes, we would have an open source tool chain with the state of the art place on the route algorithms For pretty much any FPGA Which would be wonderful? Thank you for the question did it answer your question, right? So moving on let me do the demo So what I do here is I implement the gray counters So I had this board which had eight LEDs and it had an oscillator and then I see 40 FPGA So I modeled it in the following way. I just have an oscillator input That's the hardware clock, and then I have 80 LEDs, which are the outpads You don't have to make photos the slides will be available, you know So you can just download it and I can send you this the sources if you want that it's not a problem Just drop me an email So what I do here is is I have a counter register which is 8 bit and I hope this was the words In here I always in I always incremented on the tick of the hardware clock on positive H of the H of the hardware clock and then I assigned the LEDs in such a way that they Perform the gray counting I Forgot to explain what the gray counting is It's different from binary counting in such a way that each two consecutive Numbers in the gray counter differ just by one bit. So it is it's kind of beneficial when you are designing hardware So this is what happens in here Now since I have implemented my top-level module and I have the gray counter there I also still need to map the signals from the top-level module into The actual pins of the FPGA. This is what I do in my pin map and here I only define which signal goes to which pin of the of the FPGA This is specific to your defkit or to your design So this is what I define in here and finally I build the entire design So I use the yosas for the analysis and synthesis. I use the synth IC 40 command although It is possible to poke into the yosas analysis and synthesis steps some more and Use the specific sub commands by by hand to get some sort of more control over the analysis and synthesis process Here I just used it the bulk command this in the IC 40. I specified at my top-level That my top-level design file is called top and that I want to generate a bill if netlist which is called Top the bill if I provide the top V verilog file, which I wrote here. This. This is called the top V This is the second half of it So I provided to the yosas and it will do its thing and produce the top bill if that list Now the next thing I do is I use arachnaya P and R that as a place in the root step I specify that my particular FPGA is HX 8k CT 256 With these first two parameters The next parameter is that I want to outpad the top TXT which will be the textual representation of the content of the FPGA I specify my pin map here. That's that's this thing here Which I which I've wrote where I just mapped the pins to the signals and I provide the top bill if the bill if netlist So when I have the top TXT this will take like a couple of seconds on any modern hardware I used just the ice pack to transcribe it into a binary file and then I use ice probe to program it into the FPGA Now I would definitely like to show you the board which does the grain counting but like I said I kind of forgot it so I'll show you the simulation and then you will see how it's supposed to work Let's talk about simulation verification. Are there any questions regarding the the ice storm demo? No Yes Well the cheapest one is like 25 bucks. It's extremely cheap But it's unobtainable now because when the ice storm hit the news it's just everyone bought the kit and the lead time was like 29 weeks, right and There's a more expensive one like 50 bucks or something With a larger FPGA and you can still buy that one Until they restock the cheaper one Thanks for the question So moving on to to analysis and synthesis Sorry to simulation visualization So the idea here is that you take your HDL designs and you simulate them on the host in On a clock per clock basis The thing is that you can write a test bench for your design and Provide input into your designs and then check whether after a set amount of clock or at some event if The outpads match what you expect this helps during development Because if you do some change to your design Then then you can just rerun the simulations and see whether your design is still matching the specification at the beginning Of of design process or if you change something and broke something It also helps if you are looking for some bug then then just take the IP block run the simulation take a look at What happened there at the signals you can poke into the signals in the IP block and see what's going on in there There are multiple tools for this because you don't need the actual knowledge of the FPGA. So these tools do exist I would like to talk about GHDL first because this in VHDL tool. It translates VHDL into native code so it's extremely fast and The problem is that while it can outpad the VCD the volume change them the whenever able text representation of the simulation very low sorry VHDL Needs some some more information in the simulation outpads so GHDL had to create their own format But you don't have to be really afraid of that of the GHDL Waveform format because GTK wave the visualization tool can work with that and many other formats So that's the GHDL. There is also a ventilator that one translate the very long I believe into C++ Except that the verilog parser is not as complete as the Icarus one So I'll just just mention it very quickly here that it exists and I'll go I will move on to today Icarus verilog so this one is primarily simulation and Translation tool I would like to talk about the simulation capabilities now So you provide the the Icarus with with your verilog design It will parse it the parser is extremely pedantic which is which is great It really picks out even bugs which vendor tools don't show you or don't warn you about So definitely use that It doesn't compile the the verilog into a native code instead It produces some sort of intermediate VVP code and this is then interpreted by a tool which is part of the Icarus suit VVP tool To provide to produce the the output of the simulation You can also visualize the output of from the from the Icarus verilog using the GTK wave tool The website is at the following link Now let's do demo. So how do you write a test bench for your design using? Icarus verilog. It's actually pretty simple So you define your signals in in the test bench the name of the test bench module is stop TV It has no signals because it's a test bench then in the next step you instantiate your Module which you want to simulate in my case I just put everything into the top and I will be using the great counter demo here So I instantiate that connect the signals into this this top module And then finally I perform the simulation step now This is the actual Piece of code which describes the simulation so first of all I specify where I want to dump the result of the Simulation and I set my clock to zero and then I toggle the clock 1,000 times and To perform the simulation I first have to translate this to simulate this test bench into the VVP Intermediate code. I do that using the AVerilog tool. I Use both of the test bench source and the original IP block source, which is the top V I use that in the osu! demo and Then I use the VVP tool to interpret the the VVP out pad I have additional parameter there for the VVP tool It's the LXT 2 This tells the VVP tool to generate The out pad in an LXT 2 format, which is a binary format the output of the simulation now The thing is by default VVP will produce a value change dump Outpad of simulation and this is like this will generate huge files Which are slow to slowly be imparsed by by the GTK wave and it's annoying to work with it's just huge So instead of that I'm using the LXT 2 format. It's binary. It's much smaller and Easier to work with You don't have to be really afraid that that is binary because it's documented. It's an open format It's just smaller by size And it can be converted to VCD if needed to be Now finally I visualize this this out pad the top TV LXT Using GTK wave and this is the out that you get if you load it into the GTK wave You can see on the on the right side the LEDs and how they are counting So that's so that's the the gray counter example I Mentioned GTK wave, so it's a visualization tool. It supports multiple formats Whatever goes out of the e-curve's better log of the GTK wave you can put into In of the GHTL then you can put it into the GTK wave and it will display that it's great And you can find it on this this website Now any questions for to the visualization part? Okay, so I have one final slide which I would like to do and then then I'll conclude the talk Why are FPGA tools so hard? I hope I gave you some some idea why there are such problems But to summarize it there's a lack of documentation of the FPGA hardware itself the bit stream is undocumented It's like the family gold of the FPGA vendors Another thing is that Well, why you will never get an open source quarters or Vivado is that the vendors invested Arcane amount of money into fine-tuning these tools to Perfection and they they invested like both loads of money into the algorithms and they don't want to release that Which is understandable kind of and then define then there is another thing is the pushback from the IP vendors So they are afraid that if the bit stream format was documented There might be someone who would like take the FPGA content and the reverse engineer their precious Tested IP core from that and convert it back into the arrow lock without paying for it So these are I believe that the three main reasons why? FPGA tool the FPGA tools which are open source are so problematic and so much so suffering and This is where I would conclude the talk. So do you have any questions? Yes Yes, their sales have been skyrocketing on this small FPGA that's true Let us I believe they don't they didn't react on that particular one, but The IP vendors did actually react slightly and have been bombarding the project at times with These this exact problem that they are afraid someone might steal their IP Although I don't think this is This this makes sense because if you wanted to steal someone's IP from the FPGA You would have to put so much work into going from the IP all the way to any sort of HDL That it's not worth it. It makes much more sense to just write it from scratch Thank you for the question. Yes So in case you're doing FPGA design on huge FPGAs it takes a lot of time, right? So there is a lot of heuristics in that in the place in the root step, which is I believe NP complete problem or NP hard even so there's a lot of heuristics which allow you to do it kind of efficiently and kind of well That's correct. I mean the FPGA technology is kind of extremely simple thing Sure, you have some specialty blocks in the FPGA but The bulk of the FPGA is the fabric and this is really not such a difficult thing It's just a collection of lookup tables and registers Copied multiple times over and connected with a programmable interconnect and that's really it Doesn't answer your questions. Thanks Anymore question? Yes so the question is or well the comment is that The same guy who's been doing the ice storm work work is now working on the Xilinx 7 series documentation a Bitstream documentation and the question was whether I know someone doing anything on Altera while yes, there is ongoing work on the older Altera FPGAs it is not exactly public yet and In case there is interest I guess I can hook you up if you are interested in helping the project on the Altera side. Yes Does it answer your question? Thank you Anymore questions? All right. Thank you for your attention and enjoy the end game