 today's lecture on MIPS ISA and processor. So, in two lectures I shall cover this topic. In the last lecture I have discussed in detail what do you mean by instruction set architecture. We have seen that the various components of a instruction set architecture and that instruction set architecture acts as a specification for the design of processor. So, today I shall introduce to you one processor that is known as MIPS. Do not confuse with MIPS that is million instructions per second that is different. This MIPS is the name of the processor. So, I shall introduce to you the instruction set architecture and then I shall discuss how you can realize the processor using that instruction set architecture as an input as a as a specification. So, as I told the various components that you require for storing data number one is registers. So, MIPS has got 32 architected 32 bit registers. We shall see these 32 bit 32 32 bit registers are used for different purposes and effective use of the registers is key to program performance because how you are able to exploit, how you are able to utilize this register will play a very important role in deciding the performance of the program that you write. And then you have to see the data transfer. We have seen that 32 words in registers and then millions of words in main memory. So, you will see it has got it the MIPS has got 32 bit address and as a consequence the number of words I mean it is again byte addressable and the 32 is the size of the main memory and instruction accesses memory via memory address and address indexes memory a large single dimensional array. That means the memory is accessed as a large single dimensional array and for that purpose you have to do some kind of alignment. Alignment is most architectures address individual bytes as I told like any other processor MIPS also is byte addressable. Now, whenever you do make it byte addressable your word size is now 4 bytes. So, there will be 4 bytes present in a single word. How do you really use the convention of aligning the bytes for example, this will definitely be the least significant bit and this is the most significant bit. Now this can be byte 0, this can be byte 1, this can be byte 2 and this can be byte 3 and this is this approach is known as big endian. And there is another possibility of course in this case this is the first byte second byte will be like this. That means it will again start with 0 1 2 3 and byte 4 will be here in the second word and byte 5, byte 6 and byte 7. So, this is your big endian approach. There is another approach which is known as little endian in which case these 4 bytes are aligned in a little different way. For example, what will be done there here it will be byte 0, this will be byte 1, this will be byte 2 and this will be byte 3. So, this is the LSB and this is the MSB. So, this is known as the little endian approach. So, these 2 conventions are used, but as you can see in case of your MIPS they are using big endian approach. So, addresses of sequential words differed by 4. Obviously, 0 1 2 3 then the second one will be start from 7. So, that means this will start from 0 and this will start with 4. So, this is and words must always start at addresses that are multiple of 4. Because of this obviously the addresses will be start at multiple of 4 that means 4n, 4n plus 1, 4n plus 2, 4n plus 3. So, n can vary from 0 to something whenever you are accessing different addresses of the memory different words of the memory. Now, as I told there are 32 bit registers and they are architected in a different way as you can see they perform different purposes. For example, r 0 is always 0 you may be asking what is the fun of putting all 0 in a particular register. The reason for doing it you see there will be many situations where you have to initialize either a memory location or a register with 0 when you do housekeeping of a loop or there are many situations. So, this will help you to write 0 in a particular memory location or in a register very quickly because already 0 is written in a register. So, if you copy that value into another register it will take very small time. On the other hand if you write 0 I mean if you read 0 by using immediate addressing then you try to do that it will take longer time. So, that is the reason why a register is explicitly assigned with a value 0 and which can be used in many situations. Then register r 1 is reserved for assembler r 2 and r 3 are the function return values. You will see that registers are used for parameter passing whenever you do subroutine or function calls. So, r 2 and r 3 is used to return the values by the function or the subroutine and r 4 to r 7 they are used by the subroutine to pass parameters to the function. That means main program can pass parameter to the function using these 4 registers r 4, r 5, r 6 and r 7. Then you have got other registers like r 8 to r 15, 8, 9, 10, 11 there are 8 registers they are caller saved temporaries. So, they are used to saves temporary values in this registers then r 16 to r 23 there is call saved temporaries then r 24 to r 25 caller saved temporaries. So, you can see these registers can be used either by the main program or by the subroutine to store some temporary values and which can be which will make it very convenient to use registers for storing intermediate results. Then r 16 and r 17 are reserved for operating system and r 24 is used for global pointer and r 29 is used for stack pointer. Then r 30 is used as call saved temporaries again and r 31 is used as return address sometimes it is called r r a register r a that means the return address whenever you do subroutine call that return address has to be saved you know the program counter value has to be saved in a register in most of the situations it is saved in stack. But in this particular case it is saved in a special register that is r 31. So, return address and let us look at the different types of data types that MIPS can handle data and instructions are both represented in bits 32 bit architectures employ 32 bit instructions. So, not only your word size is 32 bit instructions are also 32 bit and all the instructions are 32 bit that means you have got a single size for instruction it is not variable length. So, it is a fixed length instruction each of 32 bit and this is one of the important characteristics of risk processors and obviously MIPS is a risk processor and as a consequence you know it uses a single format for single not format single size not variable size of instructions. And combination of field specifying operations later on I shall discuss how 32 bits have been used in different addressing modes. Then coming to the data types MIPS operates on 32 bit unsigned or 2 complement integers. So, it can perform integer processing either on unsigned data or 2 complement data then 32 bit real numbers single precision floating point and 64 bit double precision floating point real numbers then 32 bit words bytes half words can be loaded in into general purpose registers. So, we have already seen it has got a large number of general purpose registers these can be considered as general purpose registers and they can be used to save these bytes half words either 0 or sign bit expanded to field 32 bit. Now, you may be here another concept you should understand suppose your data is 8 bit now this is your 32 bit number data is 8 bit. So, this part will be filled by data what will happen to the remaining bytes whenever you store an 8 bit data in a 32 bit register because your register is 32 bit a concept known as sign extension is used as you know in case of sign 2 complement number whenever the most significant bit that is your MSB is 0 then it is a positive number MSB 0 positive number and MSB is 1 the number is negative. Now, obviously this bit will be 0 if the number is positive it is a positive integer, but what about the remaining bits? So, you have got 23 other bits what is done all these are filled up with 0s if it is a positive number on the other hand if it is a negative number then most significant bit is 1 and these are all filled up with 1s and this can be your 8 bit data. So, this concept is known as sign extension that means you are extending the sign bit to fill up the remaining bits of the data. So, if it is this is the case for when the data size is 8 bit that is byte if the data size is 16 bit that is your half word in that case also the same thing is done the concept of sign extension is used to fill up the remaining bits you may be asking why is this necessary? This is necessary because when you will be doing say addition with the help of an adder you will apply one operand to one arm another operand to another arm if this data is say 8 bit, but the adder is of 32 bit. So, obviously you cannot add an 8 bit data with another operand which is 32 bit. So, what you have to do you have to apply sign extended data to this arm so that you can apply both the operands as 32 bit and you will get a 32 bit result. So, that is the reason why sign extension is used. So, sign bit extended to fill the 32 bits now only 32 bit units can be loaded into floating point registers and 32 bit real numbers are stored in even numbered floating point registers. And 64 bit real numbers are stored in two consecutive floating point registers. So, we have seen it supports not only 32 bit single precision floating point real number, but also 64 bit double precision floating point real number and that is the reason why you will require either a single register or two registers depending on whether it is a single precision or double precision. And there is some convention for representing floating point numbers this is known as I triple E 754 standard for representing floating point numbers. I request you to recapitulate this standard of floating point numbers there you will see how it is used for example for 32 bit that is single precision it uses 8 bit exponent and 32 bit significant and for double precision it uses 11 bit exponent and 54 bit significant. So, that is how the floating point numbers are represented with the help of I triple E standard 754 floating point number that means what you are doing here you are dividing 32 bit here you have got sign bit and then 8 bit significant and the remaining sorry this is your exponent and then remaining bits are 23 bits significant. So, this is 23 this is 8 this is 1 that makes 32. So, this is how the floating point numbers are represented and the processor can do processing on the MIPS processor can do processing on these different types of data by word single double precision single precision floating point numbers and so on. So, this is the data types in MIPS and I have already explained MIPS supports byte address ability it implies that a byte is in the smallest unit that it can address and 32 bit words has to start at byte address that is multiple of 4. I have already explained thus 32 bit words address 4 n includes 4 bytes 4 n 4 n plus 1 4 n plus 2 and 4 n plus 3 and 16 bit half word to start at byte address that is multiple of 2. Thus the 16 bit word address 2 n includes 2 bytes address 2 n and 2 n plus 1 and it implies that the address is given 32 bit unsigned. So, however although the address will start this way your number has to be 32 bit. Now, let us come to the instruction format I have already told that the instruction size is also 32 bit and how 32 bit instruction size has been used to represent different formats let us see and I have discussed about different addressing modes in general terms obviously all the addressing modes that I have discussed are not supported by MIPS a subset of them is supposed supported by MIPS. Let us see what are the addressing modes that is supported by MIPS with the help of different instruction format. Number one is known as R type instruction fields R type stands for register types that means your operands are in the registers and here you can see the 6 bit is the off code field operation code and then R s R t these are the two first and second register source of operands. So, that means you will get two operands from two registers R s and R t those R s and R t can be those 32 bit one of the I mean two of the 32 bit registers that I have already discussed and R d is again another general purpose is the destination register address where the result will be stored and this the shift amount for shift instruction this one is only used when you are performing shifting. So, you can not only do shifting by one bit you can shift you can shift a number is there you can shift by two bits by four bits by eight bits that can be done with the help of five bit number that can be specified by the five bit number. So, we can shift up to 32 bit and as you can see this is the shift amount which is provided as part of this instruction, but this is applicable only when you are using shift instructions. So, this field is not used for all other instructions it is used only for shift instructions then function specifies a variant of the operation called function code. So, it is normally not used, but only in case of special situations this is used this is one type of instruction format second type of instruction format is known as I type instruction format. So, in case of I type instruction format as you can see your op code part is remaining six bit and you have got two registers where the operands are available that is five bit is available here five bit is available here then this will represent some memory address and we shall see how different addressing modes are implemented with the help of this I shall come to this again. So, how this instruction format is used to generate a memory address with the help of this 16 bit then there is a J type instruction field in which you have got six bit op code followed by 26 bit address. So, it has got only three types of instruction formats, but all of them are of 32 bit R type I type and J type. So, their different fields are shown here and we shall see how they are used to generate the effective address in different situations. For example, register addressing in case of register addressing these three registers are really performing the source of operands and destination of results that means R s is the source of operands. So, it is pointing to one of the registers. So, you have got a 32 bit register file. So, it will point to one of the registers for example, it can be S 2 dollar S 2 that is one register dollar S 0 dollar S 1 that means, the you can add the content of S 0 S 2 and S 1 S 0 and S 2 and store the result in S 1. So, that will be the register addressing. So, where all the operands are involving registers and obviously, here you are using R type instruction format then coming to base or displacement addressing as you can see here operand is at memory location whose address is some of the register and constant. So, here that 16 bit address field 16 bit you know the in this format we have seen 16 bit is provided here that 16 bit is added with the content of a register that is your base register. So, it is called the base register S or displacement addressing. So, there is a base register S 0 which is used. So, here you are using S 0, but you can use some other registers then you are using this load word dollar S 1. So, in you are loading the value of the I mean content of a memory location into a register S 1. So, this is a essentially load instruction and load instruction will load some value from memory and it will load into a register and you can see the addressing how the effective address is generated. Effective address is generated by adding the content of a register with this displacement which is provided as part of the instruction. Now, let us come to immediate addressing as you know in immediate addressing you provide the operand as part of the instruction. So, operand is constant within instruction. So, it is add I stands for immediate dollar S 1 comma dollar S 0 comma 4. So, 4 is the 4 is the constant. So, you are adding the content of a register and this is this is and then you will be storing the result in the memory in the register itself. So, this is immediate addressing. So, we have seen that R S R T and this part is the that constant value that is provided. Then you can have PC relative addressing. Relative addressing is very useful particularly in situations where you will be doing let us say jump branch this type of instructions. For example, branch if equal that means, if the content of S 0 and S 1 are same you will branch to a memory location where that 16 which is provided here that as here I mean as part of the instruction that will be added with the content of the program counter to generate the effective address and you will branch to the memory location that is content of PC plus 16. 16 is provided here I mean as part of the instruction. So, this is how PC relative addressing is used to generate the effective address with respect to the program counter. So, this is useful for you know in whenever you are writing loops a program will be looping within a from one location to another. So, with respect to the present value of program counter you can specify the displacement and accordingly it will be doing the looping. Then it has got pseudo direct addressing. So, pseudo direct addressing why it is called pseudo direct addressing as you know in direct addressing that address has to be full address in this particular case full address is 32 bit. So, but you know that we do not want to increase the size of the instruction beyond 32 bit. So, off code you have to leave 6 bit for off code. So, you are left with only 26 bit. So, you have got addresses is 26 bit of constant within instruction is concatenated with the 6 bit of the program counter. So, the 6 bit that 26 bit is concatenated with the program counter value 6 bit of the program counter that most significant 6 bits will come from the program counter that is called concatenation and remaining 26 bit will be taken from the instruction that will generate defective address. So, this is how that pseudo direct instruction addressing is done. Now, let us look at the survey of MIP instruction set I have discussed about the various data types I have discussed about the different instruction formats I have different I have discussed about the various addressing modes. And let us discuss some representative instructions and from the instruction set for example, addition add simple add with overflow detected add you overflow and detected. So, you can perform addition without detecting overflow and you can perform addition without detecting overflow. Similarly, you can do subtraction overflow detected and subtraction without detection of the overflow. Then you can add with some immediate data as I have already told and that also you have got two variation addition with a constant with overflow detected or addition with a constant immediate value with overflow and detected. So, these are various arithmetic operations, but this is not the all these are some of the representative you have got multiply and divide in a similar way multiply sign product and multiply unsigned product. So, here you will see that you will you will require two registers that means, S 2 and S 3. So, S 2 and S 3 are having the operands and result will be stored in S 2 and S 3, because your result will be 64 bit whenever you multiply two 32 bit numbers you will get 64 bit signed product which will be stored in the same register S 2 and S 3 which is provided as part of the instruction. Then multiple unsigned product here it is same except you are the result is unsigned the numbers are unsigned. Then you can do division again it will involve two register S 2 and S 3 and you will be dividing that S 2 by S 3. So, your high that high higher by it will be dollar S 2 mod S 3. So, this is how it will will be perform the division then division unsigned will be done in the similar way. Then there are some ancillary instruction M F H I is just essentially to get a copy high get copy of high that means, you are higher order bits are getting copied or lower order bits are getting copied. So, these are some ancillary instructions. So, these are the arithmetic group then you have got logical group and or so it is it will perform bit wide and operation on the content of registers S S 1 and S 2 and sorry S 2 and S 3 result will be stored in S 1 or dollar S 1 S 2 and S 3 that is here it is operation or dollar S 1 comma dollar S 2 comma dollar S 3 it means that it will perform bit wise or operation of the content of dollar S 2 and S 3 and result will be stored in S 1 register S 1. So, bit wise and or you can perform addition with immediate data again it will perform bit wise and operation with the content of a with the value that is provided as constant you will be using here I type instruction format. So, this 100 is the U is provided as part of the instruction and it will do bit wise and operation store the result in S 1. So, and with the content of S 2 and result is stored in S 1 similarly or immediate you can do dollar S 1 comma dollar S 2 comma 100 is the constant and that is provided as part of the instruction. So, you will be doing content of S 2 will be odd with bit wise or operation with 100 obviously, in sign extended form and then it will store the result in S 1 and you can do the shifting and here you may recall that 5 bits were used explicitly left for shifting operation. So, here you can do the shifting. So, this 10 that 5 bit is representing 10. So, you are doing the shifting of the content of S 2 by 10 bit and shift left you are doing and store you will store the result in S 1. Similarly, here that 5 bit will is providing 10. So, it will do the shifting right shifting of the content of S 2 and then it will store the result in S 1. So, these are the logical operations and then apart from those are data manipulation instructions. So, in arithmetic and logical operations are data manipulation group instructions and then you can do data transfer. Data transfer is essentially between memory to load and store that means, from load means you will be loading the value from a memory location to a register and store is you will be storing the value from a register to a memory location. So, you have explicit load store instructions and so load dollar S 1 comma 100 and within bracket dollar S 2 that implies that your the content of S 1 will be taken from the memory location. Effective address is generated by adding the content of register S 2 and adding that 100. 100 is that 16 bit that is provided by using that I type instruction format. So, this is the load word and this is load byte you can load a byte same way and memory location is specified in the same manner. Similarly, you can perform load upper immediate. So, lower and upper so that means, here you can load a byte you can load 16 bit you can load full word. So, all the three are provided in this manner. So, here it is load upper immediate you can do lower load lower immediate also there is another instruction. Then store operations you can do store the content of a register into a memory location. And here it is again using that I type instruction format. So, the content of S 1 is stored in the memory location by obtained by adding the content of S 2 with 100. 100 is provided as part of the instruction as immediate data. Then you can do the byte storing here it is word storing here it is byte storing. Then you will be having several control transfer operations like jump branch. So, jump 2500 go to 10000. So, you have to multiply with 4 we have seen these are byte addressable. That is why you are multiplying 2500 with 4 to go to the memory location. Then jump this is a procedure call to again you are performing PC plus 4. So, jump it is a procedure call go to 10000 jump at memory location provided by PC plus 4. So, r a you can see that last register one that last is the r 31 that is your acting as a return address. So, you are adding the PC plus 4 into that register. So, that was that is the return address whenever you are doing a procedure call. Similarly, here also you can see go to return address for procedure return. So, that register r 31 is providing you the where the content of the program counter is stored whenever you are performing subroutine call and whenever you will be returning that time that value is taken from that register to jump to that memory location. So, it is not taken normally you know in many microprocessors it is taken from stack. So, it is stored in stack, but instead of using stack here it is using a special register which is part of an instruction. Then you can perform various comparison operations you can do. So, different types of comparison operations unsigned and so on. So, later on I shall give you some assignment for writing program in a similar language of MIPS. So, you have to know about various addressing modes different types of instruction. So, when you will be writing program in a similar language of MIPS then it will it can perform various floating point operations. So, various arithmetic operations single precision and double precision and floating point registers are used in even odd pairs whenever you are using double precision you will be requiring two registers. So, if you not pairs are used and using even number register as its name. So, you have to give the name of a register, but it will involve two registers. Similarly, you can do data transfer involving floating point operation. So, transfer data to and from floating point register file that can be done and conditional branch can also be done based on floating point result. So, depending on this operation whether the condition is satisfied or not branch will take place or not. So, this type of different conditional branches involving floating point operation is also provided as part of the instructions. Now, so far what I have done I have introduced to you instruction set architecture. Now, what I shall do we have to design a processor which will implement the instructions that I have discussed. So, I shall discuss about MIPS instruction set processor and here is the different points that you have to remember. First of all starting point is the specification of the MIPS instruction set drives the design of the hardware. As I have already told the instruction set architecture acts as a specification and that you have to deal the processor designer has to use those instructions to implement the processor. Second is and of course to make the design simpler we shall restrict to integer type of instructions. We have already seen MIPS will MIPS provides you floating point operations. So, floating point we are not considering for the purpose of implementation to make them to make the life simpler we have only we shall only take into consideration integer type of operations not floating point. Then identify common functions of all instructions and within instruction classes and whenever you realize a hardware you have to do kind of optimizations and that is the reason you have to do you have to identify common functions to all instructions and within instruction classes. So, that you can do instruction fetch access one or more registers use ALU. So, particularly by using risk architecture it is easy to identify the commonality of the instructions and the various instruction classes and that will help you in simplifying the implementation otherwise you know if it is not a risk processor if it is a SISC processor that implementation of the instructions with variable addressing I mean variable instruction format, variable length of instructions and with a variety of addressing modes it is extremely difficult. Then asserted signals a high or low level of a signal which implies a logically true condition and action level that means here by this statement all I am trying to tell that the signals are high active you know you can be you can make it low active you can make high active. Suppose this is your processor there is a input and that input whenever it is high active it is represented in this way on the other hand whenever it is low active it is represented in this way there is a circle here. So, in this particular case it is assumed that the inputs are the signals are high active that means you will be using this kind of convention in whenever you will be generating signals. So, instead of making it low active then coming to the clocking we shall assume that the we are using edge triggered clocking as opposed to level sensitive you know by clock we mean this type of signal which will be generated by a clock generator it can be a crystal controlled oscillator which will generate a fixed clock. Now, it can be either level sensitive or it can be edge sensitive in our case it will be assumed that this is edge sensitive that means all the changes will be taking place at these edges. So, this is edge sensitive because these conventions on our assumptions are very important whenever you do design a circuit because you have to use different components like flip flops they have to edge triggered flip flops not level sensitive flip flops. So, a storage circuit of flip flops stores a value on the clock transition edge as I have already told model is flip flop with combinational logic between them. So, model is here you have got some combinational logic and here you have got flip flop or storage element on either side. So, your input is coming from flip flop combinational circuit will be performing different things that is your processor that we shall realize and store the result in flip flop and that will be done in one clock cycles. So, right now we shall assume single clock cycle that means this combinational circuit delay of this will be such that it will be one clock cycle delay of this circuit will be same as this that means the clock frequency cannot exceed this if this is the time period clock frequency cannot exceed 1 by t because that is the delay of the combinational logic. If you use higher clock frequency then you will get incorrect result here. So, that is the assumption being made propagation delay through combinational logic between storage element determines the clock cycle length. Then single clock cycle versus multiple clock cycle this part I shall discuss here we are restricting to single clock cycle design you can design the processor using multiple clock cycles and how it can be done I shall explain later, but for the time being we are assuming that it is a single clock cycle based. Now, we are starting with single clock cycle long clock cycle for each instruction that means to perform each instruction irrespective of the type whether it is a data manipulation or data transfer or branch or control transfer whatever it may be all instructions we are assuming that they will perform in a single clock cycle and entire instruction gets executed in a single clock pulse controller is pure combinational logic because since it is done in a single cycle. So, clock controller is a single pure combinational logic and this is done to make the design simple later on you know when we shall be considering other things like pipelining more complex things then you shall see design will be quite complex, but as a starting point to make the life simpler we are assuming that it is single clock cycle. Now, you may think that a single clock cycle instruction execution would give us super high performance, but not so what I am trying to tell you may assume that since everything each instruction is executed in a single clock cycle we shall get very good performance, but unfortunately that is not true reason for that is the clock cycle frequency this time period of the clock will be determined by the worst case delay of an instruction. Suppose, you have got different instructions of different kinds and each of them will take different time to perform for example, if it is a simple data manipulation then for example, that the register adding the content of register and storing the value in another register that may take some time. However, when we will be reading say load store type of instruction you have to either load some value from memory to a register or store some value from register to a memory. So, when it will involve memory it will take longer time. So, instructions are not of equal length in the sense execution time will be different and your clock frequency f will be restricted f clock has to be less than the f you know that worst case instruction. In other words the slowest instruction will decide the clock frequency. So, you are not really achieving a much and as a consequence you know the slowest instruction determines speed of all instructions and because various phases of instruction need same hardware. Another important aspect is you know since you are doing everything in one cycle you will require more hardware. If you do in multiple cycles then there is a possibility of reusing some of the functional units for different purposes. For example, for the calculation of address for the performing addition. So, these things can be done by using a single functional unit adder whenever you use multiple clock cycle. But if you use single clock cycle since it is done in one go you have to duplicate adders and you will see the redundancy will be more that means some hardware is redundant another disadvantage of single phase. For example, we shall be using two separate memories one is your instruction memory another is your data memory. One memory from where your instructions will be fetched another memory from where data will be fetched whenever you are performing load and store. So, if you use multiple cycle multi cycle design then you can have a single memory. But whenever it is a single cycle design you have to use two separate memories because you have to fetch instruction and also load or store data. So, you have to in a single cycle. So, two separate memories will be required and as I have already told two adders in the ALU. So, here is our design summary it has some performance bottleneck the CPU cycle time is determined by the longest part of the machine. The simple jump instruction will take as long as load word the instruction which uses the longest data path dictates the time for all others. So, the slowest slowest instruction will decide the clock frequency what about variable time clock design. So, to overcome that there is one possibility what is that is your variable time clock. So, earlier we have assumed that each clock is of same duration this one this one all are of same duration. Instead of that suppose if you are performing instruction which takes smaller time. So, this is your clock cycle if it takes longer time the clock cycle can be like this. If it takes still longer time the clock cycle can be like this. If it takes smaller time another clock cycle smaller duration. So, what you are trying to do you will be generating clock cycles of different time period. So, this is variable time clock. So, if you do that you are performing each instruction in a single cycle, but each clock cycle is of different duration you may be asking why not use this, but this will definitely complicate the design of the clock circuit. Because normally you know you are using a crystal oscillator. So, which will generate a fixed frequency, but whenever you go for this kind of variable clock then the clock frequency is not fixed. So, your clock clock generator circuit will be very complicated and also you have to identify what will be your exact timings. So, clock pulse interval is a function of the off code. So, off code will decide what will be the duration of this clock t 1 or t 2 or t 3. So, this will be decided by the off code that means after you read the off code then off code will specify that this is the clock frequency for this particular instruction and accordingly clock has to be generated. So, this will make the design pretty complex. So, let us start simple with a single clock cycle design for simplicity reasons and later consider multiple clock cycle and incorporate more complexity like pipelining and other things. So, with this let us stop here and we shall resume our discussion on the processor design in the next class. Thank you.