 Hello everyone, welcome to lecture on VHDL module for multiplexer and demultiplexer. At the end of the session students will be able to analyze, design and implement multiplexer and demultiplexer. Now before starting with the actual section, let us pause the video and think about what is a sequential statement. So, those are nothing but the F statements, K statements and loop statements. Those statements are must be written in the inside the process because those statements are going to be executed sequentially one after another. Now this is the 8S to 1 multiplexer, you can see over here 8S to 1 means 8 inputs are there, 1 output right. So, here 8 inputs i 0, i 1, i 2, 2, i 7, 1 output is Z to select any 1 input to the output we required select lines. So, here S is a select line which is having 3 bits in A. Now because of the 8 inputs are there, we required 3 select lines, so which is calculated with the help of 2 raise to n equals to m. Now here m is nothing but your number of inputs, so to validate that 2 raise to n equals to 8, we required n equals to 3, so 2 raise to 3 equals to 8. So, from that formula you can find out how many select lines should be there in a design for particular inputs. So, for 8 inputs we required 3 select lines and 1 output right, so this is 8S to 1 box. Now this is the VHDL module for 8S to 1 multiplexer. Now first two lines are supposed to be compulsory lines which are must be written in a code that is library declaration over there which library you are using and which packages you are using. So, we are using library IEEE and from that library we are using package IEEE dot STD logic 1164, this is the package right and from that package we are using all comms right. After that second main part of the VHDL module is entity, so here entity name we are writing for 8S to 1 multiplexer, so mux 8 is in the entity we have to write the port declaration, port declaration which specify or gives the description about what are the inputs and what are the outputs to your device or system. So, we already saw that in 8S to 1 multiplexer 8 inputs are there and 1 output plus additionally 3 input select lines right, so I0 to I7 are the input which is the type of bit then after that S is a select line which is a type of bit vector, this is a syntax to define or write a vector signal which is having multiple bits in that, so S is a type of vector 2 down to 0, this is a one type or syntax you can declare vector as a 2 down to 0 or you can write 0 to 2 either way possible. After that you have Z is output which is also type bit single bit value it is there, so that is why it is bit, this one is a multi bit value signal, so that is why it is a bit vector right, then entity n after that comes architecture part, architecture name of entity name this entity name we have to use over here then begin. Now, in the architecture we have to write the behavior of our design right, so 8S to 1 we are writing, so we have to use the sequential statements, so for that we need a process, so process after begin architecture begin process is there. In the process inside the bracket we have to write the sensitivity list, sensitivity list is nothing but the signal which are going to affect the execution of your output system design right, so process then sensitivity list in that we having signals i 0 i 1 2 i 7 and also select line which going to affect the output right. After that process begin then because of 8 inputs available and depending on the combination of 3 select lines 3 bit select line we going to say get the output, so for that we using case statement, so case signal S for S signal we having 3 bit, so we have 8 possible combinations, so case S is when it is 0 0 0 means 3 bits of S signals are 0 0 0, in that case Z means output is equals to i 0, so i 0 is going to be connected to output when the select line having all the 3 bits are 0. Similarly, when the select line having 0 0 1 in that case Z is equals to i 1, so this is the syntax for assigning right and this is the syntax may you have to use when you are using a case statement right. So, this is the second case similarly you can write for remaining possible combinations, so 8 combinations are there up to 1 1 1 output Z equals to i 7. If the select line is not having from this possible combination it is not 0 0 0 it is not 0 0 1 it is not 1 0 0 it is not 1 1 it is not among these combination other than these combination, in that case we have to write one more that is when others my Z is equals to 0, so 0 directly assign to the output. After that you have to end the case, so end case, once you done with the case statement then you have to end the process, so because we started process here, so end process then after you have to write the end architecture right. So, this is the VHDL module for 8S to 1 multiplexer, this module can be verified with the help of simulation, so to write the VHDL module I use the Xilin software and for to verify I use the simulation which is having in build in the Xilin that is called iSIM simulator. So, this is the output for your 8S to 1 multiplexer, so here you can see that when all inputs having value 0, but the select line is 0 0 0 means first input is connected, so output to the output, equals Z equals to 0 in this case, here the values those are showed whatever the where the cursor it is, so do not get confused. If you consider this situation over here input all inputs are 0 and the select lines are 0 0 0 over here that is why the output get connected to the i0, now the select lines still 0 all bits are 0, but the input I made over here is 1 i0, so that 1 is reflected at the output same if I change now select lines from 0 0 0 to 0 0 1 and still I am having i0 input signal is 1 remaining 0 and the output is still get connected to the now because of the select line is 0 0 1 it get connected to the i1, so i1 is 0, so that is why the output is 0, now still select line having 0 0 0 0 1, now I made i1 1, so output changed to i1 right 1, so this is how you can verify the VHDM module whatever you created for the your design with the help of simulation using this waveforms. Now, let us go for the multiplexer, so now we just studied the attest to 1 multiplexer, now let us go for the 1s to 8 demultiplexer, this is the demultiplexer 1s to 8 which is having 1 input and 8 output reverse version of your multiplexer, in the multiplexer you are having 8 inputs 1 output here you are having 1 input 8 output remaining working is same 3 select lines and additional part is clock is there instead of clock it is mentioned as G right. So, let us go for the VHDM module same first two lines are library include declaration then entity part here now the input is single only one, so and one clock is there, so it is type of bit again S signal which is a type of vector, so 2 down to 0 3 bits 8 outputs, so out 0 to out 7 out type is of again bit entity ends now architecture architecture begin again process here single input signal bit signal S and I right. Now, here we have clocked included G as a clock, so if G equals to 0 means whenever they my clock signal is 0 then and then I am having the further processing, so in that again case statement now depending on the combination of select line we have 8 different combinations and my output will be connected to the input line. So, which output is connected that depends on the combination of S signal, so out 0 is your input is going to be connected to out 0 when the select line is having 0 0 0 input is connected to out 6 line when the S signal having combination 1 1 0 after that once you done with all the combinations of your case statement end case then end if after that end process and end architecture right. Now, this is the simulation output for 1 is to 8 d multiplexer you can verify that with the help of this way of forms now depending on the select line these bits here input is going to be connected to 1 of the output. So, now here it is 0 0 0, so because that it is get connected to 0 now input becomes 1, so input get connected to this out 0 because still as bit is having 0 0 0 these are the references. Thank you.