 In the last class, you know, we had just talked with the slide on the periodic table of materials and I had mentioned that if you are to ask somebody may be 10 years ago, you know, what are the ingredients of the silicon chip, you would probably see just a handful of materials as is indicated here. Silicon of course, is a group 4 semiconductor and in addition you would need arsenic and phosphorus to dope it n type and boron to dope it p type right. And of course, you would need oxide because we have been talking about FET structure, you need a silicon oxide as a gate insulator and also you would need oxide for isolation and so on and so forth right. And once you complete your transistors, you need to connect them. So, you would certainly have aluminum as an interconnect layer right and you know hydrogen is a lightest element no matter what you do, you will always have hydrogen and it turns out we also intentionally introduce hydrogen in our silicon technology to do what is called surface passivation of silicon. In other words, when you put oxide on silicon you see it is a it is a system of two different materials, when you go from one material to the other material at the interface you have lot of defects right. By having hydrogen out there, hydrogen can passivate these defects which are essentially dangling bonds of silicon which are unterminated bonds and hydrogen would minimize the defects which is extremely important in a field effect transistor because interface is the key in a FET device right. And you know once you complete your chip, you passivate the chip with what is called a silicon nitride and hence you will have also nitrogen in it and when you put it in package you will probably have gold wires connecting the silicon pads on to the package pins right. So, this was very simple just handful of materials were ingredients of your silicon chip. However, the world has changed completely now you know if you were to ask the same question what is the ingredient of a silicon chip today you will see you know a plethora of materials in a state of the art silicon chip today right. As an example for example, you know in addition to the doping materials which were phosphorus and arsenic we are also using antimony as a doping material right. We are also using indium as a doping material right and you know for metallization we are using a variety of materials as well for example, copper is replacing aluminum right. So, similarly there are reasons why we introduce a variety of materials in fact it is fair to say that we are sort of digging through the periodic table it is sort of an exploration in periodic table to really build nano electronics chips. In fact as you know the course is titled nano electronics devices and materials in fact as we go on in future lectures we will also understand why some of these materials are being introduced right. This is very crucial right. So, an appreciation for materials technology is very important new device structures are also very essential going forward right. This is our you know conventional MOS structure metal oxide semiconductor field effect transistor right. And as I have already mentioned what we have done over the years when we have been scaling the technology is really to you know scale this gate length you know the length between this the distance between the source terminal and the drain terminal that is your gate length. In other words typically in a n channel transistor the source terminal is at ground potential and you would be applying your drain voltage which is positive voltage to the drain terminal right. Now what is happening with scaling is that this drain terminal is coming closer and closer to the source this is what we call a proximity effect right. I mean we need to consider the two dimensional distribution of electric field in other words the drain electric field has started influencing the behavior of the transistor out here even without the gate being there to turn on the transistor meaning ideally when the gate voltage is 0 right your v g equal to 0 should corresponds to very very ideally 0 current, but you never get to 0 current nonetheless very small current should be out there. But because of this proximity effect you have very significant leakage current you know it is becoming harder and harder to turn off a transistor to turn off an FET as we are scaling the dimensions of the FET right. One of the important abstraction if you recall we said transistor is a switch right I mean for it to act as a switch ideally it should have a large on current and very small off current in other words one of the very important metric of transistor is what we call I on over I off ratio. Ideally we want it to be infinity right meaning I off should be 0 typically for a given on current, but of course you know you cannot get a infinite on to off current ratio, but traditionally in the past we have been easily getting on to off current ratio which is of the order of 10 power 6 a million times on current is a million times more than off current which is a fairly a good abstraction of a switch right. Because when it is on it is conducting 10 I mean 10 to the 6 times current when it is off right, but now you see this has started coming down as we are starting to move this down you know it could come down as low as 10 to the 3 or even less than that. Now imagine if your on current is only 100 times greater than your off current you know that is not a very good abstraction of a switch you see. So, in other words we need to do something out here something in this transistor structure. So, that we can bring this on to off current ratio back to reasonable number you know 10 to the 4, 10 to the 5 that kind of a thing right. We can do that only by using new device structures and hence as we will go on in the course we will also see how do we engineer these transistors. So, that we can really get a better transistor right in spite of the fact that we are scaling we are bringing this drain voltage closer to the source terminal right. So, that is a very important challenge that we need to deal with right. So, in addition to all this you know there is something interesting that also comes about. In other words when we start scaling these dimensions to nano scale you know some physical properties themselves start changing. You see for example we have been building chips on silicon as I said you know we call it bulk silicon right bulk silicon essentially means that you know you have fairly thick silicon film. Now today we are talking of building chips in silicon film which could be as thin as of the order of you know less than 50 nanometer you know that is ultra thin film. Now as we start thinning down it further right the properties of this silicon film which is a nano silicon film are no longer the same as the properties of a bulk silicon film right. The physics changes at this nano scale for example the band gap is no longer the same as the thick silicon film. If the band gap changes obviously you would expect all the semiconducting properties would change like carrier concentration so on and so forth right. So, that is something that we also need to understand and you know accordingly design of course you cannot get rid of quantum effects right. The size effect is essentially coming because of quantization but we will exploit those effects and intelligently devise and design the transistors right. So, that we would be able to scale the technology further ok. So, then characterization is also very important right you have made something and you need to really see if you have tried to make a transistor which is 40 nanometer after doing all the processes in your nano fab have you actually got 40 nanometer right. You need to do lot of characterization material characterization devise characterization and so on and so forth. We will also have quite a bit of discussion in this course on material characterization which includes measuring dimensions right whether it is 40 nanometers 35 nanometers and so on and so forth. Composition if you are making a new material you know what is the composition of that material right we will have techniques to really investigate that right. Stresses become extremely important right you have multiple materials stuck together there you know thermal expansion coefficients are not going to be identical right. So, hence there will be stresses that will be developed in these materials and they could have significant impact on the device sometimes detrimental on the other hand we can also exploit these stresses for our benefit and design devices intelligently as we will see later right. We actually do strain engineering and you know get better devices right and of course you know in terms of IV characterization eventually your electrical property is what is important when you use it in circuits right. So, such as current voltage and capacitance voltage characteristic and reliability of the device will it operate only today or it will sustain all the harsh environments for next 5 to 10 years you know that becomes extremely important right. So, we will have a discussion on all these aspects as well right and also when we talk of various processing right. You know there are two ways you can approach nano dimension right one is what is called top down approach that is you start from large dimensions and start etching materials that you do not want and bring it down to the nano scale right. So, that is what we call top down or shrink down approach which is also sometimes called subtractive approach because you are trying to get rid of films that you do not want and the key enabler here is photolithography right using that we create these devices. There is another approach that chemists have been working on this kind of approach you bring atoms together and you get a new product right that is assembling the atoms right from the atomic scale you can reach the nano dimension right. So, these are the two ways you can arrive at nano devices, but as of today you know we have no clue yet although there is lot of research going on in figuring out how to really create technologies the so called self assembly technology to create nano devices. If we do that that would really be disruptive technology biology builds the network big systems like that right, but all the technology that we have been building is essentially shrink down technology right. So, all the processes that we are going to discuss in this course is only going to be restricted on this there may be a very brief mention on you know self assembly kind of technology right. So, that you know you know where we are heading and you know these devices these chips are essentially made in facilities that are called nano fabrication facilities right which is essentially a clean room right clean room means that you know this is an area where we have extremely fine control on environmental parameters right. The environmental parameters include the dust particle in that room for example, we say that a clean room typically is a class 100 or class 10 clean room. What it means is that in that if it is a class 100 clean room if I take one cubic foot of air volume in that room and if I start counting particles of size 0.5 micron and above I should not count more than 100 particles then it qualifies as class 100 clean room just to give you a proper context a typical air conditioned office room may be class 1 million room meaning you will easily count a million particles right. So, you will have to go through a very elaborate process to filter out all that and create a clean environment right and in addition there will be very strict temperature and humidity consideration right. This is important because only when you do that you will get very high yield what we mean by yield here is if I make 1000 chips out of 1000 how many are working chips right that is what we mean by yield 100 percent yield is what we always aim for right. If you have defects for example, if you have dust particle if they sit on your silicon wafers obviously you will not get that chip in that location as a working chip right. So, that is as simple as that right so this ends to just set the expectations for this course you will gain a very thorough understanding of CMOS scaling issues. In fact we will get started on CMOS scaling immediately after this slide and you will also understand the state of the art process flow how does one put together different semiconductor processes. In other words what is called process integration to be able to create a state of the art CMOS technology right. You will also understand that through this course and you will also understand why do we need new materials and device structure I have already mentioned that very briefly, but we will take several cases and explain why do you need this right and you will also have a fairly good knowledge on design techniques to be able to do what is called a non classical CMOS transistor meaning remember the device structure I showed you earlier a simple source drain and gate structure that is what we call a classical transistor which has really worked for last four decades or so. Now we are talking of non classical CMOS transistors right. So, we will also have a fairly good idea on you know understanding the design techniques for that and hopefully you will also gain fairly good expertise in material synthesis and characterization through this course right. So, this is what we aim for through this course. So, then let us get started with the scaling and again here we are looking at CMOS technology scaling. So, you know you should look at this paper sometime you know this is of course available IEEE archives which was published in general of solid state circuits in 1974. This is a very classic paper right which is being referred whenever you talk of scaling. This was you know published by a group headed by Dennard at IBM way back in 1974 and this was essentially titled as design of ion implanted MOSFETs with very small physical dimensions right. This was as you know published in general of solid state circuits and essentially through this paper the authors present certain guidelines for scaling and also sort of explain why do you want to scale the CMOS technology. So, let us try to understand that. Now there are different kinds of scaling, but when you go through that paper you come across this term called constant electric field scaling. This is the key word here constant electric field scaling. So, what this scaling theory this is what we call ideal scaling theory for constant electric field scaling of CMOS technology. So, what it says is that you have a transistor at any given time let us say this is the state of the art technology right does not matter what dimensions are right. It has certain gate length it has certain source drain junction depth and so on and so forth and now you want to come up with a new generation of technology and that new generation of technology will have same MOSFET except that it is a miniaturized version of this transistor a smaller transistor. So, this is what we call a technology scaling starting from a bigger transistor to a smaller transistor and we define a scaling factor called k which is greater than 1. Now this constant electric field scaling theory provided 3 fundamental guidelines right which is what we call primary scaling factors or primary scaling guidelines. It says that given a transistor that you want to scale in future you scale all linear dimensions all linear dimensions no matter which area of the transistor that you are looking at by a factor 1 over k right. In other words if your transistor has a channel length l here this transistor will have a channel length which is l divided by k that is what we mean by you know scaling it by 1 over k right. Since k is greater than unity the length has come down right in a new transistor by that scaling factor k right. It turns out that you know traditionally we have used scaling factor which is about 1.4 from one technology generation to other technology generation. In other words 1 over k is approximately 0.7 it also becomes clear in a minute why we use that. You see oxide thickness essentially this is your transistor and this is your gate insulator right that is oxide thickness T ox that should also come down here by the same factor length we already talked about and the transistor has a width right in other direction right. So, the width should also scale down by the same amount right. So, that is another important parameter to think about let us see here. So, let us consider this transistor here right let say we restrict our discussion for the time being to n channel transistor right. So, this is SiO 2 and this is your gate electrode which typically is polycrystalline silicon although it has changed now we are talking of metal gate transistors today and this transistor you know will extend in this direction right because this is what we call a width of the transistor correct. So, whereas this is the length of your transistor right. So, the length will scale down by that factor and this is what we already said is T ox right oxide thickness will also scale down. So, T ox goes as T ox over k and the same thing happens to length width and also the junction depth this is what we call x j which is your junction depth. So, the junction depth will also scale down in a new transistor. So, all linear dimensions will scale down by that factor. So, that is the first point of the scaling theory right. The second point of the scaling theory is that the supply voltage also scales down by the same factor just as your linear dimensions all your linear dimensions have gone down right as 1 over k the supply voltage will also go down 1 over k. Now, you understand why is it called constant electric field scaling theory right because if your voltages are going down by a same factor distances are going down by the same factor right as a result of that your electric field which is essentially voltage divided by any distance is invariant in your original transistor and a new transistor right. So, that is the idea behind constant electric field scaling theory. Now, there is a third scaling guideline which is very interesting because in order to satisfy constant electric field scaling theory it appears that these two guidelines are more than sufficient right. But the third guideline says your doping concentrations should increase by a factor k that is all linear dimensions and supply voltages coming down. However, your doping should go up in a new transistor. Now, for example, what doping are we talking about this is anyway n plus meaning it is degenerately doped very close to the atomic density of silicon. So, there is not much we can do there we are really talking about what is called a substrate doping this is p type substrate in which we have made a n channel transistor. The doping concentration here which is designated as n a which is acceptor impurities that we have in the transistor that should go up in a new transistor as k times n a. Now, if you think about it this really comes about because of the fact that this linear dimension you see all linear dimension, but for one linear dimensions are defined by us using photolithography process like the length of the transistor you print the length of the transistor, width of the transistor you are printing the width of the transistor and so on and so forth right. The junction depth you control by how long you do the diffusion right. But there is one very important parameter which is what we call a depletion width right there is a p n junction here p n plus p junction which is what we call a one sided junction right which is n plus and this is likely doped region. And there is always going to be certain depletion width here you see this depletion width let us denote as w suffix d depletion width that is a width of the depletion region. You see this is also a linear dimension right if the scaling guideline the first guideline is to scale all linear dimension we should also enable the scaling of the depletion width right. So, how do you enable the scaling of the depletion width you see for the one sided depletion junction the depletion width is essentially given by this expression right. This is the expression for depletion width for one sided junction right epsilon silicon encompasses the free permittivity as well as the free space permittivity right. So, it is epsilon r times epsilon naught right that is the permittivity of silicon. And v is the voltage across that depletion region and n a is the doping concentration when we talk of one sided junction we are talking of doping concentration in a lightly doping junction region of the junction. Now, you see this v is scaling as 1 over k remember that the scaling guideline has already told us to scale v as 1 over k. Now, if I scale this n a as k times n a right you see then what happens in a new transistor is that you get k square under root here right q n a k square. Because you are increasing n a and you are decreasing v by the same factor which is k in other words your new transistor will now have a depletion width which is k times smaller than the previous transistor right. And hence you have been able to scale all linear dimensions consistently as per the requirement of a constant electric field scaling theory right. So, this is essentially the basis for the constant electric field scaling theory. Now, something very interesting comes out if you follow these three primary guidelines right. Now, let us first do what is called derived device behavior. If you follow that guideline what happens to the device behavior we are now looking at four important device behaviors here right. One is electric field we already said electric field is invariant it does not scale it remains same right previous electric field multiplied by 1 gives the new electric field correct. Voltage is important metric for a device we know voltage is scaling as v over k because of that your current will also scale over as sorry i over k. Now, one other very important parameter for device is a capacitance. In fact, that is the most important parameter when we talk of CMOS circuits. What is capacitance you see capacitance is again epsilon naught epsilon r times a divided by distance between you know whether it is depletion capacitance or a parallel plate capacitance it does not matter. Now, let us think about what happens to the device capacitance what is its scaling behavior right. A is area which has two linear dimensions in the numerator and D is also one linear dimension in denominator. In other words A goes down as 1 over k square and D goes down as 1 over k effectively your C will go down as 1 over k right. So, your C goes down as C over k in a new device capacitance decreased you see capacitance is like inertia for these devices. If your inertia goes down these transistor will start switching faster and faster you know that is the key. We will find out that in a minute in what is called derived circuit behavior right. Now, with this background let us look at the circuit behavior right. If I follow this what happens to your circuit. When we talk of CMOS circuit we should envision the CMOS circuit as capacitive circuits you see. For example, let me show you a very simple the simplest CMOS circuit which is an inverter which has a P channel transistor and an N channel transistor connected in series. This is VDD this is your PMOS and this is your N channel transistor and this is your output and this is your input. You see this is an inverter right that is when your input is high output is low and vice versa. But the figure of metric for us is not the steady state how long does it take to switch from one state to the other state that is your switching speed that in turn will determine your circuit speed right. Any complex circuit whether it is microprocessor or memory is all you know large number of such smaller circuits aggregated together you see. So, the switching speed is very important now when we talk of switching speed remember this circuit is going to drive a next stage of a CMOS circuit right. It does not matter what that is it could be a similar inverter or it could be a NAND gate or you know so on and so forth. In other words when we look at the input of any CMOS circuit we need we essentially see a gate capacitance right. We see a capacitive input right because it is going to the gate insulator here FET right. So, you know you have capacitance here this capacitance really has to be switched between 0 and supply voltage depending on when I am switching it from 0 to VDD or VDD to 0. In other words if my input goes from 0 to VDD then my output should go from VDD to 0 this is what I want to be able to do in CMOS circuit right. But you know there is going to be if I were to do it in a time axis if this is my input and this is my output if this input goes up at time t equal to 0 you know my output will have certain latency right it will not switch instantaneously right and this is a very crucial parameter which is typically called propagation delay. We say that in CMOS circuit the propagation delay which we also sometimes write as tau tau is given by a metric called C V over I where C is the capacitance that you are switching at any node in a CMOS circuit at any node in a CMOS circuit V is the voltage that capacitance needs to be switched you know as I said between 0 to VDD or VDD to you know ground as I mentioned already and then you know I is the current that is available for you to charge and discharge this capacitor in other words for this to go from output to go from high to low right output was high you see output was high how will it go to 0 it will go to 0 only by discharging that node through this transistor which is sitting down otherwise you cannot bring it down right and that happens because you have made this input high earlier when it was low P channel was on and hence your output was pulled up to VDD right. Now, I have switched off the P channel transistor but capacitance still has that charge you see that needs to be discharged unless you do that you would not go to 0. So, this transistor will draw out that charge and hence the current in this transistor decides what is the time it takes to discharge that right larger the current you have quicker is it to discharge and hence the discharge time is inversely proportional to current larger the capacitance more is a charge stored and hence it takes longer similarly larger the voltage more is the charge stored it takes longer to discharge the capacitor right. So, you know this is in fact you know q times i has a dimension of time right you know it is dimensionally consistent also right now this is what is the key right. Now, given this background let us now see tau is C V over i this is my delay I know that C is scaling as C over k V is scaling over V over k and i is scaling over i over k. So, what does it mean your delay goes down as k right this is amazing right what it tells you is that you do not even have to redesign any circuit you take a circuit today it could be as I said a simple inverter or a more complex microprocessor which is on a 19 nanometer technology without even redesigning you scale it down to 65 nanometer technology immediately your circuit starts operating faster of course when you go to a new generation of technology you do lot of circuit engineering redesign and also lot of system level architecting and hence your speed benefit is much more than what technology gives. But this is one of the very important reason why you want to scale the technology circuit starts operating faster, but that is not the end of the story you see in circuits speed is one important metric and power is another important metric which is V times i. So, what will happen to power V is scaling as V over k i is scaling as i over k power is scaling as P over k square right this is even better right the circuit which was operating earlier at certain frequency now operates at much higher frequency, but consuming significantly lower amount of power. So, why would you not want to do a scaling of a technology right so that is why there has been a phenomenal push towards scaling technology right. So, in fact we sort of capture this whole thing based on what is called a power delay product which is essentially P times tau you know power times delay has you know the dimension of energy you see. Now, what will happen to power delay product power is going over 1 over k square delay is going over 1 over k in other words power delay product goes as 1 over k cube right k is greater than 1. So, what it tells you is the following right energy consumed to perform any given operation is going down as k cube just by scaling the device dimension. So, this is you know very good right this is great actually and that is why we have been scaling the technology and of course what happens to the circuit density right what is circuit density the circuit density is essentially your number of transistor that you can pack per unit area correct this is your circuit density right density of the circuit. So, what happens to that remember a goes as 1 over k square and that k square comes to the numerator right. So, your circuit density goes up as k square right in other words you are able to pack more number of devices in a given area compared to what you are doing earlier right. So, this is this is what is very important to understand and also mentioned sometime some ago that typically when we are scaling the technology right the technology 1 to a technology new technology right. We have used a scaling factor which is 0.7 which is 1 over k k is 1 over 0.7 I mentioned that you know a while ago right. So, you may wonder why do we use this factor 0.7 right the idea of using this factor 0.7 is a following right you know eventually you are building a chip right you are going to scale the dimensions by a factor 0.7 in other words this dimension length and width both will come down as 0.7 in other words the area here is 50 percent lower than the area here right. Because this is 0.7 if this is x and this is x if it is square this is 0.7 x and this is 0.7 x. So, what you got here in terms of area is 0.49 x square as opposed to x square here right. So, that is a very good metric for scaling you have a chip you have reduced that area by 50 percent right. If you want to reduce it very significantly you may ask the question why not 0.3 you know 0.3 is like a you know jumping a big step you see we are at 100 nanometer technology and we want to directly go to 30 nanometer technology right you know skipping all the intermediary steps you know that is very daunting task you know it is almost impossible to do that. If you want to do that we may want to wait for 10 years right it does not make sense in this fast pace of the technology right. On the other hand why not just 0.95 because that gives a very incremental improvement right you have not really scale the technology is very significantly if you take x and scale it by 0.95 x right. Whereas you know 0.7 x historically you know we have marched along that path that has been a fairly good scaling number that we have discovered right. So, and this is what we do right. So, hence the constant electric field scaling theory gives you all these benefits and that is why we would like to scale the technology right. So, you know if you were to go by that and as I mentioned already you know your delay goes down your power goes down your power delay product goes down your circuity density goes up and so on and so forth right. So, this is a very important consideration, but it turns out if we look at the scaling we have not necessarily done constant electric field scaling right for various reasons right. Let me illustrate that to you through this typical scaling scenario right. As I mentioned this paper was published way back in 1974 during that period we had 5 micron technology which was operating at a supply voltage of 10 volt. And you know a decade later in 1984 we had something like 1 micron technology which operated at a supply voltage of 5 volt right. You can obviously see that we scale the dimension by 5 x, but the voltages were not scaled by 5 x the voltages were scaled by only 2 x right. So, then of course from 1 micrometer we came down to 0.35 whereas, the supply voltage came down from 5 volt to 3.5 volt again you know it is not the same scaling factor. However, here it is very close from 0.35 micrometer which is 350 nanometer we came down to 19 nanometer and the supply voltage came down from 3.5 volt to 1 volt right. I mean it is very close to 0.9 volt right at least here we are very close to constant electric field scaling theory right. Whereas, here in these scenarios we have actually let the electric field go up in the device right. And now you know we are first of all why did it happen right. There was always a resistance to scale voltage because you see eventually you are going to use these chips and build systems right. A system designer would have already designed a system at working at 10 volt right. And 2 years down the line if you come back to the system designer and tell the designer that I have a better chip, but you will have to redesign your entire system to operate at 8 volt you know there will be lot of resistance from system designer right. So, that is why historically the voltage scaling has been very slow there has always been a resistance to scale voltage. As far as possible keep the voltage you know only if it comes to such a bad condition that the device will break down it will not operate. See why first of all why do you want to scale voltages because if you do not scale voltages your electric fields in the device will be so large that you will have the device break down taking place right. Of course, you cannot let the voltages be stay at the same time right at the same value all along voltages have scaled as long as they satisfy the reliability consideration they have not scaled beyond that right. They have just picked the voltage that is adequate right accordingly 3.5 1 volt and so on and so forth right. And that is why we define a few other scaling scenarios that are called constant voltage scaling in which case this is another extreme right. You do not scale the voltage from the current generation of technology to the new generation of the technology right which means all linear dimensions are scaled voltage is not scaled. If you do not scale the voltage you want to scale all linear dimension your doping concentration has to go up by k square correct. Based on whatever we worked out earlier right if you do that in your device the electric field will go up by this factor k drain current will go up capacitance of course will come down because all linear dimensions have been scaled and capacitance is only a function of linear dimension. Your delay of course goes down much faster 1 over k square as opposed to constant electric field scaling theory where the delay was decreasing only as 1 over k. Your circuit is little more faster you know that is also another good thing if your circuit becomes fast and withstands the reliability constraint then you are ok you do not necessarily have to scale the voltage right. However, the flip side is that your power you know will go up your power delay product will not scale as efficiently as it used to earlier right. So, these are other issues right this is circuit density of course will improve no matter what right because you are scaling the linear dimension and circuit density will go up. So, but as I mentioned we have neither done constant electric field scaling theory nor done constant voltage scaling, but instead what we have actually done is something called generalized scaling. Here what we say is that we introduce one more parameter called alpha we have a linear dimension scaling factor which is k all linear dimensions are scaled by the same factor k your supply voltage is scaled as alpha divided by k. Now, when alpha is equal to k you know it is a constant voltage scaling theory right otherwise you know it is a constant electric you know for different values of alpha between the extreme you go between electric field and voltage constant voltage scaling and in between we call it is a generalized scaling right. Voltages are scaled, but not as aggressively as the scaling in linear dimensions ok. So, again you can go through the math that we did earlier you see that the electric fields are going up by a factor alpha, but not as much as constant voltage scaling theory in which case it would have gone up by k where here alpha is less than k. Ideas go scales as this capacitance will scale as this and your delay will go down as this as I mentioned already right when alpha is equal to 1 it is a constant electric field scaling when alpha is equal to k it is constant voltage scaling theory right. So, you know that is what we have done we have really done what is called a more generalized scaling ok. Now, this is all fine when we are talking of what is called idealized scaling right, but you see there are certain parameters that we call are non-scaling. Let us start with band gap of silicon right the band gap of silicon is 1.12 electron volt right whether you know your transistor has a gate length of 1 micron or 0.5 micron your band gap of silicon does not change right and you know that is a very important parameter right. Now, why is it important it turns out band gap is important because this in turn will determine what is going to be your bulk potential ok. You dope silicon you introduce certain number of impurities your Fermi level in silicon will change and that is what we call a bulk potential an intrinsic silicon has a 0 bulk potential you convert it to p type or n type and Fermi level will go down if it is p type below mid gap if it is n type it will go above the mid gap right and that is the bulk potential right and that bulk potential also depends on what is your band gap right and your intrinsic carrier concentration depends on band gap right. So, there are lot of device parameters which are governed by band gap right right. So, they will remain invariant they do not really scale right and thermal voltage you see this is also another important parameter what is thermal voltage essentially it is k t over q right k is Boltzmann constant q is electron charge and t is the absolute temperature you see if your chip commercial chips most of the commercial chips are spec to operate between minus 40 degree centigrade to plus 125 degree centigrade right that is your typical operating temperature of your chip right whether you do a chip in a you know 315 nanometer technology or 65 nanometer technology it is going to the same application right and hence this operating range is not going to change as a result of that the temperature remains same you know the temperature of operation is not changing. So, k t over q does not change right again this has very significant implication as we will see little later right because this k t over q among other things it determines one very important metric of a device and that is called sub threshold slope this sub threshold slope will determine what is the leakage current of a transistor. So, this is a very important parameter in fact we will see that one of the reason why the on current to off current ratio is degrading as I mentioned earlier is because your leakage current increasing and that is because your sub threshold slope is invariant you are decreasing the threshold voltage, but the sub threshold slope is not changing and hence you have very large leakage current right we will talk about that later. Mobility degradation we made a very simplistic assumptions earlier we said that voltage scales as one v over k current will scale as v over k. But in reality you know what is the current that we are talking about the current that we are talking about is a MOSFET current right you know a MOSFET current for example if it is in a saturation region then it is essentially given by you know expression which would look something like this right where this is what we call the mobility. So, now if you were to see this you know what we mentioned a while ago right this mobility we have assumed is not going to change the mobility will remain constant. First of all now let us verify if mobility were to be constant whether this is indeed the case right remember this C ox here is a per unit area capacitance. In other words this C ox here is epsilon ox epsilon naught divided by T ox that is the C ox C ox is not the total capacitance here. Now you see T ox scales as one over k. So, one over k will come to the numerator all voltages we have said scale as one over k right there is a square term here voltage square term right. So, hence you will have a one over k square term here in the denominator right. So, in other words your idea scaling rule will be k coming from C ox in the numerator k square coming in the denominator because of V G minus V T square term you see and that is how we said V scales over by this dimension and I also scale as I over k that assumes that mobility is not scaling you see, but that is no longer true mobility is also getting affected and why is that because the scaling theory told us to increase the doping concentration you see. We had this transistor right this is a source and this is the drain and this is my p type region which is doped with certain impurity concentration. When the electrons are travelling in this channel to reach the drain terminal and contribute to your drain current they get scattered because of the presence of impurities in this channel and that is what is called the impurity scattering and impurity scattering has a significant impact on the mobility of a transistor right and in general carrier mobility as I started increasing the doping concentration here as dictated by the scaling guideline I had to do that you see my mobility will degrade in the channel right because these carriers will start seeing more impurity atoms and as a result of that your mobility is no longer constant right. We had implicitly made this assumption that mobility is constant and hence v scales as v over k I will scale as I over k right. So, these are the secondary effects that we need to worry about when we actually look at a practical device. There is also another issue of velocity saturation you see and this is also you know something very important issue that we need to address and that essentially if you look at electric field versus velocity curve in any semiconductor you know it will look like this remember what is mobility your velocity is your mobility times electric field and this is the proportionality constant mobility right. So, hence v versus e is expected to be linear, but every material has a what is called a saturation velocity the velocity the maximum velocity the carriers can attain in that given material. For example, in silicon the saturation velocity is about 10 to the 7 centimeter per second and typically this saturation velocity we attain this saturation velocity at electric field such as 10 to the 4 volt per centimeter 10 kilo volt per centimeter kind of electric field you start departing from this linear relationship. Now, why is this important because remember this transistor that we said n plus n plus and this is my length the electric field in this lateral direction where the carriers are conducting right and this is the electric field which is accelerating the carriers and they are attaining certain velocity. This electric field is increasing as I said because we have not been following constant electric field scaling theory. If we have this electric field approaching this region then you know your current really does not respond to the voltage beyond certain point right you are increasing the voltage, but you are already in this regime carriers cannot attain any higher velocity right. So, your you know current will not really increase right. In other words you will have current saturation even before the pinch off condition typically in a MOSFET you get a current saturation only when you reach a pinch off condition. In other words if you were to look at I D S versus you know V D S right. So, you have this kind of a behavior right this is a linear region and this is a saturation region right and you transition from a linear region to saturation region when you have a pinch off condition correct. Now, if you have a velocity saturation which takes place even before pinch off has occurred you are increasing a voltage current is increasing, but now you have saturated the velocity of the carriers current can no longer increase beyond this point. So, you have an early saturation of the velocity and hence your current gets impacted ok. So, this is another important effect that we have to address we have to look at the device and ask the question are we operating the device in velocity saturation regime. If so we will have to use different set of equations to describe the device behavior right. So, it will no longer be a quadratic behavior between drain current to the gate to source voltage right. So, that is also another important parameter to consider right. So, the other thing of course is the parasitic source and drain resistance again you see when we talked about the transistor right this is the source and drain region and this is your gate by applying gate voltage you are only controlling this channel. Eventually we will have a metal contact which will be coming in the source and drain region somewhere out here with a proper distance maintained between the gate edge and this contact. If you do not maintain this proper edge you may have a danger of this contact shorting gate and the drain or gate and the source right you need to have an appropriate distance right. Now, what it means is the following right I am applying a ground potential to the source terminal which means at the metal contact. I am applying a drain voltage out here again at the metal contact right because this transistor sitting you remember sitting all the way down in your hierarchy of the interconnects and silicon that we looked at in the last class right. So, the supply is applied out there if it is metal 5 that is where I am applying the drain voltage and the ground potential and that signal will have to come down all the way down to the silicon although in that case fortunately we can ignore all the metal resistances right for all practical purpose. But you see this resistance out here it is no longer a metal right it is a highly doped silicon and this is what we call a parasitic resistance right. In other words I have a gate control only in the channel region if you were to write an equivalent model for this transistor then your equivalent model for your transistor would look something like this. This is your drain voltage this is your gate voltage and this is your idealized transistor, but then you have a parasitic source resistance and a parasitic drain resistance which is which should not be there ideally right because eventually if this parasitic resistance is large then it can impact the entire transistor behavior right. Now, is it becoming large yes. Why is it becoming large you see we have decreased this junction depths the junction depth is coming down and you know the current that is coming out here in the channel has to flow through this region with decreasing junction depth that resistance has also increased phenomenally right. So, that is also another important consideration and of course we do something very intelligent to overcome all this right. This is what you can understand why do we need new materials you know how do we bring this resistance back to where it should be and so on and so forth right. So, that is something that you need to keep in mind. Then the last one is what we call a process tolerance you know we will not really discuss quite a bit about this in this course, but what it tells you is the following right if you are talking about a circuit right you are making printing manufacturing large number of transistors. You have this chip as I mentioned there is a transistor sitting here transistor sitting here and so on and so forth. Let us suppose that you have designed this transistors to be identical transistor with w is equal to let us say 0.5 micrometer and l is equal to let us say 100 nanometer or 0.1 micrometer, but when you actually fabricate this transistor it turns out these transistors if you were to measure electrical characteristics they do not come out identical to each other. There is what is called a process variation when you are trying to print here it may not print exactly 0.5 here it may print as 0.52 and here it may print as 0.49 and here the length may print as 0.11 and here it may be 0.099 or whatever it is right. So, there is going to be variation in the processing that we have there is a process tolerance. What is happening is that it is becoming harder and harder for us to make tiny transistor exactly identical to each other. In other words if we were looking at a one micron technology and look at any device parameter such as threshold voltage which is a very important parameter for a transistor you will still have a distribution, but the distribution would have looked something like this very tight distribution with very very low standard deviation. On the other hand this is what you would see in a one micron transistor. On the other hand in a 19 nanometer technology if you were to look at a Vth distribution you may see a distribution which would look like this. You have made a million transistor which were supposed to be exactly identical to each other, but they are no longer identical they are actually huge spread. How do you manage this spread? This is also a very important consideration that one has to keep in mind. So, this is what we call as some of the parameters which are non scaling and we will have to deal with these parameters appropriately. But just to sort of summarize and conclude we require scaling because scaling will immediately enhance the circuit performance make the circuit more efficient in terms of speed and consumption of power and so on and so forth. However, there are lot of issues that will come about because of scaling because the world is not ideal as we looked at some of the non ideal factors. We need to be able to design the transistors so that we overcome all these non idealities and still be able to derive all the benefits that were indicated in the beginning in a ideal scaling theory. We will look at some of these things in the next class.