 Namaste, I am Mr. S.S. Shakapure, Assistant Professor, Department of Computer Science and Engineering, Valchan Institute of Technology, Solapur. My today's topic about Operating Modes of 8257 and my learning outcome at the end of this session to understand concepts of direct memory access controller and how to initiate an DMA cycle and their use in microprocessor based system. Now, Operating Modes of 8257. In 8257 block diagram, one set, the various beats in the mode set register enables each of four DMA channels and allow four different operating modes of options for the 8257. So, in the block diagram, we come to know the number of DMA channels. There we have the total four DMA channels. So, to set or we can say to enable or to disable or for any operation belongs with the DMA channels, we have this mode set register. So, the format of mode set register is this particular register consisting total 8 beats. So, the number of beats are B0 to B7 and each number of each individual beat is performing some different function. So, about the B0, so about B0, B1, B2, B3 are the four continuous beats are used to enable or disable the channel of DMA0, DMA1, DMA2 and DMA3 respectively. And to enable particular any DMA channel, we set the value 1 and to disable that particular channel, we used to set the value or the about the beat B4. The B4 beat is RP, RP is nothing but which used to indicate whether that particular beat is a rotating priority or a fixed priority. So, about the service guarantee, this particular beat is used for setting the priority. And after the next beat of B4, B5 is EW which used to set either that particular channel is an extended right selection or a normal right selection. Beat position B6, B6 is a TCS beat, TCS is equals to 1 that is if set to 1 it stops DMA on terminal count which indicates the completion of terminal count process. And after B6, B7 beat it is Ato reload. So, Ato reload is if AL beat is set to 1 it enables Ato reload and the same if we set AL equals to 0 it disables Ato reload. Now, the use of mode set register. So, to enable or disable any channel, the beats B0, B1, B2 and B3 of mode set registers are used actually which are used for enabling and disabling the channel 0, 1, 2 and 3 respectively which we already discussed. And one of one in these beat position will enable a particular channel and 0 in mode set register beat B4 is we know about beat beat B4 position it belongs with either rotating or normal. So, about the rotating priority we need to set to 1 then the channel will have rotating priority and if it is 0 then channel will have the fixed priority. In rotating priority mode the priority of the channel has a circular sequence and in this channel being serviced gets the lowest priority and the channel next to it gets the highest priority which we come to know in our following figure. So, in the rotating priority if you are looking we have the total 4 different channels 0, 1, 2 and 3 and channel 0 is the highest priority and the channel 3 is the least priority. Thus with the rotating priority in a single chip DMA system any device requesting service is guaranteed and to be recognized after no more than 3 higher priority service have occurred. About the fixed priority if you are looking here the fixed priority the channel 0, 1, 2, 3 have different priorities 1, 2, 3, 4. So, in this fixed priority after recognition of any one channel for service the other channel are prevented from interfering with the service until it is completed. If bit B4 of mode set register is logic 0 operating mode of A257 operates in fixed priority mode. Now, about the our next bit B5 where we can speak about the bit B5 is about the extended write. So, if the bit B5 is set to 1 then the timing of low write signal will be extended. So, in this particular extended write the micro computer system allows use of various types of memory and IO devices with different access time. If a device cannot be accessed within a specific amount of time it returns not ready that indicates to the A257 that causes the A257 insert one or more weight states. In its internal sequencing about my next bit bit B6 which we speak TC stop. So, if it is set to 1 then DMA operation is stopped at the terminal count ok. So, if the TC stop bit is set a channel is disabled. And after the terminal count output goes high the automatically preventing further DMA operations on the channel. And to enable DMA operation on the channel it is necessary to set enable bit of the corresponding channel in the mode set register ok. About I have a question please think about this particular question which we discussed up till now in A257 register format. The selected channel is disabled after the terminal count condition is reached when you have the four options. Ato load is set Ato load is reset TC stop bit is reset TC stop bit is set. So, your answer is D if the TC stop bit is set the selected channel is disabled after the terminal count condition is reached. And is further prevented any DMA cycle on the channel. So, my next bit is Ato load which is my last bit bit B7 and is used to select Ato load feature. So, Ato load mode when enabled the data is transferred by channel 2 only that is the other channel are not used for data transfer. On this mode permits block chaining operation without immediate software intervention between blocks. If the TC stop bit is not set the occurrences of the TC output has no effect on the channel enable bits. It can be used for repeat block or block chaining operation about the summary part. So, each DMA channel has one DMA address register and the function of this register is to store address of the starting memory location which will be accessed by the DMA channel. Thus, the starting address of the memory block that will be accessed by the device is first loaded in the DMA address register of the channel. Naturally, the device that wants to transfer data over a DMA channel will access the block of memory. And these are my references which I used. Thank you.