 I am Dr. Srisal Gajbar and in this video lecture we are going to implement full adder circuit by using Veriloc HDL language. So at the end of this session you will be able to implement full adder circuit by using Veriloc HDL. You will also be able to write the test bench in Veriloc to verify the module correctness. The software that we are going to use for the simulation purpose is model sim student edition. You can download the software by using the link which is given here. The workflow for our session will be as follows. We will first discuss the Veriloc module followed by we will also discuss the test bench and at the end we will verify the simulation results in model sim software. So full adder circuit is a combinational circuit which performs addition of three binary bits. These three binary bits are represented here as capital A, capital B and C in. There are two outputs namely sum and carry which are represented using the names capital S and C out. This is the truth table for full adder circuit and in this truth table one can see that for all possible input combinations the outputs are provided and from this truth table one can find the logical expressions for capital S as well as capital C out which stands for sum and carry output respectively. So these are the expressions that we get after the Kmap reduction. So capital S is given by using this expression so and capital C out that is output C out can be expressed using this logical expression. So we can also simplify the previous sum and carry output outputs. So this capital S after rearranging this equation which we obtained from the Kmap we get capital S is equal to C in XOR operation with this term in the bracket which is nothing but X XOR operation with Y. So the sum can be represented in case of full adder circuit as this expression which is simple to implement. So we can also simplify the carry output also and the carry output in this case is given as C in and operation with the term in this bracket. The term in the bracket is nothing but X XOR operation with Y and this complete term is odd with this term which is nothing but X and operation with Y. So this is the gate level implementation for full adder circuit. So there will be 3 inputs I1, I2 and C in, 2 outputs sum and carry out. So this is the module definition for full adder circuit. As mentioned in the previous lectures the module definition will start with the module keyword followed by the name of the module which is full underscore adder in this case and inside the bracket you provide the list of input and outputs. So and those are I1, I2 and C in which are inputs and sum and C out are nothing but our outputs. In the next line in the next 2 lines we define the input and outputs explicitly. So input is the keyword. So input followed by I1, I2, C in and outputs are defined as using output keyword output space sum, C out, semicolon. So don't forget to give the semicolon in this statement. Then next from the expressions that we have got here for the sum and C out we are going to implement them using the behavioral approach. So that is why we have written assign keyword sum equal to I1, carrot symbol I2, carrot symbol C in. So as mentioned previously carrot symbol stand for the XOR operation. So what is going to happen in this case? So I1 XOR operation with I2, XOR operation with C in is going to happen and whatever result is there that is going to assign to the sum output. Similarly, C out is written as in bracket C in and person which stand for the AND operation and inside the bracket I1, carrot I2 which is nothing but I1 XOR operation with I2. This pipe symbol represent the OR operation. So this whole term is OR with I1 and I2 and finally don't forget to give the semicolon and this module definition will end with the end module keyword. This is the very locked test bench for full adder circuit. So this will also be a module. So our name of our test bench is test underscore full adder. So this is defined using the module keyword. So module space test underscore full adder semicolon. Then we are going to define the inputs and outputs. The inputs in this case right you need to provide the various input combination and unless and until the new input combination is provided the previous should be stored. So that is why we are going to represent the I1, I2 and C in which are our inputs by using the reg data type. The outputs are represented by using the wire data type. In the next line we are instantiating our full adder module as full underscore adder followed by the name of the object that is H1 in this case. You can take any name here no problem and inside the bracket you are providing the list of input and outputs. So I1, I2, C in, sum, C out and in the next we are going to define the initial begin block. So initial block we are going to define using the initial keyword and since there are multiple statements we are going to write the begin end block inside the initial. So this is the first input combination I1 equal to 0, I2 equal to 0 and C in equal to 0. This is the first then for the next input combination I am giving the delay of 50 units and since there are 3 inputs I1, I2 and C in there will be 2 raise to 3 that is 8 input combination and all these 8 input combinations are provided here. So this begin will end here using the end keyword whereas the complete module will end with the end module keyword. So before going for the actual simulation answer the question on your screen. So the correct answer is it represents the delay of 50 units. The exact duration of the delay depends upon the time scale which you are setting. So it depends on the time scale. So whether it is second, whether it is nano second or whether it is picosecond it depends on the time scale that you are setting. So this hash 50 here represent the delay of 50 units. Now let us see the simulation results in model screen. So I have already written the program this is the model definition that we have discussed and this is the test bench that we have discussed. So the first task is to compile the program. So for compilation go to compile, select test underscore full adder compile. Just check whether it is compiled successfully or not so there are no errors and warnings so our compile is successful. Then go to library and inside the work folder go to the appropriate name so in this case it is test underscore full adder go to there simulate and go to the add to wave all items in region. So basically there will be 3 inputs i1, i2 and c in and there will be 2 outputs some and c out. The next task is to run so there are 8 input combination remember you can see that for the input combination for i1, i2 and c in as 0, 0, 0 you can see the sum is equal to 0 and the carry is also equal to 0. For the input combination of i1, i2, c in equal to 0, 0 and 1 you can see the sum output is equal to 1 and the carry is equal to 0. We can take one of the input another input combination for this combination you can see the i1 is equal to 0, i2 is equal to 1 and c in also equal to 1 so 0 plus 1 plus 1. So in this case the sum is going to be 0 and the carry should be 1 the same you can observe here. So in this case you can see the sum is equal to 0 and carry is equal to 1. So other input combination you also verify and check whether you are getting the correct answer for the sum as well as for carry output. In this case I am getting the correct answers these are the references thank you very much.