 Hello, and welcome to this presentation of the STM32MP1 Power Controller. The STM32MP1's power management functions and all power modes will also be covered in this presentation. The STM32MP1 microcontroller has several key features related to power management, including several low power modes where it is still possible to wake up the CPUs individually with an event on an I-O, as well as a large number of peripherals that can wake up from the various low power modes. Several power supplies are independent, allowing reduction of the device power consumption while some peripherals are supplied at other voltages. Thanks to the large number of power modes and independent power domains, STM32MP1 devices offer high flexibility to minimize the power consumption and adjust it depending on active peripherals, required performance, and needed wake-up sources. Some system resources can be secured. STM32MP1 devices have several independent power supplies, which can be set at different voltages or tied together. The main power supply is VDD, supplying all IOs. VDD also supplies the reset block, temperature sensor, and all internal clock sources. In addition, it supplies the standby circuitry, which includes the wake-up logic and independent watchdog. The VDD core directly provides the V-core supply. V-core supplies MPU Cortex-A7, MCU Cortex-M4, with most of the digital peripherals and the AXI RAMs and SRAMs. The DDR interface has its dedicated VDDQ DDR supply. The STM32MP1 features several independent supplies for peripherals. VDDA for the analog peripherals, VDD3V3USBHS and VDD3V3USBFS for the USB transceivers, VDDA1V8DSI and VDD1V2DSIPHY for the DSI interface. The VRF plus pin provides the reference voltage to the analog to digital and to digital to analog converters and can be used as an external buffer reference for the application. A backup battery can be connected to the VBAT pin to supply the backup domain. Furthermore, the STM32MP1 microcontroller incorporates various regulators, which provide the various voltage levels for the USB and DSI interfaces. The main power supply VDD ensures full featured operation in all power modes from 1.71 up to 3.6 volts, allowing it to be supplied by an external 1.8 volt regulator. Other independent supplies are provided for peripherals operating at a different voltage. A backup domain is supplied by VBAT, which must be greater than 1.2 volts. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator, the backup registers, and the backup RAM. When the retention RAM is used, VBAT must be at the least greater than 1.4 volts. The digital core is directly supplied from VDD core, typically at 1.2 volts in run mode and typically at 0.9 volts in LPLV stop mode. The analog power supply VDDA can be connected to anti-voltage other than VDD. When an analog to digital converter is used, the VDDA voltage must be greater than 1.71 volts. When a digital to analog converter or VRF buff is used, VDDA must be greater than 1.8 volts. The USB interfaces have their individual supplies, VDD3V3USBHS and VDD3V3USBFS. The DSI interface requires two supplies, VDD1V8DIS and VDD1V2DSIPHY. The DDR interface is supplied from the individual VDDQ DDR. The ADC and DAC voltage references can be provided either by an external supply voltage or by the internal reference buffer. This allows the converter's performance to be improved by providing an isolated and independent reference voltage. The backup regulators are used to keep the context of the backup RAM and retention RAM in standby and VBAT modes. Each RAM has its dedicated regulator. The backup RAM regulator is enabled by the BREN bit in the power register CR2. The retention RAM regulator is enabled by the BREN bit in power register CR2. When a regulator is enabled, its supply level is checked to be ready before the system enters standby mode. Independent USB regulators generate the VDDA1V8REG and VDDA1V1REG supplies from VDD. The DSI regulator generates the VDDIV2DSIREG supply from VDDDSI. The power supply supervisor ensures dynamic power supply management. STM32MP1 devices embed power management on main VDD, analog VDDA, VBAT supply input, V-core domain, backup VSW domain, backup regulator VBKP, retention regulator VRET supply, USB interface, WDD3V3 USB supply, and regulator supplies VDDA1V8REG, VDDA1V1REG, and VDD1V2DSIREG supplies. The main VDD supervisor handles reset management and voltage detection via the Programmable Voltage Detector, or PVD, when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby modes. Seven thresholds can be selected by software. In addition, comparisons can be done with an external pin. The analog VDDA supervisor handles voltage detection via the Analog Voltage Detector, or AVD, when VDDA crosses the selected threshold. The AVD can be enabled in all modes except standby mode. Four thresholds can be selected by software. The VBAT supply voltage is monitored to detect when VBAT crosses the minimum and maximum thresholds. The VBAT voltage detection function can be enabled in all modes. The main V-core supervisor handles reset management detection. The backup domain VSW supervisor handles reset management when the supply drops below the operating level. The backup RAM regulator VBKP supply supervisor verifies that the regular is ready to supply the backup RAM before entering standby mode. The retention RAM regulator VRET supply supervisor verifies that the regulator is ready to supply the retention RAM before entering standby mode. The USB interface VDD33 USB supply supervisor verifies that the USB interface supply is present. The USB supervision can be enabled in all modes except standby modes. The USB and DSI regulators VDDA1V8REG VDD1V1REG and VDD1V2DSIREG supply supervisors verify that the regulator is ready to supply the interface. The VDD power supply supervisor guarantees a safe and ultra low power reset management. STM32MP1 devices embed an ultra low power brownout reset or BOR which is always enabled in all power modes. The BOR ensures reset generation as soon as the MCU drops below the selected threshold regardless of the VDD slope. Four thresholds from typically 1.63 volts to 2.6 volts are selected by the option byte programmed in flash memory. The temperature supervisor detects when the junction supervisor crosses the minimum and maximum thresholds. The temperature detection function can be enabled in all modes. The backup battery supervisor detects when the backup battery supply level crosses the minimum and maximum thresholds. The backup battery detection function can be enabled in all modes. The battery charging feature can charge a supercap connected to the VBAT pin through an internal resistor when the VDD supply is present. The charging is enabled by software and is done either through a 5 kilo ohm or 1.5 kilo ohm resistor depending on software. Battery charging is automatically disabled in VBAT mode. The following features can be made trust zone secure. They are either all secure or all non secure. Backup battery voltage monitoring, temperature monitoring, programmable voltage detector, analog peripheral voltage detector, backup domain protection and backup and retention RAM settings. USB regulators control, DDRs self refresh and retention settings, backup battery charging systems, MPU system low power mode configuration, LPS stop and LPLV stop mode configuration and individual per wake up pin configuration. The CPU entering low power mode is controlled by the WFI and WFE and the deep sleep bit allows the mode selection between C sleep and C stop, C standby modes. When the CPU enters C stop, C standby mode, the system operating mode depends on the other CPU. C sleep mode is exited with an NVIC interrupt or RX event. The way C stop mode is exited depends on the system mode. When the system is in run or stop mode, C stop mode is exited with an NVIC interrupt or RX event. When the system is in standby mode, C stop is exited with a reset. The MPU exits from C standby mode with a reset. A CPU event input or RXCV wakes up the CPU after a WFE. The STM32MP1 system operating mode is controlled from both CPUs. The system only enters stop or standby mode when both CPUs are in C stop mode and there is no active wake up source. The system only enters standby mode when all the PDDS bits select standby mode. Sleep and low power sleep modes enable all peripherals to be used and feature the fastest wake up time. In these modes the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep and low power sleep modes. These modes are entered by executing the assembler instruction wait for interrupt or wait for event. When executed in low power run mode, the device enters low power sleep mode. Depending on the sleep on exit bit configuration in the Cortex M7 system control register, the MCU enters sleep mode as soon as the instruction is executed. Or as soon as it exits, the lowest priority interrupts a routine. This last configuration saves time and consumption by removing the need to pop and push the stack. STM32MP1 devices feature three stop modes, stop, LP stop and LPLV stop. Which are the lowest power modes with full retention and fast wake up time to run mode. The contents of SRAMs and all peripheral registers are preserved in all stop modes. All high speed clocks are stopped. The 32.768 kHz external oscillator and the 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake up from stop modes. The MPU system clock on wake up is restored and the MCU will receive the HSI clock. LP stop and LPLV stop power consumption is lower than the consumption for stop mode. But those modes support less active wake up peripherals. When comparing stop modes, stop power consumption is higher than the LP stop and LPV stop consumption. But the wake up time is shorter. For stop and LP stop modes, the number of active wake up peripherals is higher. Stop and LP stop modes keep the V-core domain at the same supply level as run mode. Allowing a very short wake up time at the expense of a higher consumption than LPLV stop mode. LP stop mode allows the external power supply unit to be placed in low power mode, reducing overall system power consumption. LPLV stop mode allows the external power supply unit to be placed in low power mode and supplies a lower VDD core level, reducing the STM32MP1 and overall system power consumption. Stop and LP stop modes support the same number of active wake up peripherals, where LPLV stop mode supports a reduced subset. The standby mode is the lowest power mode in which 4 kilobytes of backup RAM and 64 kilobytes of retention RAM can be retained. The automatic switch from VDD to VBAT is supported. By default, the voltage regulators are in power down mode and the SRAMs and the peripherals registers are lost. The backup registers are always retained. Thanks to software, it is possible to retain the backup RAM and the retention RAM. The ultra low power brownout reset is always on to ensure a safe reset regardless of the VDD slope. Five wake up pins are available to wake up the device from standby mode. The polarity of each of them is configurable. The MPU system clock is restored at wake up and the MCU system clock selects the HSI clock. The backup domain allows us to keep the RTC functional and to preserve the backup registers in case the VDD supply is down, thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low speed external oscillator at 32.768 kHz. Three tamper pins are functional in VBAT mode and will erase backup registers also included in the VBAT domain in case of intrusion detection. The backup domain also contains the RTC configuration register. In case VDD drops below a certain threshold, the backup domain power supply automatically switches to VBAT. When VDD is back to normal, the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the battery backup level. When VDD is present, the battery connected to VBAT can be charged from the VDD supply. When a CPU wakes up from its C stop mode, it has to know from which mode the system has awakened. For this, each CPU has dedicated flag bits, standby flag and stop flag. These bits inform the CPU about the state of the system and which parts may need to be reinitialized. When the MPU wakes up from C standby mode, it is informed by the MPU standby flag. The system modes at wake-up are available in the stop flag and standby flag. This table gives an overview of the MPU and MCU wake-up state versus the system operating mode and how they are signaled by the wake-up flag bits. It also shows how the MPU and MCU were awakened through an interrupt or an event or a CPU reset. Here is a summary of the PWR control-related interrupts. The debug control register is used to enable debugging in stop and standby modes. When the related bit is set, the CPU clock and bus matrix clock is kept active and the regulator is kept on in normal mode to supply the core logic. This maintains the connection with the debugger during the low power modes and keeps the debugging alive during and after wake-up. Remember to clear these bits when the device is not under debug. Because the consumption is at higher than all low power modes when these bits are set due to the fact that they force the regulator to remain enabled and keep clocks active. In addition to this training, you can refer to the reset and clock control and interrupts trainings as well as those for all the peripherals with wake-up from stop and standby capability.