 अस्लाम लेक्म स्टुडन्त, आम्वस्टीमिक्राम, this is the 19th lecture in a series of 45 lectures on digital logic design. कैसे हैं आप अप अच्छला ठीक होंगे अच्छे होंगे. पिष्टल लेक्चर में हमने मुल्टी प्लेक्सिस पे बात की ती. अप स्लेक्ट एंपृट से एक एक एंपृट उसका स्लेक कर हैं, जो भी वाल्यो होगी वो अध्पृट पे जाती आजाएएगी आपके पस. ती वेरीबल बुली बच्छन में आपके पास आत मिंटम सोट सकने हैं. जो भी मिंटम उस चन्टर्ट समथ परटक्ट एकश्प्चन में मोचोद है उसको अप रबजैन करेंगे बाया वारन फ्लेलेझ. अप प्लेले लेँग. तो भी चेंज हो सक दे दूड़े दिफन प्रामीटर से अप ने शोटा सा सरकेट बनाया था using a multiplexer for input multiplexer a 2-4 decoder or a 2-bit counter. तो भीसेखली, counter जो है, decoder के outputs को बारी-बारी सेलेख करतार उन output से जो चार प्रोसेस ने वो बारी-बारी activate होते जो ही एक प्रोसेस कंठलीट होता हो एक activ high signal या logic 1 बेजदा अपने output थे जो output है चारो प्रोसेस की वो जो चार अंबॉत है multiplexer उन से connected है तो at any given time आपने पले पैले अंटर्वल में process 1 जब चरला थो एक output जो है multiplexer बे connected है मूल्टिप्लेक्सर का इंपुट वाँ अक्टीवेट हूँवा तो जुही वो वान आएगी मूल्टिप्लेक्सर के अउट्फुट प्या आगा वो आगे लेईवेजने काम्टर को इंक्रिमेंट कर दिया तो इस्टीटना सेखिन प्रुस्सच चलेगा थर्द and 4 अजा मैं धिसकीषन �皆你有Con why it originated larger दिमूल्टिप्लेक्सर दिमुल्टिप्लेक्सर है थी टिमुल्टिप्लेक् SI матери is the opposite of a multiple जस्नंभन मुल्टिप्ल्लेक्सर की बाद की ताच Blue one word was multiple inputs with the same oneflu स्लेक लाईसे आप जो मुद्सलिफ इंपॊट है।ия। in-line select mining in mongrel of inputs योपसेट ज़िन्मुटिप्लेक्सर, योपका अप्टी प्लोच्चर खुईघ of multiplexir, ति्दी प्टी प्लोच्चर का येग येग याईग येग पुच्चर खोगह योगगग अप्टीप्ली येग येग आप्टीप्ली अप्टीप्ली खृदौत कुञ होगगगichen. जीग आप भी भी झाूमा कुढ़ूँ कोब सब यदा from multiple destinations, select one out of multiple fate on the output. जी जव से अब दिस प्रेनै कीगड तो उगरा प्रे से लिए अपर दिसकनेर सेरी लेँग प्रेरेंगा। to apply a code on the selected input, जो में अप्च्ठ्ज्थ में यान्जाँ। क्रेंट आलीगाजा थीा आप्च्च्ट उहने देखौगाग। अंगी तुप्चट एक योंंने दींवटिख के क्ये रदा हैञां। of these lines are connected to all four and gates e Each of the four and gates is beautiful selected trough to select input lines i 1 and i 0 . These lines are connected trough inverters . So, to select the first output o 0 the select ______ have to being set to 0 0 similarly to select the second output, output1 the select lines have to be said to 1 0. i1 is 0, and i 0 is 1.Similarly, the third output O2 and the last output O3 can be selected by applying appropriate select inputs at i0 and i1.We have just looked at the circuit of a 1 2 4 de-multiplexers. d-multiplexers go to data distributer bikers length, because they are a source for different destinations since data distributen inных अगर आपको दीकोडर के सरकेत याद हो, और उसको अगर कमपेर करे दी मुल्टिप्लेक्सेस है, तो उन में बोत सी सिमलरेटी, अगर अगर अपके पस 2-4 दीकोडर है, तो उसके भी चार अट्फुट्स हैं, और दो अन्फुट्स हैं, और एक हम चिप इनेबल उस में यू� तो उसके नीए से दाता एंपृ रहा एत, आपके पस दीकोडर हो, अप उसको बगुज़ असानी से अजध दी मुल्टिप्लेक से जुस के सेथें, आप उसके जो दाता सेलेक लैईं हैं, याद चिप सेलेक लैई लैईं है, उसको आजद डदाता एंपृ लैईं के तोर उ बचो सर्सेर को देखें वो आर्टमतिक लोडिक वून्ट की हम नी बाद की अज्नातक लोंट्टे की है. यक लोडिक पत्टिक यूनेत की हि रोंझकलाँ बूश्यरी प्याम करएटधे रेगा. अर्तमातक बुर्छागत ईक अद्पुट मैं, after the results of the logical operations, अर्च्मातक अप्को मैं लेग. अगउ लेग लग, याई और पनी किेंगी श तोर करना, you need to store the results somewhere. सूत बेसिको इछले बात कि भी जे आप ये पफ़ुत निफ और और पॉत हैं। When we spoke in the classroom, आप तवा आप वफ़ट है अपको 3-Bit counter यूज करना पड़गा जो अपने मल्तिप्लेक्षर के साथ भी विए लिए जेव चाद जब आप पडलफ से शीरील में खनवरट कर रहते हैं जो 3-Bit counter है उसके अपपड़च अपको अप्टर थे सिलक्ट लाईन से अप ने पछ्ट הי ड़ अद आप वो बात लिए की ती वन मिलाचने के अप एक बिट कर ते वन मिली सेकन के अप यह हे के भिड़ कर ट्मंट कर रहे हैं सो इस थ्च स कैस मे लिए एक मिली सेकन के सेँ सेचस कर रहे हैं आप और वोगाiblyट कर गया look at the circle which hoses the Affix choral to Merge proverb, the single input of a 8 output team multiplexer is connected to the serial transmission line where it receives the incoming serial data, the eight outputs are connected to an 8-bit the tree select inputs a 0 a 1 a 2 are connected to the outputs of a 3-bit counter c 0 c 1 and c 2. . The counter is incremented through a clock signal. So initially,the counter is reset to 0 0 0 . This selects the output at a time in the其实 to have a set of output of  SUBSCRIBALS še �이크업  Transport še  MUSCLE äre broadcasting line . 這個  Ginsengchang ौ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ ॑ite bits at the input of the왕 quantities are stored in the eight-bet register at the output. We have looked at the application of a dimultiplexer as a serial to parallel converter. There many other applications of a dimultiplexer. Now, let us start our discussion on programmable Logic Devices, PLDs. आबतग हमने do traikeначewan kear, sikh hain. तो पने हैं, सीखे हैं, जिन के तु हम कुमबनीशनु स्रकित इंपलिमेन कर सकते हैं एक तो पलावाला तरीका है, लोजिक केट्स हैं आप कोई भी फुंक्छन जो है, उसका फुंक्छन तेबल बना हैं, अस में उसको सिंपलिफाई करनें, तो आप कोई भी फुंक्छन निपलिमेन कर सकते हैं, उसको उगर तो अपना खुम्प्लिक्स भी हो सकते हैं, और नप फुँछन भी हो सकते हैं, आप प्रड़ा इसका होगा, आप एक प्रुडि धिवाँस बना ऐप पूँप सरकित पूँचान दिएं, ज़ाई ये क्या आप दिपन् कौगएज यूँस करहें या प्मश्छनौल दिवाईसीच जोगेए में सैईचिप से थोगे योँस करहें आप एक प्यल्टी से एक अच्गाँ सार्ग्च कम्प्ल्ट सर्किर बना सब नें. आपके बज्थ सरे जो यक जैजटस यों ख़ापा, हो आम तरब बचुटी होटने, अब पीजेखल साच बचुट बाद खम है, अगर उस में इन सारो में दिगीमन दिजटल सरकेत होता है, अगर आप लोगिक गेट से लेईंठ करट है, अपन्च्छनोल योंडन्ट्टच थे अंप्रमेंग तो दिए जगा थोडी होती है जिस में पुरा सेगेट आ नी पायगाट उड़र आप प्यल्टी जिस लिज़ कर सकते हैं तुसनां प्यल्टी का तब दिशगषा लिज़्र, तुष्नम प्यल्टी का फाँईडा देखगेगे, कि आंको भार भार प्रगेम भी की और था सकभाया है उसका फाइडा यहे कि आपने लिथ से कों एल्क्டोनिक इंट्ट्टग दीवाईश है, उसका नेखस्ट मडल आँय, नेखस्ट वजन आए तो, उसको नफ्रूथ करने किलि आपको थ्या करना होगा, प्रिली डिवास को तुबारे से प्रोगेम करनें, वो यो बेद्तर फुंषन फुम करेगा या एक जो फुंशन है, यो पहले स्लोट हो आप नूप आप एक खम ताइम में वो पहले लिए हैं तो आप दिप्टाए नहीं हैं। आएज़र दिसखस कहतें की जो ठी येलटी धिवािसिस का अिन्तनलों स्थक्छो ये है है गे है जो हम भाद कर रहा है कि उन्फरी आण गेट से है और सोगाट से है अपस मैं कुनेक वह लिए हैं वाँ अर गेट अरे जो है, उस में आप यस तना उसको देख सकते हैं, के दे आर नम्र अप वर्टिकल लाईंस जाए आप एंपोट सप्लाए करते हैं, कोई भी बुलिन एकसपैशन हैं, उसके दिफन वेरियबल्स होते हैं. अगर अप यसके स्तुक्तौर को देख हैं, अपके पास एक ग्रिद बनावावा या एक अरे बनी हुए जुस में बुल्ट सब वर्टिकल लाईंस हैं, जाए आप एंपुट वेरियबल्स अपलाए करनें, बुल्ट सब होरिजन्तल लाईंस हैं, जो आपके दिफन अर गेट के एंपुट पे कुनेक्तेद हैं. इसाडी वेरिइटिकल लाईंस और वीरिजन्तल लाईंस जो हैं, ये आपके समें कोनेक्तेथ हैं, तुफॉजस नागत लाईंस था अपने कोईबी ईनपृ एंपुट कीसी और गेट पे कुनेक करनाई थू वो फॉज सब रैना देंगे, अगर आपने कोई तम नहीं कोनेक करनी तो आप गया करेंगे वू फूँस को उडर बलो कर देंगे उसको हटा देंगे. हटाएंगे कै से बसिकली यह सरा प्रोसेस तूग पोगामिंग होगा. अगर यह दफा आपने फूँस ध़ा दिया उसके बाद दोबारचे फूँस नहीं लगा सकते है. अपने आन्गेत अडरे को पुगाम करने तो आप आप उप्रोपेतली कुछ फूँसेस को उडर रहने देंगे औच कुछ फूँसेस को अप उदर से बलो करटांगे अस में. अपने आपने खॉएस के अपने एकूँसेस कुछ फूँँसेस के अपने आपने जा सकते है. the third vertical line is connected to B and the fourth vertical line is connected to B bar, the complement of B. There are six horizontal lines, two lines are connected to one or gate. So, there are three or gates and six horizontal lines. The diagonal lines show the fuse linking each vertical line with a horizontal line. So, basically this is an array of four into six, four vertical lines and six horizontal lines. So, you have 24 fuses which you can keep intact or you can blow out to program this or gate array. Let us have a look at the AND gate array. The structure is similar to that of the OR gate array. Again you have four vertical lines representing the four inputs A, A bar, B bar. You have six horizontal lines representing the inputs to three AND gates. You have 24 fuses which are shown to be connected. If you need to program this AND gate array, you have to blow some fuses. Let us now have a look at a programmed OR gate array. Again the same OR gate array has been used. Most of the fuses have been blown out. Only six fuses are shown to be there. So, the first OR gate gives the sum term A plus B bar. Now the fuse connecting the first vertical line which is connected to variable A to the first horizontal line. So, the input of the first OR gate is A. The second input is connected to B bar. So, the output is of course A plus B bar. Similarly, the second OR gate gives the sum term A bar plus B. Now as seen from the diagram, the two inputs of the second OR gate are connected to the two vertical lines A bar and B through the two fuses. Similarly, the third OR gate gives the sum term A plus B. The two inputs of the third OR gate are connected to the vertical lines for variables A and B. Let us now have a look at the programmed AND gate array. Again the same AND gate array is being used. It has four inputs and three outputs. The first AND gate gives a product term AB bar. So, the two inputs of the AND gate are connected to vertical lines A and B bar through two fuses. Similarly, the second AND gate gives out a product term A bar B. The two inputs of the second AND gate are connected to variables A bar B through two fuses. Similarly, the third AND gate gives out a product term AB bar. The two inputs of the third AND gate are connected to variables AB bar through the two fuses. We have seen the examples of the implementation of AND gate array and OR gate array. The structure is very simple. There are two ways of programming. One way is that we have seen in the slides that all the fuses have been connected to the horizontal lines in the beginning. You will have to program any product term or sum term. You will let some fuses remain. You will remove the other non-required fuses. The second way is that the AND gate array and OR gate array does not have any fuses in the beginning. Whatever product term you want to make or sum term through the appropriate gates, you will put those fuses there. Basically, you will make a link in it. Again, this link is done through programming. The fuses that blow up are also being programmed through it. In both the ways, if you blow up a fuse or make a link, it is once only. If you do it once, you cannot change it. So, if there is any mistake in your function, then you have to throw away the device and start all over again with a new device. Now, there are different types of PLD devices. Basically, there are four types. The first type is Programmable ROM P ROM. Programmable ROM will have AND gate array and OR gate array. The AND gate array is fixed. You cannot program it. It is already programmed in the form of a decoder. So, you can put more information in the OR gate array. Basically, P ROM is used as a memory. It is a programmable ROM. It cannot be used as a device. The second type of P early device is PLA, Programmable Logic Array. Programmable Logic Array's design is a PLA made to improve the AND gate array in P ROM. PLA has AND gate array and OR gate array. So, AND gate array's output is connected to OR gate array's input. In PLA, both the arrays can be programmed. So, AND gate arrays and OR gate arrays can be programmed. The third type is PAL, Programmable Array Logic. Basically, this is an improvement over the PLA device. As we have said in PLA, there are two programmable arrays. Due to this, the complexity of the circuit is very complex. The second problem is the gate delay. The output signal is after a lot of delay. So, PAL is made to improve both these things. In PAL, AND gate is programmable and OR gate can not be programmed. It is the opposite of P ROM. Similarly, the fourth type is generic array logic, GAL. Basically, GAL and PAL's structure are the same. In GAL, there is AND gate array and OR gate array. You can program AND gate array and OR gate array. You cannot program OR gate array. The two major differences in PAL and GAL, you can program GAL again and again. As we have said in the beginning, once you have programmed any PLA device or made a fuse, you cannot change it. But the logic used in GAL device is E-square CMOS, electrically-resable CMOS. Due to this, you can program it again and again. So, it is a very flexible device that you can use in your lab. You can use it in your lab. You can use it in your lab. The other devices are not so flexible, of course. The second benefit in GAL device is that you can configure the outputs of it in PAL and other two devices on it. You do not have the ability to configure them. Let us see the block diagrams of these four. Basically, there are connections between AND gate arrays and OR gate arrays. Let us have a look at the block diagram of a PROM. It has a fixed AND gate array and a programmable OR gate array. The inputs to the PLD device or the PROM are connected to the fixed AND array. Similarly, the outputs of the fixed AND array are connected to the inputs of the programmable OR array. The output of the PROM device or the OR gate array The output of the PROM device are available from the OR gate array. Let us now have a look at the block diagram of a programmable logic array or a PLA device. The structure is similar to the structure of the PROM. It has a programmable AND gate array and a programmable OR gate array. The inputs to the PLA are applied at the inputs of the AND gate array. The outputs of the PLA are obtained from the output of the programmable OR gate array. The outputs of the programmable AND gate array are connected to the inputs of the programmable OR gate array. In this case, both the AND gate array and the OR gate array can be programmed. Let us now have a look at the block diagram of a PAL device, the programmable OR logic device. The AND gate array is programmable and the OR gate array is fixed. It cannot be programmed. The inputs to the PAL device are connected to the input of the AND gate array. Similarly, the outputs of the PAL device are obtained from the output of the fixed OR gate array. The outputs of the AND gate array are connected to the inputs of the fixed OR gate array. As seen from the diagram, only the AND array can be programmed. The OR gate cannot be programmed. Let us now finally look at the diagram, block diagram of a generic array logic, GAL. The AND gate is programmable and the OR gate array is fixed. It is not programmable. However, the output of the GAL device can be programmed. The inputs to the GAL device are connected to the input of the AND gate array. The outputs are obtained from the fixed OR gate array. Similar to the other devices, the outputs of the AND gate array are connected to the inputs of the fixed OR gate array. As said before, the GAL device can be programmed repeatedly. It uses a different logic, which is different from the remaining three devices. We have looked at four different types of PLD devices. The first device, the PROM, it is programmed once. You cannot program it again. Similarly, the PLA device, PL device, you cannot program it again. The fourth device, GAL, you can program it again and again. We will discuss it in more detail later. Let us continue with our discussion. Let us talk about the PAL device, the Programmable Array Logic Device. The PAL device said that the AND gate array is connected to the OR gate array. You can program the AND gate array, but you cannot program the OR gate array. So, basically the outputs of the AND gates are permanently connected to the inputs of an OR gate. So, you do not have a choice. The inputs cannot be selected by OR gate. You can apply any product term on OR gate. All the product terms are being applied on OR gate input. Now, let us have a look at the structure of the PAL. If you estimate the actual commercial device in the structure, how many inputs and outputs of it can be. Basically, there can be eight inputs or more than eight. So, let us just consider a device which has eight inputs. Similarly, the outputs are normally eight to ten. Some of these PAL devices, their outputs can be configured as inputs. So, total inputs can be 16. As we have seen in the previous examples, every variable's complement form and uncompliment form are connected to the AND gate's inputs. So, if you have eight inputs and eight outputs which can be used as inputs, then how many total inputs can be applied if we apply eight different variables on the inputs. Similarly, eight outputs can be applied there as well as eight variables. We have complemented and uncomplimented forms which are coming. So, total input lines are 32. The horizontal lines which we have seen are connected to the input of each AND gate. We have a lot of AND gates. With each AND gate, there is a connection of 32 lines. It is difficult to make this kind of circuit. Let us simplify PAL circuits. So, instead of showing all the 32 lines, we will show one single line. We will mark it with a notation that these are 32 lines. Similarly, all the fuses are not necessary to show the fuses. We are showing the intact fuses as a cross mark. So, we have simplified PAL circuits. So, let us see that we have programmed a simple PAL as SOP function. There are three AND terms in it and the output is basically sum of these three AND terms. After that, let us see the other slide in which the simplified structure of PAL is shown. So, let us have a look. Let us have a look at a very simple programmable logic PAL programmed to implement an SOP function. There are three AND gates and the outputs of the three AND gates are connected to a single OR gate. So, the OR gate array cannot be programmed. The AND gate array can be programmed. The first AND gate outputs the product term AB bar and the appropriate fuses are shown to be intact. They are connecting the variables A and B bar. The second AND gate generates a product term AB. The input of the second AND gate is connected to variables AB through two fuses. Similarly, the third AND gate generates a product term AB. The inputs of the third AND gate are connected to variables AB through two fuses. Now, the three outputs of the three AND gates are connected to a single OR gate and the output of the OR gate generates an SOP function AB bar plus AB bar B plus AB. Now, let us have a look at the simplified diagram of a programmed PAL which we have just discussed. Again, it has four vertical lines representing the two variables AA bar B and B bar. It has three AND gates. Each AND gate is connected to two horizontal lines and the output of each AND gate is connected to a single OR gate. Now, we have added some input buffers. So, the variables A and B are connected to the vertical lines through these two buffers. Now, these input buffers pass on the uncomplimented variable and the complemented variable. So, A buffer is shown to give an output A and A bar. Similarly, the input buffer connected to variable B is shown to give an output B and B bar. Now, the two input lines to each AND gate is shown by a single line with a slash with the number 2. So, this represents two lines shown as a single line. Similarly, the two AND gates are connected to two input lines but a single line is shown with a slash mark indicating the number 2. The fuses are shown by cross marks. So, the first AND gate generates a product term AB. The second AND gate generates a product term AB bar and the third AND gate generates a product term A bar B bar. We have just looked at the implementation of a standard SOP function using a PAL. We have also looked at the simplified circuit diagram of a PAL. Instead of multiple inputs, we have just shown a line with a number which represents the number of inputs. Similarly, the vertical and horizontal lines which are connected to AND gate and the input terms which are connected to AND gate you have to show the fuses by a cross mark. There is no need to write more than this. Now, some of the PAL devices have outputs which can be configured. What is the benefit of that? We want to get different types of outputs. We had just talked about a few PAL devices which can be configured as an input. So, you can apply some input variables on the output pins and where the input variables will be connected basically they will be connected to AND gate input. AND gate arrays are coming to its inputs. Now, the output circuit of PAL can be configured in three different ways to give you different results. The first one is a simple combinational output. Whatever AND gate sum of product term produced will be available on the output pins if you configure the circuit to simply give you a combinational output. The second way to configure the output is combinational input and output. Basically, we can configure the output circuit and use the output pins as input or as output and input in both ways. There is a third way. We can configure the output. We can program polarity. How can we program polarity? Let's say you have a product term on the output of AND gate. The active high. You are interested in the active low. You would configure the output circuit using the third type in which you can program polarity. Let us have a look at the three circuits and let us see how we can configure the output of the PAL to give us three different outputs. Let us first have a look at the block diagram of a PAL with programmable outputs. The block diagram has been modified. It still has the programmable AND array connected to the fixed OR gate array and the output logic is shown as separate blocks. The output of the output logic is of course available at the output pins of the PAL device. Inputs are connected to the inputs of the AND array. Let us have a look at the first method of configuring the output circuit. The first method is combinational output. In this circuit, we see an OR gate which is the input of the OR gate is connected to the AND gate. The output of the OR gate is connected to a tri-state buffer. The tri-state buffer is like an OR gate which is controlled through a control line seen at the top. Let us suppose the control line is set to high. The tri-state buffer would behave like an OR gate. Whatever the input, it is inverted. The inverted output is available at the PAL output pins. In this particular case, tri-state buffer has an active low output. Whatever the input of the tri-state buffer it would be set to low. This particular combinational output provides an active low output. Let us now have a look at the second method which we can use to program the output circuit of the PAL device. It is the combinational input output with active low output. Again, the AND gate array the output of the AND gate array the output of the OR gate the output of the OR gate is connected to the input of a tri-state buffer. The output of the tri-state buffer is available at the output pin and it is also connected to another buffer. The outputs of the other buffer the complemented and uncomplimented form are connected to the input of the AND gate array. Now the output of the OR gate is available at the output of the tri-state buffer बफर is active. So, the output is active low. Now, this same output is available at the output pin and it is also available at the input of the AND gate array through the second buffer. If the control pin of the tri-state buffer is set to low, the tri-state buffer is inactivated. So, it basically disconnects the output of the OR gate from the output pin. Now, the output pin behaves like an input pin. It is connected to the second buffer which has two outputs connected to the input of the AND gate. So, the output pin is now used as an input pin. Now, let us have a look at the third method of programming the output of the PAL circuit. Now, this circuit is similar to the circuit discussed earlier. It only has an additional exclusive OR gate. Now, consider the exclusive OR gate, one of its input is grounded or permanently connected to 0 through a fuse. Now, what would be the output of the exclusive OR gate? Basically, it depends on the input. If the input is 1, the exclusive OR gate output would be a 1. If the input to the exclusive OR gate is 0, the output would be a 0. So, the output of the OR gate is connected to the input of the exclusive OR gate. If the output of the OR gate is 0, the output of the exclusive OR gate would be a 0, which would be inverted by the tri-state buffer. So, the output would be available as a 1. Let us see, if the second input is connected to 1 by blowing away the fuse, if a 0 is applied at the other input, the output would be a 1. If a 1 is applied at the other input, the output would be a 0. So, the exclusive OR gate is inverting its input. Now, if the output of the OR gate is a 1, the exclusive OR gate would invert it to 0, the tri-state buffer would invert it back to 1. So, what do we get at the output? We get the actual value, which is available at the output of the OR gate. So, by using this circuit, we can program the polarity of the sum of product terms available at the output of the OR gate. For this circuit to work, the tri-state circuit has to be active, the control pen is set to high. We have just looked at three different options to program the output of a PAL device. So, the output circuit is there, we can configure it in three different ways and take different outputs. Now, how would you identify a PAL device? It will have a unique number which we will identify. Identify what we have to do. Basically, we need to know its inputs, its outputs, and its output is active low, active high, or its polarity can be changed. So, the number is very unique and very easy to remember. The first prefix is three letters P-A-L indicating that this is a PAL device. After that, there are two digit numbers representing the inputs. So, if P-A-L is 10, that means the PAL device has 10 inputs. After that, there is a letter which could be an H, which could be an L, or P. H indicates active high outputs, L indicates active low outputs, and P indicates a programmable polarity. You can change it, you can increase it, you can lower it. After that, again, there will be a digit in which you will tell how many outputs there are. So, if you have P-A-L, 10, H is 8, so it is a PAL device with 10 inputs. H means active high outputs, and 8 means 8 outputs. After that, there is some more information like the temperature range, its speed of operation, and some extra things. Now, let us talk about the PLA device, Programmable Logic Ray. Right now, we are basically discussing its structure, we are understanding its structures. After that, we will see how these devices are programmed. So, right now, we have seen the PAL device and its structure, and we have seen that the AND gate array can be programmed, and the OR gate array is fixed. We have seen a simple example in which we have programmed SOP expression. The AND gates of three outputs are permanently fixed with OR gate. So, we do not have any choice to select any input of OR gate. The next device we are going to see is basically the Programmable Logic Ray PLA. In this, as we discussed in the beginning, the AND gate can also be programmed, and OR gate array can also be programmed. First, let us see a simple structure with some number of inputs and some outputs. The PLA devices are available in different configurations. Basically, the parameters of the number of inputs, the number of outputs, and the product terms are available. Basically, as we said, the output of AND gate is attached to OR gate's input. Now, the output of AND gate array depends on how many AND gates we have applied. So, the three limitations of PLA are the number of inputs, the number of outputs, and the number of product terms provided by the AND gates. Let us have a look at a simple PLA device. This PLA device has four inputs, three outputs, and six product terms. First, let us see the structure of the AND gate and how we can program OR gate. After that, we will look at a simple function. So, let us have a look at the structure of a Programmable Logic Ray PLA device. It has four inputs shown by I1, I2, I3, and I4. These four inputs are applied through four buffers. So, the outputs of these four buffers give us the terms I1, I1 bar, I2, I2 bar, I3, I3 bar, I4, and I4 bar. Now, these eight terms or literals are connected to each of the six AND gates. So, P1 AND gate gives a product term which can be based on six literals. Similarly, the second AND gate gives a product term P2, which again can be based on six literals. Similarly, P3, P4, P5, and P6 give us four different product terms. Again, each of these product terms can be based on up to six different literals. Now, the AND gate array is shown to be connected. All fuses are intact. To program this AND gate array, we would blow away some fuses. Now, let us have a look at the OR gate array of the PLA device. It has three OR gates giving us some outputs O1, O2, and O3. Now, each of the three OR gates are connected to six product terms. So, the output of AND gate 1, P1, P2, P3, P4, P5, and P6 are connected to the first OR gate. Similarly, the second OR gate is again connected to the outputs of the six AND gates. So, the input to the second OR gate can have product terms P1, P2, P3, P4, P5, and P6. Similarly, the last OR gate is again connected to the six outputs of the six AND gates. So, six product terms can be applied to the third OR gate. Now, each of the three OR gates give an output which is based on the sum of product terms. So, which particular product terms are used? That depends on the OR gate array. In the OR gate array, all fuses are shown intact. Now, let us suppose the first OR gate gives an output based on the first product term and the last product term. So, in order to implement this, the first fuse would remain intact and the last fuse would remain intact in the OR gate array. And the four fuses would be blown away. Now, let us program this four into three PLA device. As can be seen in the diagram, the first AND gate gives a product term which is based on the variables I1, I2 bar, I4. Similarly, the second AND gate gives a product term P2 which is equal to I1 bar, I2 bar, I3. The third AND gate gives a product term which is equal to I1, I2, I3 and I4 bar. The fourth AND gate gives out a product term which is equal to I1, I3, I4. The fifth AND gate gives a product term which is equal to I2, I4. And the last AND gate gives a product term which is equal to I1 bar, I2, I3 bar, I4 bar. Now, the first OR gate gives a sum of product terms which product terms are used. So, the first OR gate is connected to the product term P1, P2, P3 and P5. Similarly, the second OR gate is again configured to give a sum of product term. The product terms which are used or which are connected to the second OR gate are P2, P4 and P6. The third OR gate again is configured to give a third separate function which is again an SOP function. The product terms which are available or which are used and connected to the third OR gate are P1, P3, P4 and P6. So, the output of the third OR gate is represented by a Boolean expression P1 plus P3 plus P4 plus P6. And P1, P3, P4, P6 have already been defined. Now, this particular 4 into 3 PLA device can be used to program three separate SOP functions. अब यमने PLA device को देखा उसके Structure को देखा उसको नहीं पुगाम करके देखा है।