 So our speaker is Aaron Thomas, and he will talk to us about risk-v. Aaron, you have the floor. Is the mic on? Yep, okay, good. Alright, so I'm Aaron Thomas, and I'll be talking about Risk 5, open hardware for your open-source software. So how many of you have heard of Risk 5? That's a good number. How many of you were aware that Risk 5 is actually pronounced Risk 5 and not Risk V? That's actually pretty good. Okay, alright. How many of you have played with Risk 5 hardware either or emulated hardware at all? That's a few people. And how many of you have read any of the Risk 5 specifications? That's a good number. Okay, so there's people who know things about Risk 5 in the audience, so that's cool. So I'll give you a quick overview of my talk. I'll give you kind of a... The goal is sort of to give you a tour of the Risk 5 ISA, the instruction set, where it came from, kind of a quick overview and point you to the specifications, and then I'll talk about the ecosystem, so the hardware and software, the open-source hardware and software, that are available for Risk 5. And my kind of ulterior motive in coming here is to kind of grow the Risk 5 community, so I'm hoping I can get you all interested in Risk 5 contributing to Risk 5 and becoming a part of the community. So the talk, I'll start off with a little bit of a Risk 5 101, so a little bit of background on the ISA where it came from, that kind of thing. Then I'll talk about the Risk 5 hardware landscape. There's been a lot of kind of interesting developments in the Risk 5 hardware landscape. We actually have Risk 5 silicon that anyone can buy now, which is pretty exciting. And then there's a lot of open-source SOCs and chips that are out there. Then there's been a lot of work in the software stack in the last 6-12 months. A lot of open-source projects have been ported to Risk 5 and things have been upstream. Thanks. So yeah, so that's sort of the overview for the talk. Sure. I will do that now. Sorry. Is that better? Is that okay? Yeah. Alright. Okay. Is that okay? So that's the overview of the talk. A little background and then talk about the hardware and software ecosystem. So we'll start off with a little Risk 5 101. So Risk 5 is an open instruction set specification. It's an ISA. So some of the other ISAs that you may be familiar with, they're X86, ARM, Power, Alpha, MIPS. So Risk 5, unlike them, is actually an open specification. So you can build open-source or proprietary Risk 5 implementations. It's completely up to you. It's an open standard and you can do what you want with it. So if you tried to do this with one of the commercial ISAs such as ARM or X86, you might get a friendly letter from one of their lawyers. Maybe not so friendly. But yeah. So the nice thing about Risk 5 being an open ISA is that you don't have to pay any licensing fees. You don't have to deal with any lengthy contract negotiations and you don't have to deal with lawyers, which I think is a good thing as an engineer. And so, I mean, the licensing fees are a problem. So I mean, if you're trying to build a really low-cost IoT device, the licensing fees can add up to a substantial cost for your specific device. Contract negotiations can be lengthy. It can take 6 to 12 months to come to a negotiation with ARM and other vendors. And that can kind of kill you if you're a startup and you've got VCs breathing down your neck. Yeah, no lawyers, so that's good. So I'll give you kind of a quick overview of Risk 5. So Risk 5 has a very modest goal. And that goal is to become the standard ISA for all computing devices. So from microcontrollers to supercomputers, accelerators, basically any chip that you have in your iPhone system on chip, we want that to go from some sort of proprietary ISA, there's so many different proprietary ISAs to a single standard ISA and that would be Risk 5. And so, yeah, it's a modest goal. And so Risk 5 is designed for research, education, and commercial use. And our research and education were kind of the initial uses because this Risk 5 actually came from the University of California, Berkeley. They were using it for research and education. And it's also becoming more widely used in the commercial sector. People are building products on Risk 5. And if you go to the Risk 5 workshops, it's kind of interesting. So I've been to all of the Risk 5 workshops and every workshop, there's more people using Risk 5, there's more companies using Risk 5. There's a lot of interesting research people are doing with security extensions and memory models and silicon photonics. So there's a lot of interesting Risk 5 stuff that's been happening because there's an open standard. So you can blame these folks for Risk 5. These are the responsible parties. So Krista Sanovich and David Patterson are professors at the University of California, Berkeley. David Patterson actually retired recently, so I guess he's a professor emeritus. And there's students Andrew Waterman and Yonsep Lee are sort of the inventors of Risk 5. And so the story goes that Krista and the Berkeley Architecture Group, they were beginning to search for a common ISA for their research. So the way Berkeley works, or at least the Berkeley Architecture Research Group, is every five years they form a new lab to tackle some new problem. And so they were starting up this new lab and they had used a bunch of different ISAs over the years. And they were like, maybe we should start reevaluating what ISA we want to use for this specific lab for the next five years or so. And so the dominant ISAs that are out there right now are X86 and ARM. And they have a number of problems if you're a researcher. So one is that they're fairly complex ISAs. There's a lot of instructions. If you've actually tried reading the Intel manuals or the ARM manuals, they're pretty long. There's a lot of stuff in there. If you ever see Krista Sanovich on the street, you should ask him about X86's AAA instruction and see what reaction you get. So the ISAs are just generally too complex for research. So they decided against it. And then you have the IP issues. They're not open ISAs. If you try to tape out an ARM ship, you're going to get sued. So it's not really ideal for researchers. So then they embarked on... So as a result, they embarked on a three-month project with their own clean slate ISA in summer 2010. And they continued to work on it over the years and kind of refining the ISAs. They taped up more ships and gained more experience. And then four years later, three months turned into four years, they released the frozen RISC-5 user specification, May 2014. And then as people became in companies, academia and various people became more interested in RISC-5. RISC-5 sort of moved outside of Berkeley and became part of the RISC-5 foundation. And the foundation was formed in August 2015 to kind of care-take the ISA. On a personal note, I actually designed an ISA myself. I embarked on my own three-month project. I co-designed an ISA for an undergraduate computer architecture course. And it was not a particularly great ISA. If RISC-5 existed, then I would have used it. So yeah, I think RISC-5 will be a good thing for researchers and university lecturers everywhere. So the RISC-5 foundation, which was recently founded, it's a non-profit. Its mission is to standardize, protect and promote the free and open RISC-5 instructions that are architecture and also to help build up the hardware and software ecosystem for use in all computing devices. And so the RISC-5 foundation is a non-profit based in the U.S. and it has over 50 members and there's a lot more members that have been joining or are interested in joining. So we expect that to continue to grow. And there's been broad commercial and academic interest. So the last RISC-5 workshop, the fifth workshop, sold out. We had over 350 people and the attendance has been steadily going up. And so that pulled from 107 companies and 29 universities. So it's sort of a broad interest in RISC-5. So some members of the RISC-5 foundation. So you have some fairly large companies. So Berkeley, of course, is a member of RISC-5 foundation. But big companies such as Google, Hewlett Packard Enterprise, Huawei, IBM, Mellanox, Micron, MicroSemi, Microsoft, NVIDIA, NXP, Qualcomm, Sci-Fi of Western Digital. You get the picture. There's a lot of big companies that are interested in RISC-5 and kind of evaluating RISC-5 for their products and research. Other RISC-5 members, AMD, ETH Zurich, MIT, Low Risk. There's a lot of people who are interested in who are members of the RISC-5 foundation. And actually these slides are out of date a little bit. There's been a few people have been added. So the RISC-5 foundation is doing pretty well. So to go back to the RISC-5 ISA. So RISC-5 is the fifth risk ISA from Berkeley. So the earlier risk research was done at Berkeley in Stanford in the 80s. And so they've done a number of risk chips over the years. So this is the fifth risk ISA from Berkeley. So it's RISC-5, so the Roman numeral 5 or V. And the nice thing about RISC-5 is the modular ISA. So it has a simple base instruction set. It's fairly small. And then you can layer extensions on top of it. So it has this base plus extension model. And so there are 32-bit, 64-bit, and 128-bit versions of the ISA. And yes, I did say 128-bit, it turns out. So the ISA itself is the base ISA is fairly small. There are fewer than 50 hardware instructions in the base ISA. So this makes it feasible to implement microcontrollers and really small cores. And as I mentioned, it's designed for extension and customization. So you take a RISC-5 core, and you basically can customize it to your application. And this sort of comes from the base plus extension model. So to just kind of go over the base ISA. So there are different base integer ISAs for each word with. So the 32-bit RISC-5 instruction set, the kind of naming scheme is rv32i, and i stands for integer. 64-bit is named rv64i, and 128-bit is rv128i. So the way RISC-5, the kind of naming scheme is that they have these one-letter names for extensions. So i stands for integer, and there are a number of other standard extensions. So m stands for integer, multiply, divide, a stands for atomic memory operations, f is the single precision floating point extension, and d is the double precision floating point extension. And so because all of these extensions are fairly widely used and necessary to boot up in general purpose operating system, they're lumped into this GISA. So this includes the integers, your multiply, divide, atomic, single and double precision floating point. And this is the ISA that you'll use if you want to boot Linux or BSD or something like that. So in addition to the standard instruction sets you also have, you can build your own non-standard extensions as well. RISC-5 is designed for that. So kind of the cool thing about the RISC-5 ISA is that it's small enough that you can actually fit it on a sheet of paper. So this is a green card for the RISC-5 ISA. It's not actually green, it's called Back in the Day, or so David Patterson tells me. So the nice thing is that the base integer instruction set is, you can list all the instructions in one column, basically in the left column. You probably can't read them in the back, but the RISC-5 ISA looks kind of like a standard RISC instruction set. You've got loads, stores, shifts, arithmetic operations, logical operations, compares, branches, that sort of thing. So it's pretty familiar if you've done any hacking on any RISC ISA in the past. At the bottom you can see some of the instruction formats. They're designed to be efficient for hardware implementers. The rest of the sheet actually shows the optional compressed extensions. So they have some extension for better code density. And then the back of the sheet has some of the other standard extensions, your multiply, atomics, and floating point, all this stuff. So there's enough room to actually include the RISC-5 calling convention. So it's a pretty kind of lean ISA. So you can look at the specs for the details. I'm sure you couldn't read that, but the specs are online. So you can check out the user-level ISA specification, version 2.1, to find out the details of what the instructions look like, what do branches look like, that sort of thing, what do loads and stores look like, what kind of arithmetic operations are available. The privileged ISA specification is in version 1.9.1. So the privileged ISA is actually, this is kind of the interface that the OS and firmware uses. This is actually in development, so version 1.10 will be released soon. And if you want to look at these specification sources, if you want to look at the actual LaTeX sources for these specifications, you can actually find them on GitHub as well, because it's an open standard. So now that we talked about the ISA as a whole, we're going to talk about the RISC 5 hardware landscape, some of the open source SOCs and cores that are available. So there's a lot of RISC 5 cores and SOCs, and they're designed for many different use cases. So some of the main use cases are education, research, and commercial products. And we'll see some of the examples here. And so you have cores that are really designed for small, low-cost microcontrollers, and you also have like high-performance, like multi-core chips as well. There's more of this over time. RISC 5 is still fairly new, and you see a lot of cores popping up and a lot more people developing RISC 5 now than even a year ago. And these cores are written in a variety of hardware description languages, or HDLs. So the ones you've probably heard of are VHDL and Verilog, and so there are RISC 5 cores, many of them that are written in VHDL and Verilog. Some other languages that you may not have heard of are Chisel and Blue Spec System Verilog. And so these are newer HDLs that are a bit higher level and in some ways a bit more productive. So some of the Berkeley cores, the Berkeley cores are actually written in the Chisel hardware description language. So I'll quickly talk about UC Berkeley and Psy 5 and the relationship there, just because a lot of the cores that I'll be talking about originate at Berkeley and Psy 5. So the Berkeley Architecture Group, UCV's BAR group, created RISC 5, so this was Chris Desanovic and David Patterson's group, as they were developing RISC 5, they also developed a number of open-source cores and SSEs for research and teaching. And eventually the RISC 5, so the graduate students, Andrew Waterman, Yonsepli, like graduated and they wanted something to do, so they decided, hey, this RISC 5 thing's kind of cool, and so they decided to found a company called Psy 5 with Chris Desanovic, and they basically designed custom RISC 5 chips for customers, and they're building on their open-source cores to do that. So it's kind of cool that they're actually a company that's doing open-source stuff, and they continue to contribute back to the cores that they built at Berkeley. So some of the Berkeley hardware that's out there, so for the system on ship, there's the rocket ship, and it's a parameterized RISC 5 SoC generator. Because it's parameterized, you can tweak the number of knobs that you can tweak. You can tweak the cache hierarchy, the number of cores, the TLB size, whether it's a floating point unit, whether it isn't, and it makes it really easy. You basically go in a config file and you can tweak the core to your needs. In addition to the system on ship, there are a number of cores you can choose from. So the rocket core is kind of the standard core that many people use. It's a five-stage pipeline, single issue. There's also BOOM, which is an out-of-order core. It's a research project by Chris Ceeley at Berkeley, and it's actually pretty cool to study the source code of an out-of-order core. There aren't that many out there for people to study. Berkeley also has a set of educational cores called SOTR. They're one-stage all the way to five-stage, and they're designed for simplicity so people can understand them in university courses. And you can find all the code on GitHub, which is pretty cool. So quick note about the rocket ship SoC generator. So as I mentioned, it's a parameterized... It's a parameterized SoC generator, and it's written in this chisel HDL. And so chisel is this new hardware description language from Berkeley that's an embedded Scala DSL. And so Berkeley uses it, and SciFi uses it for all of their cores. And so by using the rocket generator and chisel, you're able to target a few different backends. So you can target a C++ software simulator, which is basically an executable that simulates your risk five core. You can target an FPGA by targeting the FPGA tools, for instance, your Xilinx tools. Or you can target some of the ASIC tools, like Synopsys or Cadence. And so the nice thing about the rocket ship SoC generator is because it's parameterized, it's designed for customization, you can use this as a basis for your SoC. It's all open source, and you can use it for your application. So as I mentioned, you can either target FPGAs or actual real hardware. And so SciFi has been doing this, and they've been building on the rocket core and the rocket ship SoC generator. So they have two platforms now, the Freedom Everywhere, which is their low-cost 32-bit microcontroller product. And they have the Freedom Unleashed, which is the high-performance 64-bit multi-core SoC. This is kind of the Freedom Everywhere will run your kind of like real-time embedded operating systems, and the Freedom Unleashed will run Linux, BSD, that sort of thing. And you can find their code on GitHub as well. And so here's the cool hardware. So SciFi has these FPGA development kits. And so the RD board, which is about 100 on the left, is about $100 US, and you can use that to emulate the Freedom Everywhere. It's in the microcontroller class, and there's a little display hooked up on the right. It's Xilinx VC-707, and it's emulating the Freedom Unleashed. So this is the general-purpose core that runs Linux. And so the cool thing that you can probably see is that they're running DOOM, and they actually did this demo at the last RISC-5 workshop. And so it's kind of cool that you can run DOOM on a RISC-5 hardware. It was kind of a pretty cool demo. So RISC-5's kind of making progress. So FPGAs are cool. I really like FPGAs, and even more exciting is that there's actually RISC-5 Silicon now. So the Hi-5 One board is the first generally available open-source RISC-5 Silicon. There were people who had RISC-5 Silicon, but basically they fabricated themselves, so you either had to basically fabricate your own RISC-5 chip or have a borrow one from a friend, but now you can just go on Crowd Supply and buy one for yourself. So the Hi-5 One has the Freedom Everywhere 310 SoC. So this is the microcontroller core. It's Arduino compatible, and it supports the Arduino IDE, and it's about $59 U.S. from Crowd Supply. And a Hi-5 was kind enough to donate three boards, so I will be giving three boards away at the end of the talk for people to play with and hopefully port some more open-source software and just do that kind of thing. So the chip and the Freedom Everywhere 310, the chip in the Hi-5 One is open-source. So all the RTL source code, FPGA strips, board support packages are all on GitHub, and you can find the documentation board schematics there as well. So that's actually pretty cool. Another interesting project, another interesting RISC-5 SoC is a low-risk project. And some of you may have seen the talk two years ago here at FOSDEM that Alex Bradbury gave about low-risk. So low-risk is based at the University of Cambridge, and they're aiming to build a really low-cost development board. The tagline is Raspberry Pi for grown-ups. And it's... So it was actually founded by one of the founders of Raspberry Pi, so they basically want to create a completely open version of the Raspberry Pi, so that's actually, I think, pretty cool. And it also builds on the Rocket Ship SSC generator from Berkeley in Hi-5. And they're doing some interesting research things with tagged architectures for security and a minion cores for IO offload. And they have a couple tech notes about this, and I think they're doing some pretty cool stuff. And yeah, you should definitely check out Alex Bradbury at FOSDEM 2015 talk and just follow their progress in general because they're doing interesting things. And their code is also available on GitHub. So the shockty cores from IAT Madras are another set of RISC-5 SoCs. So RISC-5, apparently, is the standard ISA for India, which is kind of cool. And so as a result, IAT is building six open-source cores, and they're, like, literally going from microcontrollers to supercomputers. And so there's a lot of people building a lot of RISC-5 hardware there, which is pretty cool. And they're using BlueSpec System Verilog as their HDL of choice. And you can find their code on Bitbucket, not GitHub. And so some other RISC-5 SoCs and cores that are available. There's Pulpino from the ETH Zurich. There's PicoRV32 from Cliff Wolf, and this is meant to be a really size-optimized RISC-5 implantation, 32-bit RISC-5 implantation. And there are a lot of other commercial and open-source RISC-5 cores that are out there, like too many to name. It seems like there's a new RISC-5 core popping up every day. I mean, there's a lot of people who are just kind of trying to build their own RISC-5 core, which I think is pretty cool because RISC-5 is an open standard. If you're a hacker, you can just go and build your own core, which is, I think, pretty cool. So if you want to customize RISC-5, I mean, the nice thing about RISC-5 is it's designed for customization. The easiest way to do it is to modify the tunable parameters of an existing core. So basically, you'll just grab the rocket ship and then play with some of the parameters, disable the floating point unit, mess with the cache hierarchy, et cetera. You can implement your own RISC-5 accelerator. You can implement your own RISC-5 instruction set extension. If you... Chapter 9 of the user specification has some information on this. And if you think it's useful enough for... If you think it might be useful to other people, you can submit it for standardization. And if you have a lot of time on your hands, you can implement your own RISC-5 core. So, yeah, there's been a lot of interesting stuff happening on the hardware landscape. So on the software landscape, in the last six to 12 months, there's been a lot of stuff happening as well. So just to kind of give you an idea of what development platforms are available. So if you don't actually have FPGAs and you don't have RISC-5 hardware, you can use a RISC-5 emulator. So Spike is kind of the standard RISC-5 simulator. So it's also called RISC-5 Isosim. It's kind of the golden model. So every time a specification update is released, the changes go into Spike. In addition to Spike, there's also QMU, which many of you are familiar with. So the QMU has RISC-5 support, but it's not upstream yet. We have support for full system and user emulation. So this is actually pretty cool. So there's another simulator called RISC-5 Emu, built by Fabrice Belard. And you can boot RISC-5 Linux in your browser, which is, I think, pretty cool. You should all go do that now and see if you can crash. Don't do that now, but it's pretty cool. So it was kind of funny. So Fabrice Belard is one of these guys who's super productive. So I get an email from him and he's just like, oh, yeah, so I built this small project. It's a RISC-5 emulator. It boots Linux in the browser. It has 128-bit support and some other stuff. Even Spike doesn't have 128-bit support. So he's like, I don't know. I didn't even know he's aware of RISC-5, so it was a pretty cool one. He was like, yeah, I got this little project. He does all these things. He's an impressive guy. So yeah, RISC-5 Emu is worth checking out. RISC-5, which is a full system simulator that's used by computer architecture researchers, and hopefully we can get that upstream and kind of farther along. So a quick note on Spike and QMU. So Spike is great for prototyping hardware features. I use it a fair amount. The nice thing about it is it has a really small and simple code base, and it makes it really easy to add instructions and customize the ISA and everything. But if you're doing software work, I think QMU is probably a better option. The emulation is faster. It's got a number of handy debugging features. It's got better device support. There are a few rough edges in QMU RISC-5 now, especially with respect to device support, but we'll be ironing it. We hope to iron them out fairly soon. So yeah, but both are good emulators. With respect to the RISC-5 tool chain, there's been a lot of progress. So I'm excited to report that RISC-5 support will be in Ben Util's 2.28, and the GCC Steering Committee has accepted the RISC-5 port for inclusion. So the port will likely make it into GCC 7.1. So this is due to a lot of hard work by Andrew Waterman and Palmer Dobbelt and thanks to all the GCC maintainers and reviewers for reviewing patches and making this happen. Now that we have the tool chain stuff, I think Linux distros and more of the software-enabled stuff will just fall out. The lack of an upstream tool chain really kind of was kind of slowing down some of the software efforts. So now that we have upstream tool chains, I think the software-enabled stuff will go a lot faster. In addition, there's an LVM port in progress. Some of the patches are upstream. Alex Bradbury from the Low Risk Project is working on this. There are a number of... He's working on co-gen patches. They should go out in the next week or two. His goal is to basically make this the cleanest back-end, and he wants the RISC-5 port to be the kind of exemplar for all the other architectures that come after it, so he's building a really clean port. And so as a result, it's taking a little bit longer, but I think it's going to be exciting when it's done. There's a lot of people who want to have LVM RISC-5. So we have a lot of RISC-5 OS and firmware ports in progress. They're all in various stages. Some are more mature, some are fairly early. So in terms of firmware, the kind of standard firmware right now is there's this Berkeley bootloader, which is kind of an initial firmware, but people are working on core boot and UEFI support, so that's coming online. For Linux, there are ports in progress for Fedora, Debian, Gentoo, and Yachto Poke. So Fedora has about 2,000 packages building. It's a little out of date. Debian has a little over 1,000 packages. Manuel's in the audience somewhere. You can talk to him about Debian. Yeah, so if you want to talk more about Debian RISC-5, you should talk to him, because it'd be great to get more people working on that. There's a Gentoo port. It's a little out of date, but Polymer will update it as soon as the stuff goes upstream. The Poke distribution, which is an embedded distribution, has been updated recently, and it's actually a reasonable platform if you want to do RISC-5 hacking. It's not upstream yet. We'll have to start pushing that stuff upstream as well. If you're a BSD person, FreeBSD actually has pretty good support for RISC-5. There's a couple things that need to be added, but FreeBSD actually has upstream RISC-5 support, which is pretty cool. NetBSD has a port in progress, and there are a number of other operating systems that have RISC-5 ports in progress, and these tend to be more embedded operating systems. So, SEL-4, Chinode, Hellenos, Zephyr, FreeRTOS, R10s, Minute. So the software stack is getting there kind of steadily. And the most exciting thing is that we have a couple operating systems that have upstream RISC-5 support. FreeBSD and FreeBSD 11.0 and the Zephyr kernel from the Linux Foundation also has upstream RISC-5 support. So that's actually pretty cool. The software stack is starting to come together. There are a number of RISC-5 language efforts in progress. For Java, there are people working on OpenJDK and JikesRVM. There's a Go port. There's a talk about Go at the last RISC-5 workshop. So there's a few Google people who are working on Go RISC-5, which is, they're making a lot of progress in a short amount of time. There's people working on OCaml and Haskell support for RISC-5. CompSert is a formally verified tool chain. It's also got RISC-5 support. There are people from Rust who are interested in getting RISC-5. It hasn't started yet, because they're kind of waiting on the LVM port. But I think once LVM comes in, we'll see a lot more language efforts kind of getting farther along. So there's a lot of action on the RISC-5 software front. So what's next? So we're preparing the Linux kernel, and we will be preparing the Linux kernel, GLib C, and QMU patches for upstreaming. So one of the things that's been kind of holding back some of the distros is the lack of upstream Linux kernel support in GLib C. So it looks like the Linux kernel support, the patches look reasonable. Some of the maintainers have looked at them. And there's a few issues that need to be fixed, but once they get fixed, hopefully those patches can go in. And then there's some work on GLib C as well. There's also some more work on standards. We need to flesh out our ABI specification. We also need to work more in the privileged specification, because it's not a frozen spec yet. It hasn't been ratified. So there's some more work to be done there, and this will be done sort of in parallel with the upstreaming of the Linux kernel and GLib C stuff. So as I was saying, once the Linux kernel and GLib C get upstreamed, we're going to continue... It'll make it a lot easier to do Linux distros. So we'll continue to kind of improve and update our Linux distro support and upstream those changes. And if there are any distro people in the audience, we'd love your help with getting RISC-5 on your distro. And in general, we want to port more software packages to RISC-5. So if you're a maintainer of any software packages, we'd love to work with you to add RISC-5 support. And yeah, so in general, we want to push RISC-5 forward. We hope you'll kind of join the RISC-5 community and kind of help kind of with some of these software tasks as well as some of the hardware stuff and documentation as well. So if you do want to get involved, there's some resources that you can check out. So all the codes on GitHub, so that's the GitHub organization. We have mailing lists for hardware development, software development, and development of the ISA. The RISC-5 workshop proceedings are online, so both the slides and the talks. And this is a good way to kind of get up to speed with what's been going on in the RISC-5 community. There's a stack overflow, so if you have questions about RISC-5, you can ask them here. Once you learn more about RISC-5, you can answer the questions. That would be great too. There are a couple articles in microprocessor report that sort of describe the RISC-5 ISA in general. If you're new to RISC-5, these are worth reading. So the first one kind of talks about the rationale for having an open ISA, and the second one talks a little bit more about RISC-5 particulars. There was an IEEE micro article written by the Berkeley folks about their agile approach to building hardware and RISC-5 microprocessors. And that's kind of interesting, because a lot of what they're doing is using open source and the Chisel HDL, a higher level HDL, to build hardware more quickly. So there are a number of upcoming RISC-5 events. If you're able to, it would be great if you could come to some of the events. Meet the community and get involved. So May 9th and 10th, there's the sixth RISC-5 workshop. It'll be in Shanghai, China. This is the first time the RISC-5 workshop has been outside of the U.S., so that's pretty exciting. It's hosted by NVIDIA, I forget the name of the universe, Shanghai. Yeah, I'm going to draw it over. And then March 14th to 16th, there's an embedded world. So a number of RISC-5 foundation companies will be exhibiting there. April 2nd to 3rd, G. Madras is having a RISC-5 conference. And so they've been doing a lot of work with RISC-5, so you'll hear more about their shock decors and you'll also hear about RISC-5 projects from all around the world. So that should be a cool event. September 8th through 10th, there's ORConf in Hebdenbridge, U.K. So ORConf is actually an open RISC conference, but they've kind of opened it up to RISC-5 people, so there'll be a fair number of RISC-5 talks there as well. So in summary, RISC-5 is an open instruction set specification. You can grab it, you can do it, you can build proprietary cores, you can build open-source cores. You don't have to worry about getting sued, which is good. But it's... And because it's an open instruction set specification, there's a lot of open-source cores that are available. So there's several options. I talked about the rocket ship, low risk. There are a number of other options that are available as well. I just highlighted a few of them. The RISC-5 software stack is steadily coming together. Things are getting upstream, distros are happening, and we love your help there. And in general, we're looking for contributors all across the hardware software stack. So the takeaway is that you should hack on RISC-5, and I hope to see you at one of the many 2017 RISC-5 events. Thank you. Sorry. Could you speak? Yeah, so this is one of these things that's sort of difficult. So I think the question was about what peripherals are available in the SoC and the bus. So Axi. Right, so this is a question about specific implementations. So for the rocket ship implementation, the bus that uses Axi, and they have, I don't know, they have spy devices, PWM, they have, I don't, I actually don't, they have some GPIOs. So this is one of these things where there are some devices, but there's going to be more work that needs to be done. And so I think the Free Chips Foundation, the Fawzi Foundation, LibreCores, I think together we'll have to work together. So there are some peripherals there in the SoC. I don't remember all of them offhand, but there definitely will need to be work there. There are no GPUs, for instance. That's difficult. But for a lot of the embedded peripherals, a lot of some of that stuff is there. I think we have USB now. Maybe, I don't know. So that's an implementation question. And so it depends on the implementation. So the ISA, I mean, it really depends on the implementation. So the Hi-Fi board can be clocked at 320 megahertz. They're using a TSMC 180 nanometer. The Freedom and Leash platform, they've quoted, they're going to use, TSMC 28 nanometer. You can clock that at 1.6 gigahertz above. 1.6 gigahertz and above is what they've quoted as. So it sort of depends on the implementation. Yeah. Actually, do you want a board? All right. Anybody else? You. Yeah. Yeah. That's a good question. So the next RISC-5 workshop that's outside, the first one that's outside the U.S. is going to be in China and sort of what about Europe, I think was the question. Yeah. So actually we were hoping to come to Europe. Just because of the timing. I mean, there were a couple venues that were discussed like Cambridge and Zurich, and it was mostly a timing thing. So we're definitely going to come to Europe. It was just the dates that we've set up were kind of difficult with university calendars and things like that. There will be some RISC-5 meetups that we haven't scheduled yet, but we're hoping to have a couple of RISC-5 meetups. There'll be smaller events in Europe. But yeah, we definitely want to have a foundation event soon in Europe. Probably, I assume, I think the next one will probably be in the U.S., but hopefully sometime next year we can get to Europe. But there are a lot of other, we'll definitely be holding smaller RISC-5 events. Sorry, what was that? I don't know about this year. So the question was will some of the RISC-5 founders come to ORConf? Yeah. So they've been to ORConf in the past, like two years ago they gave talks there. I don't know if it'll happen this year, but I'll see if they can make it, or some other RISC-5 people. Yeah, I think in general we should get more RISC-5 people going to ORConf events and come into Europe. You get aboard too. Does anybody else want to? Oh, yeah. The guy with the microphone. So now that you've tackled the CPU and thanks, how about pretty please with sugar on top start tackling the GPUs? Yeah. Please. Yeah. That's a good question. Yeah, so the GPUs are hard. There are some, I know there are some academic efforts that are building their own GPUs. But I think the RISC-5 foundation and some of the other, like, Fawzi Foundation, there's a new pre-chips project that's been founded and basically they're kind of taking over some of the, they're playing the foundation role for the rocket chip. So their goal is to build more open source IP blocks. I think the GPU is going to be hard. We need to get a lot more people working on that. So I think it's probably going to require collaboration between all the open hardware projects. There's a couple of academic projects that look promising. I don't remember, honestly. Yeah, I don't remember where they're from. Yeah, open GPU university. I'll ask some people about it because I remember hearing about a couple that seemed kind of promising. I mean, the other thing you could do is just post to the RISC-5 mailing list Hardware Dev and just get a discussion started. It's not a priority for us right now. There's a lot of other things we have to work on. The open hardware community as a whole together, we should definitely tackle that. Yeah, GPUs are hard. Open GPUs are hard, too. Yeah, we'll get you afterwards. Is there besides the instructions that you've shown here today, do you have any ideas about something like SIMD? SIMD, okay. So there's a vector extension that Krista's working on. So Krista's apparently worked on, like, vector machines. Kind of like his whole career. So he and some other old school vector people are really excited about putting, like, a vector proposal together. So there's been some discussion about it, but it's going to take a while to kind of standardize. If you're interested in that, you could talk to people on the ICDEV mailing list. We also have working groups at the RISC-5 foundation meetings. So there are people who are interested. In particular, it's all about vectors, so something will happen. I can't promise anything in terms of timeline. Yeah. Someone here had a question. Yeah. Oh, sorry. So you want to buy a sci-fi chip? Yeah, just a chip, not a board. Are they available for your own designs? I'm sure if you email sci-fi, they'll still use some chips. So you don't really know. Yeah. I mean, so their business model basically is that they'll do custom design for you. So I'm sure they'd be happy to sell you chips if you have some sort of board that you want to build or something. It's a pretty nice chip. About the openness, you mentioned a lot of times that it's open and there are no lawyers involved and there's nothing to be afraid just copy the implementation of the course and edit. What's the license? Are there any patent issues? Is there one license for all implementations? That's a good question. So the license depends on the implementation. So the Berkeley course under the BSD license, sci-fives licensing, some things under Apache, other people are using the ISC license. I'm sure there's some copy left like GPL hardware as well. So it's sort of up to the project to decide what license they want for their specific implementation. Yeah, absolutely. It can be proprietary as well. So if you're a company, and there are several companies doing this, because it's just a standard, you can implement your proprietary RISC-5 chip and that's completely fine. Yeah, is that everybody? Hi. What peripherals are available on the RISC-5 MCU that they're selling now? Yeah, okay, so... Like SPI, I2C. Yeah, so it has some SPI, it has some GPIOs, it has some PWMs. I don't remember everything else. The crowd supply page will have all the details, but it's Arduino compatible, so you can put like Arduino shields in there. So there's a couple Adafruit shields that they use, and there are demos. So I don't remember all of the details, but if you go to the crowd supply website, it has all the details, and there's the data sheet. Yeah. Sorry, there's a question back there. So the question was, are there implementations using multi-threading? So there are multi-core implementations. Are you talking about like symmetric multi-threading, like hyperthreading? I'm talking about having maybe several program counters, several registered banks, and you can select which program counters every cycle. Find great multi-threading. Yeah, I don't know. They may exist, I'm actually not sure. I don't think the rocket ship does that. I think the rocket ship is just multi-core. So it doesn't have like hyperthreading or anything like that, or SMT. There were some questions back there. Okay. Okay, so the question was, are the specifications frozen, and what's the risk about if you buy hardware that it doesn't match the specification? So the nice thing about, so the specific, the high five one board only implements the microcontroller spec. So, or, it's a microcontroller, so it doesn't implement the privilege specification. So the stuff that it implements is frozen. But the privilege spec is under development. Hardware that is using the privilege spec. There actually isn't any generally available, but that could be a problem there. But we're hoping to standardize the privilege spec this year. So hopefully none of the hard, I think it's unlikely that hard roll will be out that doesn't match the spec. That's generally available. I mean, you can build your own test ship. Several people build test ships with the earlier version of the privilege spec. So two things. As you mentioned, GHC, the Haskell compiler, it's actually pretty easy to add basic architecture support to GHC. You just have to like edit two lines of Haskell code or something and like Autocon. I've actually been doing that in the past quite a lot for like Super H which is like now being redeveloped as an open source architecture. And the second thing in general is so in Devian developer and in Devian we have this project called Rebootstrap. I don't know if you've heard of it. It's basically like an automated system which allows you to cross bootstrap a new architecture. So it's like it's an amazing effort and you just run a simple script and in the end you end up with like the minimum set of packages cross-built for the new architecture that you need to be able to bootstrap meaning that you can build it on the build, the Devian built infrastructure. And the nice thing is that it's constantly running on a Jenkins job so we are like basically verifying all the time like if something you know is cross-boot strappable or not, packages cross-buildable and so with this mechanism we are actually fixing all the bugs and making new architectures built on Devian and we of course upstream build all that stuff. And open risk is included in that. That sounds cool. Manuel, I guess you know about it? Sorry? Sorry, it's not going to Manuel because he's done the Devian risk 5 port. I was like, Who? Manuel? No. Yeah, so he's our Devian guy. Can I get a board? Sorry. I think these two guys got one. If I have more, yes. There was a question there, yeah. Yeah, that's a great question. So there's a question about whether there's a certification program to make sure that the standard is followed. So that's actually something that the Risk 5 Foundation is working on. So it's kind of key that we're building out these compliance tests and so we need to make, and that's kind of like going to verify that you are meeting the Risk 5 standard. There's also been some work on building a formal specification of the Risk 5 ISA that's kind of different, but related. So that's in progress, but it's still pretty early.