 We want to design an or maybe at least minimum maybe necessary for example many times CMRR is not specified because one believes for the gains we talk about bands we talk CMRR will match requirements okay but if not you evaluate and figure it out. I again repeat for those who need not make any mistake DC gain has nothing to do with it is AV0 mid band gain okay do I know okay the other parameters to worry about in design are power supply rejection ratio PSRR the output impedance some stands are specified this is sometime very important in fact in some larger circuit where impedance matching for the power transfer is very relevant so sometime they do specify output impedance then one of the major worries which most amplifiers or any analog circuit is worried about is the noise limits and we will evaluate independently noise we will have after this after OTA design we will discuss noise noise is a very interesting noisy area so it is fun to know about noise okay and one who does not understand noise makes noise so I am the one okay. Layout area is also one of the constraint essentially it comes from the technology node you choose and the area if it is a opium is a part of a digital analog mix circuit then some area is specified for you okay this is the area then you have to fit in somewhere all of it what they want okay so the out area was sometimes the limits then there are constraints which I call boundary constraints for example any design you choose the silicon chip if you have to fabricate the design which will date on a specific technology node because if you are doing spies or any KDM simulations including layouts including schematic and everything you have to specify node because only then you will get technology file okay so first thing you have to decide this chip has to be designed on what node okay and I keep saying if you are 100% analog chip do not go beyond 180 or below 1.18 microns everything is working well with 180 nanometers and things will start deteriorating as you cross 100 nanometer down okay so if you are only looking for analog blocks or analog block then always prefer 0.25 micron as the best of technologies cheaper these days by cost therefore most of the chips which IIT Bombay student do is only on 0.25 because per mm square a cost is the minimum right now okay 0.1 it is 1.8 times of 0.25 so same area so that is to worry so node is the first thing you have to design decide with as I said typically my data from the books which I am using they have a 0.8 micron data spice file so it does not mean that one cannot design it any other this you need actual data from the spice file whichever node you are using since I have copied it from the given book so they have a 0.8 spice file so which I am just using for my calculations the second worry for the boundary constraint come from the threshold voltage available for that node and what is the beta dash value that is what is the mobility one gets this is one of the data spice file specify mu and of course they also specify oxide thickness so mu C ox is known for n channel and P channel because mu and mu P are separate so you will get beta n dash and beta P dash you also have to know something about the subset bias parameter is gamma and also the saturation parameter lambda now you will also see that some data which I have given lambda also is a function of lengths okay so at what lengths you are working even if node is anything you must figure out what is lambda there so generally spice allows you to know at different lambda values at different lengths okay then you have to specify VDD VSS typically technology node almost decides for you what is your VDD and VSS but it is not compulsory I can have any requirements I can create on chip the other biases and can work if necessary but typically one does not want to do that we use whatever is given for the node for the 0.8 microns 5 volts total supply is required so they generally will make VDD 2.5 VSS minus 2.5 so that the total swing is 5 volts supply current and the range there is a maximum current which chip can use under this you know because it will start heating so the I max is also sometime provider which is not the current you will use in any analysis but it is the it never should exceed that value okay so it is called supply current also kind of resistances it assumes which means what the power supply can it deliver this please remember current can be delivered as per you may have 3 volts supply 5 volts supply but the resistance down decide what current maximum it can draw so that therefore they specify for given voltage what max current you can draw from the supply that you have to know how much is available to you and then finally the operating temperature range your chip is going to operate okay. For all this given specified this as well as given the most of the parameters design specs you can design the op-amp and when I say design my output is the W bile size of all the transistor in the chip okay because once I get the transistor sizes layout is relatively simple automation can be done and you will be able to actually design the chip so our output as far as the design course is concerned is the size future further I had many other things are important but this is the output from our side that is the end for us okay. So as I said these are constraint these are those are specs we have already seen this circuit I will repeat again slightly modified one not really modified only bias circuit has been added this is my single ended to stage amplifier defam plus gain stage and this is the biasing circuit this R can be replaced by diode if necessary and so this is your actually current bias current you are creating now many a times you need voltages okay let us say you want to bias with VB okay so I put two diodes each will have some voltage drop so we really minus that and will at this current what W bile you choose I can decide what drops it has so I can create a V bias of my choice I may put even three okay so but to know all that W bile for them I will need current and current comes from M4 okay or M9 okay sorry you must be observing these are M1 M2 of the input stage M3 M4 of the current diode connected loads the current is created out of M5 from the mirror side so this is your ISS current going through M5 this is the C1 capacitance which we discussed and there is this feedback mirror capacitance CC and then there is a gain stage M6 M7 forms the gain stage and the output capacitance which includes load so that is our seat now you must be finding out that somewhere I did not put some number which number I missed 1 2 3 4 5 6 7 9 so 8 I missed so somewhere 8 is going to come okay so I just left that right now additional resistance will be required and we will see where the where that will come so one can find if you know VDD and you know the W bile we know from this what current is flowing through this minus this divided by R is the current VJs of this and these are same this is a current mirror so nothing great happens so whatever current is here can be transferred here excess voltage is generally known for N channels for given technology to use that so you can you will be able to get the currents in this arm and size wise it will give you whatever current you want in M9 normally M9 currents are same as M12 and then increase ahead whatever currents people are asking so this basic mirror is not really great but normally same size voltage is created out of the diode drops okay and to get this drop you know what the unit current so you know this current is this so you can figure out what drops VDD minus that is your VB so for example tomorrow you want to bias this as a current source M3 M4 you can create V bias of your choice and actually connect there is that clear to you so why I use this because in case tomorrow you want double ended outputs and you have a current source biasing you can use one of the bias points to reach there if you want very finicky about this that this voltage is not very good what should I put there instead a band of reference can be introduced there and that voltage can be used for even stricter control on VB but simply this is good enough in many cases so this is the circuit which we want to design no I just now said in case tomorrow you want a current biasing then you need VB so the bias circuit is normally kept common for everyone there are whosoever wants you can pick up whatever he wants this is general in our case this whole arm may not be there we can directly you can leave M9 M10 M11 full arm okay you can directly form for M5 this to M5 so it is not that is necessary but general biasing we do keep additional arm and there we actually use the same current and figure out what bias I can create okay so is that clear to you I am I am why I will not write now design for you the value of M10 M11 M9 M12 this can be independently handled as bias circuit and we will not write now in our opamp design to first extent we will not design the mirror part because which we can anyway independently design this has nothing to do it ahead so that can be independently designed but just to show you that how much circuitry is essentially in an opamp is connected there you are right good question but I just now said this is a general biasing scheme we bias is not used by me but tomorrow let's say I do not want diode connected load and I want current source loads I need bias so I use this so this is independently created and views whenever you want different bias you put different diodes is that clear you can have another arm and put three diodes there or maybe four whatever it is and you can create different BB values to actually suit your different circuit requirements wherever it goes but this is not redesigned it always comes once and you reused every time okay okay so this is my circuit which I want to design so I will like to define design for given specifications you now start the value of W by L for M1 M2 M3 M4 M5 M6 M7 this is what output of my design will be okay is that okay so this is what we are going to so on what specs we want to design everyone run the circuit this morning only accept that this part the rest circuit is same okay also I said you this CC is I have connected I knew it because I want stability anyway I want to split so I am going to put it the value I may now choose how much I should be okay that's the only thing but otherwise I will not go by CGD I actually put CC there okay is that okay so we go for the specs now these are arbitrary specs nothing very great but typical specs and these are good enough specs in many requirements you have a DC gain I want more than 4000 and I keep telling you that the values are not specified in design exact numbers no one says 4972 no one says so okay I want a gain DC gain which should be larger than 4000 okay they do no no the design itself they will say now how much for gain for opam is designed for a gain gain greater than something the reason is that that when you design a chip a circuit with this opam you should only use 4000 that is called over design it may be 4000 5000 also is that correct but not just that in during the design itself I may go any other value than 4000 because you the specs is that not less than 4000 so I have no parameter which I can play with okay for some specs to me I figure out that AV0 should be 4500 so I will put 4500 because the design says it should not be less than 4000 so I meet the those specs in but once I designed it once I got it those specs are fixed one chip is this done then it's not changed again and again till you fix you are the parameter to vary on then the power supply is 2.5 VDD and minus 2.5 VSS so your total current total swing of 5 I have a gain bandwidth requirement is 6 MHz then I have a load capacitance which is C2 in our case okay which is 10 pop so all our capacitance plus CL all adds up to 10 puff okay they don't just go by CL it's a total C2 is 10 puff. Alternatively you evaluate the without CL all the values by the formula we give and add the external CL value and you say that is C2 now okay that okay for evaluation right now some number is chosen which is higher enough compared to others we are also told this minimum slew rate should be 10 volt per microsecond that is the output voltage should rise in a microsecond up to 10 volts okay that is called slew rate so we are DV0 by DV minimum required is 10 volt per microsecond then the output swing this is also interesting parameter we want output to be though the power supply is 2.5 minus 2.5 the at least output swing between minus 2 and plus 2 okay then ICMR which is common mode input common mode range V in max V in min so V in min is 1.15 okay slightly not correctly shown but it is 1.15 volt you will be figuring out that if I increase to 1.5 it will not be satisfying saturation so I first thought 1.5 then I looked at it I said reduce to put one extra there that's the way it is okay because I didn't aspect somewhere so I just think I said oh a calculator or not one level before yeah but that gives me 0.35 shifts that's good enough okay and the maximum in maximum is 2 volts available to you power dissipation P dissipation is less than 2.5 milliwatts this includes power in the bias circuit power in the defam and power in this sometimes we may specify only in the defam and gain stage so right now as I say since bias circuit was not part of my design so this value does not include power coming from the bias but in real life the power dissipation includes power in the bias circuit power in the defam circuit power in the gain stage circuit and in real open there will be a buffer stage power in the buffer stage which may be even higher so actual power dissipation is some of four arms okay and that you have to use and then the main way is you should start allocating okay how much arm I should give okay so that net is within this and then try to adjust then keep varying this suits most of that okay that's how it's apportioned so currents are apportioned each arm okay right now for us we are taking simpler issue so only two arms defam and so I don't have to apportion I will evaluate what current going through the other and therefore I will be able to tell you what is the net power dissipation which I believe should be less than 2.5 so it can be 2 volt 1.5 volt okay or it can be 1 1 milliwatt sorry not old it's fantastic but that if you do this whether you reach this or whether you reach this you verify if that still satisfies fantastic lower the power better is the design okay another varies which is so far this morning we have been talking is whether the open design has good stability and that we must verify essentially what does this means what phase margin I choose okay for relatively good stability so that is my design spec I am deciding it what fine I should use design output gain for all 12 transistors I need to know W by else and node I am using is the reason why I say that data which I will show you now is taken for this okay 0.8 microns CMOS is that okay so these are my specs this is something I believe I should know which I will fix and this something I derive at the end okay 2.5 VDD 2.5 minus 2.5 PSS is available for pointed microns 5 microns 5 volt swing okay all fine pointed analog circuits allow you for 2.5 actually higher the node higher is the voltage pointed is a almost close to 1 so it is anyway higher actually why choose 5 because there is we are not using it it is a short channel twice some effects are short channel are seen which in our calculations will not use it spice will take care of many of those parameters okay okay it is a very good question tried yourself for the sake of brevity why people at all go for minus 2.5 or minus 2 plus why dual ring why not ground and VDD so there is something advantage I get by doing this those things till I get 5 okay now come a minus case now work fish for our so Joe make the next time coming back I guess there are so joking everyone no no not just the something he said there is something to do with noise okay so I give you some noise on that okay always analog circuits unless it is single ended power supply requirement come some and our plans do you say only one otherwise you must see all open show two terminals that's the idea or general purpose will have VDD basis only specific opams which use only specific requirements they may use single ended power supply okay these are the pointed micron node spec taken from a spice file actually this was not 0.7 but I made it equal VTMS 0.7 and 0.7 minus 0.7 is VTP another thing which I have not stated but I use in the end which I now want to say the VTs are there are actually VTs are not specified as single values they will specify or rather sometimes you may have to figure out in case they are not what is VT maximum and what is VT minimum okay now maximum values can be because of variation in process temperature and also bias substrate bias if it goes through so VT varies with substrate bias VT varies with variation in process and VT varies with temperature so in real life when we design a circuit we go for the bounds so we do use max and min values of VTs and in this case it is found typically 0.1 plus minus 0.15 volts is chosen as possible variation so for example this may be 0.55 and the max may be 0.85 okay why I need these values because you have if you see the voltages ICMR say V max or V minimum or V minimum so at that time what maximum and minimum I should use out of VT which will guarantee me this mean or max values okay so otherwise the W by a size will be very different from the real life okay so I just told you in a real life this delta on this is specified if not you have to actually generate by simulating where four corners design curve figure out what maximum you will get okay but generally in course I will tell you what is the maximum okay so I have designed the features of my design karta some a charo on don't know okay don't know calm don't know hot sub maximum peak they are not bad okay so beta and dash is 110 10 to power minus 6 amps per volt square and gamma for N channels gamma is the subset bias factor which is 0.4 root volts root volt and beta P dash is 50 and 10 to power minus 6 so we are roughly expecting 2.2 ratio of mobilities and gamma P is 0.57 per root not per root volt then again this spice file if you see they say lambda n is 0.01 4 and 0.01 as lambda increase from 1 to 2 okay similarly lambda P goes from 0.05 to 0.01 link goes from 1 micron to 2 micron so each spice file will specify you you go see for model files and not necessarily in the ng spice you have but the level 9s between models will specify you what maximum it will go through okay our case we choose one of the values and probably solve something but in simulation why should it should figure it out what is it and it should solve okay so I just gave you in real life these values are chosen by a program and not by you it will actually pick up the value to find since you are not calculating so I did not give T ox etc that also I should specify C ox everything but I didn't but anyway just for me potentials are given to you for N channel and P channel we also wish to tell you that in most cases where the device is in saturation I will assume for calculation of VGS lambda is small and therefore I use VGS is VT plus VOV or VT plus under root 2 ideas by beta this is the expressions I will use accuracy probably is bit of last but if it is lower value that does not matter so if longer that is why I keep saying the longer length everything is fine shorter length all worries except something I said last time it helps you a lot okay is that okay specs you have written these are the process specs which will be specified to you okay and this is actually taken from a spice file for a pointed micron okay CMOS file so I have not added subtracted anything which they have said if they are wrong the company which is manufacturing they are wrong data I don't have for me it doesn't matter what value I get I will get instead of W by 4 I may get 16 or they wanted 16 I may get 4 for me how to get this more relevant so as of now but with these specs which are standard I am told this should be relatively correct values okay we already done this morning the equivalent circuit using Miller capacitance the GM V1 C1 R2 that's C1 C2 we already specified what are those now please remember C2 include CL or rather C2 a CL or total and we also believe that in defam M1 and M2 are identical that's our starting with defam because otherwise there will be a huge issues so M1 M2 identical so GM1 equal to GM2 both W by and thresholds are same for internal transistor forming defams then we say M9 to M12 as I just now showed constitute the biasing circuitry with register R which could be a diode for bias current control which right now as I say I am not designing which I can independently design for you but this is something which immediately I am not designing I am only desiring defam stage and game stage that W by but once I know how what I want I can go back and figure out what I should push so how we know the data we know the specs we also know that it should be stable okay so all these things which I said have been known to me I also decided the schematic that this is the circuit I want to design right now I have chosen this in real life this is not specified so you may have to even decide what circuit you should use but generally single-ended opams a single-ended output stages are used and defam are used for a normal gain stage opams 7 4 1 and all series have single-ended outputs the differential opam as they call is essentially two-ended outputs okay so right now we will not go into that okay maybe we need it where there are issues something what opam you are done in second year or third year I do not know where do you see analog lab second year isn't it there is one exam experiment we asked you to find our offset voltages so between the two inputs if I do not apply the output should be 0 but it not so you apply a difference from opposite so that we 0 goes down so one technique of offset cancellation is using a different system so that is why I say it is used many a times for offset cancellation inside chip not externally inside we will do something so that offsets are 0 no push to register the jubar sacred because I am dead tune karna kali kuch jagan iin bhartha part co-gumata bhaan kya karan is lemakush niggas please remember what you can do on the board I cannot do anything on check so you must plan everything fixed and don't think it's still probable okay so here is so let's start now so far so good if first thing my values are always for any amplifier is how much stable it will be okay and this morning I have with great fanfare said that as long as your five phase margins is 45 degree and up to 70 degree we below the FM bill or amplifier will remain stable and I have explained to this morning enough that anything lower or higher what it can create so therefore this is typical range of FM which I am going to use in design as a spec as a parameter is that clear so I can choose 45 I can use 50 I can choose 55 I can use 60 65 70 any of these values is within my control I should decide oh 60 is good enough for me that's fair enough for you if you say no I want minimum 65 you take 65 if you choose different all the other values will correspond English it because that W W by GB by P and P2 will change so everything will change doesn't matter some other W by L will appear but you must decide the margin for you so I have chosen these three values for initial calculations the final design is for 60 but I just show you how much variation the poles will get if I choose 50 if I choose 60 or if I choose 70 please take it even 75 is not out of question but as I said you it creates some other problems and therefore preferably keep to 70 from the given open circuit since it is two stage with two capacitance and there is third capacitance with today calculate that this value the C3 which is for the defam side can you before I actually you write down can you quickly tell me what will be the pole there just see no no this you write down then I will tell you what the C3 capacitance which is coming there will may give you a pole and a zero C3 is in the defam inside that is at the M3 M4 stage there is a capacitance look at this M3 M4 has EGS sitting there now so that that may create a pole and also zero because it is in a feedback so it may have a pole and a zero what is the criteria criteria is because of this the values which you are going to get if they are larger than say 100 times or 500 times again bandwidth value then I say it is damn care otherwise you will have to worry about what as what is the third pole is going to give you 99% or 99.99% the CGS values are so small that typically for example 6 megahertz you are asking gain bandwidth I evaluated probably I do not know reach there today it will be around 900 megahertz will come as your pole frequency okay so 900 megahertz for a 6 megahertz gain bandwidth far far far away okay so when by the time 900 megahertz frequency comes the gain would have gone to some 1000 dBm dB-1000 dB but kind of things so we are least worried about such poles and zeros okay. However this is not to be taken without just saying evaluate figure it out if it comes fair enough if not think of it what do I do now okay. Yeah CGS is given from technology spice file gives you all capacitance spice file gives you everything currents are decided by you so GM you get it and GM by CGS you have to evaluate okay so that the pole you have to figure it out okay I will show you value of calculation of that for a given beta given values and the way I calculated it around 930 megahertz okay which is far far away in my opinion but I will take again may not mistake for success but I hope so it is normally no one takes so obviously must be right okay we know phase margins is 180 minus tan inverse omega by P1 minus tan inverse omega by 2 and this morning we should tan plus tan inverse Z1 by W but when it goes the other side it becomes tan inverse that by W by Z1 so and we know I again I think I am making same mistake again and again this is only 5 and 5 and will become when omega is gain bandwidth value okay so fine is 180 minus tan inverse GBW by P1 minus tan inverse GBW by P2 minus tan inverse GBW by Z1 okay we also said this morning that typically we expect the 0 this morning we have plot the sigma j omega exists plots and we have seen that if 0 should be on the right half plane and as far away as possible from GBW is that clear what is the criteria we said then because by the time 0 appears the gain should have fallen much larger in negative values okay if minus 100 dB you add 20 dB it does not matter but minus 20 dB if it adds it becomes 0 dB so that may create phase issues is that clear so we already said the 0 should be quite far away from the gain bandwidth value okay how much we will check okay tentatively we can say 10 times the gain bandwidth times 10 is what the 0 could be okay but I have solved for all four cases four possible cases so 0 is at the frequency which is 10 times the GBW this ensures that 0 occurs only when due to both poles gain falls to minus 40 per decade around 100 dB minus 100 dB and then 0 appears okay that is as long as it goes to large minus this it doesn't influence so this is now what we can do what is the what we can start choosing fine okay so I how many times I have chosen three values so I will evaluate for three values this this this and I also use some four five values for that one okay so combination okay five five 15 so I did this calculation I'll show you okay so what I get from there is interesting to me everyone has written down please note down okay so is that okay this statement is okay that I am having three values of I am and I will also choose different value of Z1 and figure it out what is the value of P1 P2 let's see what is P1 P2 will come soon okay is that everyone has written down that's a case of 5 and 60 degrees so this is also 180 degrees if I not put 0s degrees put put everywhere degrees as long as I might have missed some places so 60 degree is equal to 180 minus GBW by P1 this is the expression which we are going to use okay now we see that AV0 is 4000 is that correct so what is P1 the bandwidth so what is gain bandwidth P1 into AV0 is that clear gain into bandwidth so gain bandwidth is gain is 4000 minimum plus bandwidth of P1 okay so gain bandwidth divided by P1 is AV0 is that correct so AV0 now if I take tan inverse of gain bandwidth by P1 I am essentially saying take tan inverse of AV0 is that correct and AV0 is order of 10 to power 4 so tan inverse 10 to power 4 kya hotai 90 degree it's like infinite okay so 90 degree so this term is taken care so now we say let's say now there is chosen as 10 times the gain bandwidth so if I choose that then I say tan inverse this by this is tan inverse 0.1 which is 5.7 degree by my calculator hopefully it is correct okay so I got now 120 degrees equal to 90 degree plus tan inverse gain bandwidth by P2 plus 5.7 is that correct I substituted this and I substituted this so I got this so what do I get therefore tan inverse GBW by P2 I got now everyone has written down please write down this experience this is what we are going to a 30 hours message 5.7 gap 24.3 okay so tan inverse GBW by P2 is 24.3 so GBW by P2 everyone noted down so now we are getting some feeling how many calculations you need to really still there is no where we are close to W by we are just struggling to reach there no so GBW by P2 is tan tan of 24.3 which is 0.45 okay 1 4 5 4 5 but roughly 0.45 so now there are many options one is why we chose 4000 we can choose higher but as far as tan inverse gain it does not matter because it will be 90 so it does not matter for me as far as tan inverse GBW is concerned 4000 or 5000 or 8000 does not matter but you can still have a choice now which you may use later okay so it is not necessary we are not worried now how much should be it can be anything 4000 you say limit okay it is enough for me. Now we can also say Z1 can be any other value Y10 so I have many other values I said okay why I have actually gone up to 100 times GBW so I say 5 times 10 times 20 times 50 times 100 times distance away from 0 okay so I have many values of Z1 which I can use which is in my control okay I can decide what value I should push I have 3 values of 5 so I have 50, 70 and 70 so I have 3 values of this and let us say I choose 5 Z1 so I have table of 15 so I have 5 Z1 values 3 say FIM values and then I can calculate this P2 for any one of them is that clear to you what is the technique I am following so this is essentially let us say for example if I use 0.05 sorry it is 100 this is how much 0.05 is 1 by 20 mega like this this will come 0.51 so you keep changing the Z1 value and correspondingly this term will keep changing and I will have a table to show you that so I do get design word now that we have options means you are designing you are trying to fit what you want okay is that okay everyone so I did this calculation for you since I had a calculator so I did the P2 will be 1.47 GB if I use 10 times 1.31 gain bandwidth if it is 50 1.85 if it is 5 times and 1.19 into GB if it is 100 times the gain point all that it will be 10 inverse that Z by W changes so I subtract and again then I figure out what is the tan of that and then I get these values so you can see Z can be between 100 this and this so pole can vary why I am interested in pole 2 because FIM was decided by pole 2 and from the FIM only I am now getting that value of pole which satisfies my FIM by making a choice of Z1 okay which I have 5 choices to make so from 1.85 to 1.19 times gain bandwidth it can vary if I change the 0 from 5 times to 100 times but you can see even if I change very drastically these values are not changing as much is that clear so typically 10 times 20 times should be good enough in most cases but just to get an idea that even if I go 100 times too far what values I am going to get okay so I just did the evaluation for you everyone if I do it for 50 instead of this I can get 130 now the first time will be 90 and again this can be Z1, Z2, Z3, Z4, Z5 so correspondingly I can calculate the value of P2 for this phase margin for 5 values of Z1, Z2, Z3, Z4, Z5 so I did it for 60 degree I am now I am showing you for 50 degree and finally I will do it for 70 degree so you will find that this does not very much changes very much but something else changes because something because of larger phase margin GM may be different or the CC value choose may be different and that may create further problems in some other position clear it for example so do not think that this small change means small change somewhere may be 10 times somewhere else okay so decision is how much have you any time seen a data book for any specific they say typical minimum maximum 60 degree is typical so we will do this 50, 70 can be min max okay has anyone noted down P2 GBW where it can be 0.76, 0.68, 0.84, 0.54 depends on the Z1 values I choose okay if I use this 70 degree as phase margin so 180 minus this if I subtract it 110 this will be 90 so 20 minus this and I calculated for 5 values of Z1 again and figured out the ratio of gain bandwidth to P22 as 0.2, 0.25, 0.536 okay you write down this of course these are not very relevant numbers just to show you if I am a designer you can do in simulation everything is fine but when you are not doing simulation or rather when you want to start simulation first get hold of what around what you should simulate okay otherwise too many specification too many parameters to handle it can go here I am okay so do not try the sheets okay so here is the table which I created phase margin 4 values of Z1 and correspondingly P2 values with response to this all that calculations which I showed you earlier are summarized in this table you can even write a small program and just continuous value change everything can be printed in 15 minutes and my time left there is no transcendental equation there is no second order equation there is no non-linearity simple calculations problem is that dn by dt is dj by dx time space variance continuity equation you know problem a time frame make this was space frame that process which number that I can solve current it may feel Poisson's equation rho by epsilon yadkar over a non-linear lake area then that requires numerical okay okay if that table is written down this table does not give you any great information it is only trying to tell you how things change if I change 5 or Z1 so I can actually evaluate for any 5m for any Z1 what should be the size what should be on my P2 is that clear now you may have to try few of them in real design and check but as I say I am going to do for 60 degree at 10 GB so one value I will use but I say I have access to any value of this kind and I can still third design all okay you can see roughly except this first one almost everyone is around to say it is not that it is changing drastically in great numbers so it is okay but in this it may change if you go from 50 to 70 things change but on the same phase margin it is not that great change so you can choose 10 20 is okay whatever you choose is that okay so having done this we now state the case typical value of 5 equal to 60 and Z1 of 10 times the gain bandwidth so I got from this 2 from the table now the second pole is 2.2 into gain bandwidth is that clear just now I got it so I say second pole should be 2.2 times that of gain bandwidth okay for 0 has been adjusted to 10 times the gain bandwidth and phase margin chosen is 60 degree this morning I have discussed so much about 60 okay Z1 is a pole you have to fix because today I said right hand pole we never worry but now I am saying it that control also helps okay in design as many controls you get better for you because one will change drastically so the other can be used to not allow this to change drastically so as many parameters you hold that is better control for you okay away from the GBW point from 5 times to 100 times I checked it I find 10 is normally good enough for my evaluation so I chose 10 but you may start with 20 and get away not much will happen okay so for this case what is the P2 pole we calculated from the expression GM 6 by C2 okay GM 6 by P2 and typically this value what does it say actually it does not say equal what should it show the pole should be larger than this value so that 60 degrees guaranteed for you is that correct so the minimum is equal to but anything about is also acceptable to us okay so GM 6 by C2 should be greater than 2.2 what is the gain bandwidth product GM 1 by CC okay so if you do this from this inequality I want CC should be greater than 2.2 GM 1 C2 upon GM 6 what is the effort going on for this phase margin what is the value of CC I want to know okay at least in terms of C2 if not it was given to me 10 puff if I can get the ratio of this and if I know this I know what should be the minimum value of C2 I should hold okay is that okay what I am looking for the value of CC which will give me 60 degree plus phase margin when I put 0 up 10 times the gain bandwidth so if I do this since I said Z1 is 10 times the gain bandwidth that is GM 6 by CC and that should be greater than 10 times gain bandwidth GM 1 by CC both CC please take it so GM 1 by GM 6 will less than 0.1 okay or equal to 0.1 is that okay so this is the inequality inequality GM 1 by GM 6 should be less than 0.1 or equal to 0.1 that is the possible now this value I can get this is specified for me okay so then what do I calculate I can calculate CC value is that correct because that is one spec which I did not know how much to put CC so now I have figured out I can evaluate CC if it is 5 times I get GM 1 by GM 2 should be less than 0.2 10 times it is just now I calculate it should be 0.1 times so typically for 10 times gain bandwidth as Z1 the CC should be larger than 2.2 into 0.1 into C2 put everything value here so CC should be greater than 0.22 C2 okay. Okay C2 is given to us 10 puff so CC should be 2.2 puff should be 2.5 should be 3 so I know which is the minimum CC I must use so that 60 degree phase margin is guaranteed when I put my 0 at 10 times the gain bandwidth okay so one of the features of evaluation was abitat hum main W bar ke tera bhaiye nahi hain abitah hum sir para fell nahi hain CC kya hai hain so this fact has to be understood by you that it is most important part for you is to know what is the CC values okay of design gap what is the design then you may choose value yourself 2.2 is the minimum you may choose 2.5 you may choose 3.5 then you say 5 what will happen so then you come no 2.5 is okay that is what the design specs is trying to tell before I go to the actual evaluations what is my figure of amplifier before I leave this before I start calculating W by L's please remember I have now calculated this which is what I say is requirement for amplifier to be stable now I have seen that there is a C3 capacitance sitting here which is essentially CGS related okay why CGS because CGD is shorted this is a P channel device so do not say CGD kitna CGD short kata khai that if CGS input per hai now if you want to see CGS or what we call C3 so there are 1 pole which will come because of this resistance what is this resistance 1 bar C3 okay so if I calculate the input pole for C3 it is minus GN3 by C3 and if write expression for output this I will get a 0 which is minus 2 GN3 by C3 so here is but what is the sign of 0 minus what is the sign of the pole minus so both are lying now on the left of plane so they are least worried because they may cancel now a 20 dB is a jagai you see you see it pass me yeah now say if my P3 is much larger than P1 P2 and Z3 is also much larger than P2 which I have got it in fact as I say 900 on megahertz then the use of this poles and zeros is not of any relevance in further calculation there we may have to evaluate to verify okay but just to tell you where from the verify just this substitution here I must get GN3 I must get this value of CGS whatever I get and correspondingly evaluate these 2 and figure it out where is the poles and zeros going up okay and if that happens to be too far away 1000 times we damn care about it so this is an issue which you must address though as I say if you do not address nothing goes wrong in 99 cases but as a designer I cannot accept anything without seeing it okay though my intuition says it will not affect so this is an important because we keep on talking that we are starting designing how do we create a right half plane 0 or left half plane shifted to 0 a resistance you know so next time we will when we design we will try to see somewhere instead of see it should be R and C series of that and once we get it much of this 0 on the right hand side can also be handled by us that is the next stage which we will have to do it right now I assume that without anything 5 and 60 degrees achievable with whatever values I choose but in case there is an issue further I may actually start looking that 0 also you score where we come down we see put the beth on kya I saw I can cancel kardum okay Miller cut the banana I do not want to increase CC that I knew if I increase then I have more issues so I said okay CC I kept this now I bring this polly 0 on the pole and cancel it nulling the effect so we will do that but before last slide I may like to show I just want to show you that there is another P3 Z3 available but in most cases we never bother about them but as a designer I thought we must show you that yeah there is a pole and 0 which you must evaluate and if it is extremely away we get it okay which way happen why it will happen because CJS is so low the GM by CJS is very high frequency so do not worry too much because CJS compared to all their capacitors is very low everything is safe for you okay at least it will be like that unless the size of that transistor is so big that the CJS value boosts up and then that pole may come okay so if it is 100 bended agya size kya so then you have to worry about this pole as well okay pole 0 if I continue my design at least this sheet will finish and we will stop we say C2 is given to 10 puff CC is taken to 0.22 C2 so we say CC should be greater than 2.2 puff so I can choose 2.5 puff I can choose 3 puff I can also choose 3.5 puff if I need okay I have calculated both for 2.5 because close to 2.2 so I thought okay one value should be as close to this the other is little away from it okay so that designer should actually evaluate both 3 is of course not too close but still too far but still now you look at this figure again and again that figure is very important you note down and then I will show you the figure our requirement came CC should be greater than 2.2 puff and then I have a choice to make is it okay you just write down think of this right now just forget this first only write down CC values are 2.5 or 3 puff one can choose even higher but I have chosen only 2 to evaluate okay I will come back to it 8 minute so what I see now this CC value is connected to the output of the defense stage is that correct so if this is to be charged faster okay that is new rate for this then I must see that the current which can allow this CC to get the current is only provided from this arm is that correct now the maximum current which any of the arm can get is how much when this is off this is on so the maximum current which this can provide here is only i5 ids5 is that correct to charge this this is the only current available is that correct full of it because in midpoint is half up but the maximum possible age one current which is iss or ids5 if I decide that that is CC dv0 by dt because this is v0 so if I have to charge this capacitor by this current the maximum current available to me is ids5 okay that value I use and I say I was given the slew rate of dv0 by dt is 10 volt per micro second CC dv0 by dt is ids5 ids5 is therefore equal to CC is 3 into 10 to power minus 12 3 puff into 10 into 10 to power 6 which is given dv0 by dt which is 30 micro amps or if I use 2.5 it is 25 micro amps so the first parameter I need to know about gm 1 and 2 is I must get the current in m1 and m2 is that clear so once I know ids5 what is the gm value will be what current I require half of this iss by 2 so 25 by 2 or 30 by 2 I can use to evaluate gms which I will evaluate next time and then we start then we will start getting w bios once I get gm and I proportionally start getting distance links ratios is that correct so the first parameter which gave got me closer to w bar came from there CC I chose from the phase margin slew rate gave me one value of current from where the other current value I can get power dissipation is that correct the temperature not given even that can give me another limit once I get my limits I may now say this say 12.5 the other says 15 or 20 I said fine 20 higher current I will not choose because no power will be lower than that so I may choose this current but let's say that becomes lower than this then I will choose that value and adjust this value what maximum cc I should so I will have to go back and change my cc value to come back here is that let's say that current is smaller than this value power is first so now change cc to get to that is that clear so that is the design issue it will start so it means yes because it is not open it is essentially v0 is going at the cc output so the output rises as the capacitor cc charges but that is not actually charged by this current charged by m6 or m5 okay that is the limiting this okay that that is the slew rate for the external where actually we will not use this we will actually put a another buffer stage to drive that this essentially slew rate is specified for the two-stage opamp in which output node which is my m6 m7 this how fast the cc allows current to come there okay that is essentially called slew rate for the two-stage system what you are saying opamp finally slew rate there will be third stage available which anyway is a bigger one and which is a push pull kind so it will dump huge currents or it will remove the huge currents or recharge so then that slew rate is not very important because I am actually dumping the currents heavily from the buffers okay this is very important because this is going to create my next output for the push pull stage and that I wish to know how much is that okay so these are the issues which will discuss further as of now I only look for cc charging because that is going to be output node and that only can provide through the m m2 m4 arm okay which is the maximum current is id s5 so that I charged through that