 Now, the interrupts, I have here a few slides about the interrupts, how the interrupts work. Okay, we're running usually in the main, in some main process, mainly in the main vial1 loop, in the vialmain.c. When the stm32.pyfray detects the interrupt and we configure the pyfray to create the interrupt. He sends the interrupt event to the nvig. In case that in the nvig is the interrupt enabled, nvig will notify the core. The core stops the processing of the main process and goes into the interrupt-interrupt handler. When the interrupt handler ends, and also when in the interrupt handler, we clear all the events, the microcontroller returns back into the main process. This is the purpose of the interrupt to handle the asynchronous events during the execution of the main program. Yes, for this the interrupts, we can have the multiple interrupts and we need to decide which interrupts have the priority. What is for us the interrupt with the highest priority? Then for this the nvig has the inter-inside embedded arbiter, which we solved before. When if we have one interrupt, we're doing the one interrupt, and we trigger the second interrupt, which has the higher priority or lower priority. This interrupt with the higher priority can be executed before the low priority interrupt, and then we add it to the low priority interrupt and back to the main process. This is called the preemption priority. Preemption means that the interrupt with the higher priority can stop the interrupt with the lower priority and execute himself. The sub priority is something different. In case that we have the two interrupts with the same group priority, same preemption priority, but they have different sub priority. In case that the iiq1 came first, then came the iiq2, the core doesn't matter, because the preemption priority is the same. You wait after the interrupt one execution ends, and then we start executing the interrupt 2 with the same preemption priority. But in case that these two interrupts came in the same time, then now the sub priority is take his role, and the interrupt with the lower sub priority will be executed first. In this case is the iiq1, and after iiq1 will end, we continue with the iiq2. Then the sub priority is only the case when the interrupts came in the same time. In the core, you can choose with the group priority how many bits are reserved for the preemption priority and the sub priority. This is available only on the m3 and the m4 cores. On the m0 and m0 plus, this function is not available, you have only preemption priority. But on our m3, m4 and also m7 cores, we have this possibility to select how many bits, because for disparity groups, you have only the 4 bits, then you can have parity for 0 to 16, but you can select how many bits I use for the pension parities and or the sub parities. Yes, during the enabling the interrupts in the nvc, you may be saw that there is put the strange name with the iiq type, which interrupt is it, this usually number, and this number is defined in the stm city to f4xx.h, but usually qpmx do this for you, but in case that you want to enable the interrupt in the how underscore nvc underscore set parity on your own, you need to have the name of this interrupt, and this name is defined in the stm city to f4xx.h.