 Welcome to the presentation of the STM32-G0 DMA Request Multiplexer called DMA-MUX. It covers the main features of this module. The DMA-MUX Request Multiplexer allows routing a DMA request line between the STM32-G0s peripherals and its DMA controllers. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMA-MUX synchronization inputs. The DMA-MUX may also be used as a DMA request generator from programmable events on its input trigger signals. Request chaining capability is based on an event generated on a particular output channel that is used as an input of the request generator to activate another channel. The DMA-MUX supports two interrupt request outputs. DMA-MUX registers are accessed through the AHB slave interface. The DMA-MUX is used to map the peripheral requests onto the seven available DMA channels. This mapping is programmable. Moreover, the DMA-MUX embeds a four-channel request generator that converts triggers into DMA requests. The following triggers are supported. The 16 external interrupts, low power timers 1 and 2 timeouts, timer 14 output compare and four events generated by the DMA-MUX itself. DMA-MUX events enable the user to chain DMA transfers without software intervention. Each request generator has programmable registers to select, the trigger input, trigger active edge, the number of generated DMA requests. An overrun interrupt request is asserted when a new trigger is detected, when the number of generated DMA requests caused by the previous trigger has not been completed. The DMA-MUX instantiated in the STM32G0 has the following features. 57 peripheral requests mapped to seven DMA channels. 23 request generator channels. 23 trigger inputs. 23 synchronization inputs. The DMA-MUX has two main sub-blocks, the request line multiplexer and the request line generator. The DMA-MUX request multiplexer enables routing a DMA request line between the STM32G0's peripherals and the DMA controller. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line, unconditionally or synchronously with events, from its DMA-MUX synchronization inputs. The DMA-MUX may also be used as a DMA request generator from programmable events on its input trigger signals. The DMA request line multiplexer generates both a request to the DMA controller and also events that can be used as synchronization inputs as well as trigger inputs. Do not confuse DMA request generator channels from 0 to 3 with DMA request line multiplexer channels from 1 to 7. The DMA-MUX request multiplexer enables routing a DMA request line between the peripherals and a DMA channel in unconditionally operating mode. When the multiplexer is set, it ensures the actual routing of DMA request acknowledge control signals. The connection of a peripheral request to the multiplexer channel's output is selected through the programmed request ID in the DMA-REC ID field of the channel control register named DMA-MUX-C-X-C-R. For each peripheral request line, an ID is assigned. DMA-REC ID equals 0 corresponds to no DMA request line selected. After configuring the DMA-MUX channel, the DMA controller channel to which it is routed can be configured. It is not allowed to configure two different DMA-MUX channels to select the same DMA request source. The DMA-MUX event output is generated when the DMA request counter reaches the value 0. Its operation will be explained in the next slides. Each DMA request line multiplexer can individually be set to synchronous operating mode by setting the synchronization enable bit in its corresponding multiplexer channel control register DMA-MUX-C-X-C-R. The DMA request router has multiple synchronization inputs. The synchronization inputs are connected in parallel to all multiplexer channels. When a multiplexer channel is in synchronous operating mode, the effective connection of the selected input DMA request line to the multiplexer channel's output is conditioned with events on the selected synchronization input and on a built-in DMA request counter. Upon the synchronization event, the selected DMA request line is connected to the multiplexer channel's output. From this point on, each served DMA request on the selected DMA request line decrements the DMA request counter. At its underrun, the DMA request counter is automatically loaded with the value in the NB-REC field of the controller register and the DMA request line is disconnected from the multiplexer's channel output. Thus the number of DMA requests transferred to the multiplexer's channel output following a synchronization event is the value in the NB-REC field plus 1. When the DMA MUX channel is configured in synchronous mode, its behavior is as follows. The request multiplexer input indicating a DMA request from the peripheral can become active, but it will not be forwarded on the DMA MUX request multiplexer output until the synchronization signal is received. When the sync event is received, the request multiplexer connects its input and output and all the peripheral requests will be forwarded. Each DMA request forwarded will decrement the request multiplexer counter. This counter is user-programmable. When the counter reaches zero, the connection between the DMA controller and the peripheral is cut, waiting for a new synchronization event. For each underrun of the counter, a request multiplexer line can generate an optional event to synchronize with a second DMA MUX line. The same event can be used in some low-power scenarios to switch the system back to stop mode without CPU intervention. Synchronization mode can be used to automatically synchronize data transfers with a timer, for example, or to trigger the transfers on a peripheral event. A synchronization event on edge is detected if the state following the edge remains stable for longer than two AHB clock periods. This delay ensures that glitches on the synchronization event are not taken into account. After writing to the DMA MUX CXCR control register, synchronization events are masked during three H-clock cycles. This delay masks possible synchronization events that could occur while the controller register is updated, causing metastability. The synchronization event overrun condition occurs when a new synchronization event is received, while the request multiplexer counter is different than zero. When enabled, the multiplexer channel generates an event with a pulse when its DMA request counter is automatically reloaded with the value of the corresponding NBREC field. The event generator is enabled by setting the EGE bit in the control register of the corresponding multiplexer channel. Only four channels support the generation of events, channels zero to three. When the DMA MUX channel is in event generation mode, it generates an event with a pulse when its DMA request counter is automatically reloaded. The request counter is decremented with the execution of a DMA request. The DMA MUX channel event output can be used as a synchronization event or trigger for another channel. On its output, the DMA request generator produces DMA requests following trigger events on DMA request trigger inputs. The DMA request generator has multiple four channels. DMA request trigger inputs are connected in parallel to the four channels. The outputs of DMA generator channels go to inputs of the DMA request line multiplexer. Each DMA request generator channel named generator channel further in this section has an enable bit. The DMA request trigger input for generator channel X is selected through the SIG ID field of the corresponding generator channel's control register. Trigger events on a DMA request trigger input can be rising edge, falling edge, or either edge. The active edge is selected through the PALL field of the corresponding generator channel's control register. This slide shows how the DMA request generator can be used to generate a series of DMA requests from a single DMA trigger input edge detection. Upon the trigger event, the corresponding generator channel starts generating DMA requests on its output. Each served DMA request, signaled by a request signal, de-asserted, decrements a built-in DMA request counter, internally to the DMA MUX request generator. At its underrun, the DMA request counter is automatically loaded with the value in GNB Rec field of the corresponding DMA MUX RG-XCR register, and the request generator channel stops generating DMA requests. Thus the number of DMA requests generated after the trigger event is the value in the GNB Rec field plus one. Upon the trigger event, the corresponding generator channel starts generating DMA requests on its output. Each served DMA request decrements a built-in DMA request counter. At its underrun, the DMA request counter is automatically loaded with the value in the GNB Rec field of the corresponding generator channel's control register, and the generator channel stops generating DMA requests. Thus the number of DMA requests generated after the trigger event is the value in the GNB Rec field plus one. A trigger event, signaled by an edge, is detected if the state following the edge remains stable for longer than two AHB clock periods. This delay ensures that glitches on the trigger input are not taken into account. After writing to the DMA MUX RG-XCR control register, trigger events are masked during three AH clock cycles. This delay masks possible trigger events that could occur while the control register is updated, causing metastability. If a new synchronization event occurs while the DMA request counter's value is lower than the GNB Rec field value, the synchronization event overrun flag SOFX is set in the status register DMA MUX CSR. This flag is reset by setting the associated clear bit CSO FX in the DMA MUX CFR register. Setting the synchronization overrun flag generates an interrupt if the synchronization overrun interrupt enable bit SOIE is set in the configuration register of the corresponding multiplexer channel. If a new DMA request trigger event occurs while the DMA request counter's value is lower than the GNB Rec field value, the trigger event overrun flag OFX is set in the status register DMA MUX RG-SR. The overrun flag OFX is reset by setting the associated clear bit COFX in the DMA MUX RG-CFR register. Setting the DMA request trigger overrun flag generates an interrupt if the DMA request trigger events overrun interrupt enable bit OIE is set in the control register of the corresponding generator channel. This table shows the list of the request inputs of the DMA MUX unit. Note that the actual number of request inputs is 57 plus 4. Since the requests numbered from 1 to 4 are the outputs of the 4 request generator channels. The trigger inputs and synchronization inputs are the same and have the same ID in the DMA MUX instantiated in the STM32G0. An interrupt can be generated for a synchronization event overrun in each DMA request line multiplexer channel, a trigger event overrun in each DMA request generator channel. In both cases, per channel individual interrupt enable bits are available. Please refer to the training link to this peripheral for more information. STM32G0 DMA Controller