 So, welcome to this lecture on VHDL and the course digital system design with PLDs and FPGAs. In the last lecture we have seen the concurrent statement when else and the equivalent sequential statement if then else. So, let us run through the slide before we come to the today's part today we will look at the case when sequential statement and the loops both concurrent and the sequential loop concurrent is called generate and the sequential one is called loop you know the normal for loop. So, let us run through the slide before we get to today's lecture. So, in the last lecture the first part was the when else the syntax is that you have an output signal for you know you have an expression in terms of inputs when condition some condition again in terms of input else, else means if this condition is not met another expression and some condition happens and so on. So, this shows a priority and when you come here it is not of condition 1 and condition 2. When you go to the next step it is not of condition 1, not of condition 2 and condition 3 and so on. So, it builds up at the end there is an else which captures you know the not of everything previously specified and the conditions are you know general in the sense that in the condition 1 could be a equal to b then d greater than 3 the expression itself can have the inputs some expression of inputs obviously it accommodates priority. And as I said from the description one might think it is not a kind of truth table but it is truth table in a very abstract sense and this is how the equation builds up which we have seen. And we have seen that when you write such a statement like a when p greater than q else b when r equal to 2 else c essentially are specifying a big truth table we discussed it is almost 128 rows of the truth table. So, wherever like you have a p, q, r, a, b, c as I said a, b, c is not shown a separate column but it has to be then whenever p is greater than q then you have a wherever p is less than or equal to q and r is equal to 2 then you have b else everywhere else you have c. So, that is what it this convey actually the simulator as I said whenever there is an event on a, b, c, p, q, r this is computed synthesis tool is not going to make a truth table as such it is going to infer the operator greater equal. And that kind of circuit will choose a MUX where a, b, c is let in ok we will see that later how that is kind of synthesized but the synthesis tool is going to infer operators and replace with the library codes and things like that and that is what is written here. And we have seen an example code of priority I have not written the library, entity, the architecture body and all that I suppose you can manage that you can do that because a, b, c in the port you know the a, b, c come as input as standard logic and prior come as a output which is standard logic 1 down to 0 and all that I suggest you write this and simulate in a tool if you know the tool already otherwise as we proceed I will show a demonstration of some tools by which you can try this. And we also have seen an example of a transceiver with venals, so it uses the venals construct and it also uses the, it shows the usage of in out and this array assignment and so on. And we looked at if then else which is equivalent venals, so in the simplest form it has it is like this you know you have if condition 1 then y gets a else y gets b. So the equation is that a and condition 1 or b and not of condition 1. And this if then can be used only in sequential bodies like the processors functions and procedure it cannot be used in the architecture statement region where only the concurrent statement works and the most generic form is this you can specify as many conditions you want and you end with an else which captures all the not of all the conditions that is how the truth table is completed ok. So this goes like this you know if condition 1 then y gets a else if condition 2 y gets b and so on. So the equation is the y is a and condition 1 as I said condition 1 itself is composed of some input signal when I say a and condition 1 it is symbolic definitely that as to if you write a truth table and work out the product term it expands into multiple min terms or product terms or or of product terms and so on. So that should be kept in mind so this is still not a kind of Boolean statement is little abstract. So y is a and condition 1 or b and condition 2 and not of condition 1 or c and condition 3 and not of condition 1 and not of condition 2 or d and not of condition 3 and not of condition 2 and not of condition 1 that is what is shown here. So as I said like a priority encoder picture like the AND gate with the bubbles increases the same thing happens here the structure is same here also there will be an AND gate similar to that where the multiple conditions kind of you know gets inverted or complimented and control that part. And this is equivalent to NL's but there is a major difference that you can specify multiple outputs you can implement nesting and we have seen an example where there are 3 inputs a, b, c and you have 2 outputs y and z then you could write like if condition 1 then y gets a it gets something else else if condition 2 y gets you know you can specify y and z for all these conditions. But in real life it may happen that it is not so neat you know the z may not you cannot assign z for all these conditions may be a subset of conditions only work for z and so on. So in such a case you can use the nesting you know you say if condition 1 then you can write the z straight away here that condition 1 is applicable to z. But condition like y has a restricted condition then that can be specified you know that can be split and specified in condition 2. So if condition 2 then y gets a else if y gets something else. So as far as y is concerned the equation becomes y is a and condition 2 and condition 1 and or say if it is y is equal to b you say b and not of condition 2 and condition 1. So like that it goes so you can work it out. Then we looked at something which is not fully specified suppose in VHDL if you write like this which is quite valid there is nothing kind of no error with this syntax. If condition 1 then y gets a and if that means we are not specifying the else condition then it means as far as VHDL is concerned VHDL treat this statement as like this you say if condition 1 then y gets a else y ok. Now mind you when you write the real code do not write like this ok write like this ok that is what is the standard. So if do not ever write like this always if you want a latch you write like that. And this as I said is a latch where the if this condition is not met the output is fed back you know you have the output going back as a input you know that is what it achieves this kind of code. So it is called implied memory or inferred latch implied memory because if this code implies memory through feedback or the synthesis tool will infer a latch from this code that is why it is called inferred latch. And the pictorially it is shown here at 2 to 1 marks the select line is controlled by the condition 1 so if it is select line is 1 then a goes to the output if select line is 0 then it comes back that is how the latch is implemented. You could have concurrent statement which kind of with the same effect if you miss the else part so with select you can say with enable select y gets a when 1 and you are not specifying anything else you are not specifying you know b when 0 or something like that or it means y gets a when 1 and y when 0 that is the meaning of it. And similarly you can say with enable selects y gets a when 1 you can say unaffected when others okay for in concurrent statement when you say unaffected it remembers the previous value as regard to the when else this is a statement which achieves a latch y gets a when enable is 1 and you do not specify else or if you specify else you say unaffected like the unaffected in the concurrent statement in sequential you have a null. So it again means that here you could say if condition 1 then y gets a else y get null you get the same kind of inferred latch by the synthesis tool. So implied latch is useful when we come to the maybe this end of this class or the next lecture we will handle the sequential circuit or the flip flops and registers and so on. There this is quite useful because this kind of coding is used to specify the behaviour of memory you know the behaviour of latches and flip flops and registers specifically the memory part of it. But the problem with this kind of code is that unintentional latches can happen that happens when there is a lot of nested loops and if something is missing particularly if there is not symmetric it is very difficult to work out. And as I said this can you know become an unintended kind of latch but the trouble with that is that and it is one of the most one of the common errors I see people make in VHDL but the important thing to remember is that if you make that error to debug is difficult because testing for all inputs want to expose it. Because for a particular condition if it is a latch you to expose it you have to have the previous condition previous tested condition which should have an opposite output then only that will be exposed here but if the previous condition as expected output as now then there is no way to detect this error. So this should be kept in mind and if the designer has kind of made a mistake he or so she will not be aware of it and there is no question of working out a condition that you have not aware of does not arise and this can waste a lot of time. So I suggest be very careful when you write multiple output when you do copy paste when you do nested kind of if nested case and so on you have to be careful okay not that you should not do copy paste but there is a danger okay. So let us come to the next sequential statement which is case when and this is the syntax please have a look at it. So this is identical to the with select concurrent statement only the syntax is different. So you have case some input signal is now you say when value 1 so you can write statements here okay sequential statements here when value 2 assignment when value last value assignment when others you write assignment. So these values are the mutually exclusive values of the select signal so it is exactly like you know with select and you are specifying the truth table and the statement can be is normally the output assignment it can be numerical value can be expression where the input is there okay. So it is exactly like when else but as in if then you know comparison with the when else sorry this is my mistake this is apologise this is equivalent to the with select not when else because that is where we you know there is no priority and we specify the truth table. So this is equivalent with select so like the comparison between if then else and when else the same thing applies here, here you can specify multiple output that means in the statement part you can have x get something y get something z get something and all that and you can do the nesting you can nest a case within the case that means you could say case select signal is when value 1 under that maybe you might say case some other signal is then you know you could make nesting or you could say when value 1 if some condition. So you have the freedom you mix case and if and that is one of the kind of useful structure like you have a you know the outer level case and for each value you have you know the if statements which are very useful structure we will see that when we go ahead maybe we will see an example of the case when now once again I show only the real code you could you know write all the other parts like entity, architecture, body, library and all that and the signal declaration all that should be done properly. So here I am writing two outputs you know the x and y using the case so the syntax is case select select is another input is when value 1 when the select is equal to value 1 x get a y gets b then you say when value 2 okay now I should have said when others because I need to specify all the conditions so here instead of value 2 it should be when others okay which should capture the value 2 also okay so but assume that there is a when others at the end so that everything goes well with this kind of code. So when others you can imagine there is one when others here so when value 2 x gets c y gets d. So if you look at the equation like with select you have x is a and decode of value 1 or a and decode of value 1 means you know you have so the select line is 2 bits and if it is 0 0 then it is s1 bar and s0 bar and so that is what I mean is or c and decode of value 2 now that is it. Similarly you can you know y is b and decode of value 1 or d and decode of value 2 that is what is written here. So that is how the equation or the circuit is kind of you know inferred and even in this case if you have a kind of case statement there are multiple choices okay and if you miss something in one place then can create an implied large it is not only if then everywhere whether it is congruent statement or sequential statement implied large can happen you should be careful. Once again as I said when the structure is complex then you have to be more careful okay. You could as I said nest the case when with the case when or if then it can be the case when within if or if within case when and so on. So I am showing an useful example case select is when value 1 if condition 2 then y gets a else you know you have else if which goes on. So if you look at this part only then the equation comes y is a and condition 2 or the decode of select is equal to value 1. Then you say sorry y is a and condition 2 and decode of select is value 1 or if there is a y equal to b then if it is else then y equal to b not of condition 1 and decode of select is equal to value 1 and so on it goes. So you can make out you know you can easily work out the equations and the circuit from the structure because by now you should be thorough with what I am saying. And let us see an example because you know the width select so it is identical. So let us look at this case of a 1 to 4 d multiplexer and each input and output all are 4 bits ok it could be any number of bits and since you have 4 selection 4 outputs you have 2 bits select line you know that is what is s is 2 bits y is 4 bits a, b, c, d are 4 bits. So that is a d multiplexer so let us look at the code so this is the library declaration the package and this is the entity we call it is dmax 1 to 4, 1 t4 is then it is a port the y is in standard logic vector 3 down to 0 because 4 bit for 4 outputs you have 2 select lines. So s is input again standard logic vector 1 down to 0 and a, b, c, d are output each of which is standard logic vector 3 down to 0. So that completes the entity in the architecture you give a name say some name is given of this entity then you we do not have anything to declare because very simple input output 2 inputs 4 outputs that is all. So you say begin now we are going to write the case statement for this and you know that remember the case can be used only in sequential body so we are going to write a process and within which we are going to write the case ok. Now the next question is that what should be in the sensitivity list ok. So we said that when you write when you implement something with the process you have to write necessarily the input in the sensitivity list. So because any change in the input should trigger a computation as far as the simulator is concerned so we write s and y in the sensitivity list and we have 4 outputs so when we write a case statement for each choice we have to specify all the outputs you know a, b, c, d has to be assigned for each value of you know the s, 0, 0, 0, 1, 1, 0 and 1, 1. So that is what we are going to do so that shows the process sensitivity list has 2 inputs s, y because any change in any of the simulator should you know compute and you say begin and you say case sc is the input select input is say when 0, 0, when it is 0 you know that a, y will go to a, when it is 1, y goes to b, when it is 2, y goes to c, 3, y goes to b. So that is what is written here when 0, 0, a gets y but all other thing has to be specified otherwise there will be latches. So we specify b as 0, c as 0, d is 0, when 0, 1 we assign b, y rest all is 0, when 1, 0 c gets y rest all is 0, when 1, 1 d gets y rest all is 0, when others everything is 0 really for synthesis it does not matter but for simulator if some other condition occurs by mistake then this comes up and as I said that is easy to debug. So this is the code for the demultiplexer, 1 to 4 demultiplexer using the case statement. Now the question is that here you are forced to write all the outputs in all the choices of this S value. Now the question is can we save on this because if there are too many outputs then that is going to be a problem and you know if something is missed then you can create implied latches. So is there a way out that is what we are going to see and also as I said there is no need to write when others separately you could combine with one one. So here you could write when others and you can avoid this kind of statement it does not matter. So let us see little more concise version of it. Here you see that the same process with S and Y in the sensitivity list and with say begin at the beginning before the case A, B, C, D is made 0 okay. Now in the case statement you say when 0, 0 A is Y okay and we are not specifying B, C, D because B, C, D is 0 here okay. Similarly when 0, 1 B gets Y Rust all is anyway specified 0 because when the simulator computes it goes you know that in a process statements are executed from the top to bottom once you know only once. So this works because you know if there is an event on S that means if the select line changes the simulator starts computing and initially A, B, C, D is assigned because say simulation time is 100 nanosecond, A, B, C, D is assigned kind of all 0s and suppose S is 0, 0 then A gets Y and now since it is at the same simulation time we had an assignment under plus delta A as 0 but that will be replaced by this A gets Y. So it works properly and mind you all this is we are assuming that this is for the simulator okay. This all this game of delta cycle everything is for simulator but for synthesis tool definitely it looks at this old statement. So it looks at the case statement and understand that it is a kind of what structure comes out of it and you know it is basically a demultiplexer because depending on the select line the output various different output get the same input. So that is inferred as a demultiplexer and also it has to take this initialization part of it okay. So this works perfectly fine but you should not take liberty with the synthesis many a times it is dangerous to assume something about delta cycle and write all kinds of code and expect that it will happen. This is a very kind of clear case that it works but sometime in a complex case if you assume some delta cycle initialization things can go wrong. So you have to be very careful with the coding for synthesis tool because it is a perfectly okay for simulation but for synthesis you have to keep these things in mind. So we have come to like we have completed the sequential statement major you know construct the last one we have seen was a case when identical to which select but it supports multiple output it supports nesting and if any output is missing it will create implied latch and now we have seen an example of case when with 1 to 4 demultiplexer okay. So what is remaining is the loops the concurrent statement and the sequential statement. So let us look at the loop part of the VHDL. So let us move on to the slide. So there are two loops one is concurrent which say it is like it is called generate and the sequential which is called loop itself. So the syntax will be for some indexing generate and for sequential again for something indexing like i is equal to 0 to something loop okay. And generate can work with equation it can work with component instantiation that means you can write an equation Boolean equation and you can put it in loop then you will get kind of repeated pattern of what is written of course you have to write it properly. So if you have a regular modular structure interconnected in a decent you know normal symmetric way you can use the generate to you know very concisely express that kind of structure very efficiently. Similarly you can even for component instantiation when blocks are interconnected in a symmetrical way in a regular way you could use the generate loop to come out with this structure. So let us move on let us take an example I am taking an example of a ripple adder. So you know that ripple adder is composed of full adder. So we are going to work out a kind of 8 bit ripple adder. So you have the ripple adder is made of full adder. So the full adder has two part the sum generation and the carry generation. If you remember the sum equation is A, X or B, X or C okay that is a sum equation. And carry is one when more than two or more inputs are high okay active then the carry is one. So it is nothing but A, B or BC or AC that is what is shown here. So now we take this as a module where the input is A, B and C in carry in and output are sum and carry out. Now if you write like you have a one full adder here with A0, B0 and carry 0 as input then you get some 0 as output. The output carry output is now the output out of the first stage to the input to the second stage it is called carry one. And the next stage you have A1, B1 as input the real inputs the carry from the previous stage carry 1 is input then it generates some 1 and carry 2 which is used in the next stage. And you go all the way up to the sum 7 and carry 8 sometime this is called carry out okay. So let us see how we can write and generate kind of loop for this. And you say the syntax is for i in 0 to 7 generate i is an indexing variable which is used temporarily for you know to expanding this. So for i in 0 to 7 you could even say 7 down to 0 it does not matter only thing is that indexing start from 7. So it should work normally it does not matter whether you write 0 to 7 or 7 down to 0. So you look at it so if the index is 0 then sum of 0 is nothing but A of 0, XOR, B of 0, XOR carry 0. So that is what is shown here sum 0 is A0, B0 and carry 0. And you say carry i plus 1 that mean carry 0 plus 1 carry 1 is nothing but A0 and B0, AB0, AC you know A0 and carry 0 and B0 and carry 0 that is the meaning of it. Now when we go to the next iteration when the index become 1 then you say you get the sum 1 as A1, B1, carry 1 XOR of that when you come to the carry 2 output you see it is composed of A1, B1 and the carry 1 which comes from the previous output previous stage is output. So that is how this is you know this happens. So automatically the carry 1 goes the output of the first stage goes as a input to the second stage the output of the carry output of the second stage goes as input to the second third stage and so on ok. So that is what is shown here. Now you could do this by writing component also that means that you write a full order you know the component by writing the library entity and architecture. In the architecture statement you just write one you know one full order not 8 of them like this one full order. So which say sum is nothing but AX or BX or C in and C out is nothing but AB, BC, AC like that you can write. Then you write a top level component which is composed of interconnection of all these you know you have to show the net list which we have seen. Then and that can be worked out by this kind of generate loop. So we have a full order with input carry AB output is sum and the carry out. So we write the full order port map 0 to 7 generate carry I AI BI these are input sum I and carry I plus 1 as output. So exactly same thing will happen you get A0, B0 carry 0 as input sum 0, the output and you see the carry 1 output is used in the next stage when as an input. So it works perfectly. So you could write generate loops either with the equation or with the component instantiation both works perfectly. Once again for a small example like a ripple adder you do not do a component instantiation it is enough if you write like this. You can write structural coding like this in a complex case. So just for completion sake you know clarifying I have written this component instantiation using the generate loop that is what is shown here. You could in principle have the loops conditionally that means you can here we are it is a regular structure you know the 8 full order modules are interconnected using this. But it may happen that thing is not very regular you know something happens from 0 to 5 something will happen for 6 and 7 and so on. So in such cases you could write some conditional generate you say give a label and you say if condition or some expression of the condition. Then you say generate and you write various statement you write n generate that means unless this condition is not met this will not be generated. So this can be used to like generate some kind of asymmetrical regular structure because you know where things go kind of does not fit in. So you specify that condition then that either do something else you can say if condition one then generate you know then only conditionally that will be generated. Similarly when we come to the loop for the sequential loop the syntax is like this for i in some range loop then write some statement n loop ok. So this is the kind of for loop in VHDL look at the code I have written I have written if reset is 1 then for i in 0 to 7 loop fifo i is other 0 n loop you know it continues ok maybe else is there. So many times people say the loops for loops are not synthesizable once again this is a kind of very general statement which is not true many a times this code is synthesizable you know it only say that there is a reset input when it is high all the fifos are reset ok. Now it is very simple you have flip flops within the fifo you tie together all the reset and you connect it to the reset input then it works perfectly fine. So this is synthesizable but when somebody say the loop is not synthesizable once again as in the case of variable it means that you take a algorithm which is specified using a for loop straight away translated into VHDL then if you give it to a synthesis tool you may not get you know a sensible circuit is what is the meaning when somebody say the for loops are not synthesizable many a times people say this as a kind of just as a kind of thumb rule or what they have heard from somebody else without much thinking. So you should not get kind of worried by such very sweeping general statements ok. So there is a kind of conditional loop which say that say you have a loop label then you say the syntax is while expression loop and loop that means while something is true do this loop again this is useful in generating some structures where which is not very symmetric you can say while i is greater than 2 then do something ok. So very specific ok else you know the other things can be specified before and one other the while loop usage is this one in test pages you say while not n file, n file is a kind of procedure and the argument is a vector file that means that it say whether we have reached the end of the file. So which say while not n file the vector file then do the loop ok normally you have test vectors written in a file line by line this say if the end of the file is not reached then you do loop and you do the test bench you know. So this is another useful thing for the while loop though you can use it for you know with the normal loops sequential loops this while you know conditional loop you can use that and like in C language you can have some control over the loop by exit and next you know the exit if you write somewhere you have a big loop and you write exit it means that it will just come to that point and will come out ok. A kind of blanket exit is hardly useful because you have a loop which goes from top to bottom and if you are putting exit right in the middle the remaining part is not anyway computed. So just writing exit may not be a big idea may not be useful you could say exit loop level whichever kind of here if you say exit somewhere here then you say exit tb loop so that it exit because that is useful when you have nested loops and you want to exit the whole loops you know the main loop you want to exit then you can give the proper level then it will exit otherwise if there are nested loop it could confuse whether the immediate loop or the outer loop need to be exited. Another useful thing is that you can say exit loop level when some condition is met this is may be good to kind of generate kind of irregular structures when you have a loop you say exit loop level when a particular condition happens ok and that can be rewritten in this form also like you say if condition then exit end if. So wherever you have written exit you know loop level when condition 1 you can say if condition 1 then exit end if exit loop level if you want write you can write the next is again that next is that you skip to the next index when you are looping somewhere in the middle if you say next then at that point it does not continue with the rest of the loop it just skip that index at that point and goes back to the beginning and start from the top ok. So that also is useful but a blanket unqualified next may not be of great use so you can say exit next loop level whenever there is nesting you can clearly specify which loop you are you know exiting or you can say next loop level when some condition is met again useful. So this can be rewritten or rephrased as if condition same thing when instead of when condition if condition then do the next that means then you skip it. So that shows the loop control exit and the next which can be useful but then you have to think whether it makes sense as far as the circuit is concerned if you do not think about the hardware and you keep write some blanket statement the proper circuit you may not get that should be kept in mind. So you should not with simulation it is ok with synthesis you need to be careful and if you can think of a very simple way of synthesizing the circuit then the tool might do that but if you yourself not sure what kind of circuit this will you know generate or this functionality can be brought in there is a less chance that the synthesis tool will do some magic and give you a circuit with the behavior that you have written in the VHDL using the exit or next and so on ok that should be kept in mind. So that completes the statement so the last part was the loops generate loops which can be used for equation and component instantiation and we have seen an example of a ripple order which is composed of full order and we have shown it two ways one way is using the equation and one way is using the component instantiation. Now as I said for a simple case like this component instantiation is not very attractive but definitely the equations looks better not to discourage you if you want to write component instantiation you can write. Then we have seen the loop control the exit and the next and we have seen basically the four loops the sequential loops we had this loop is synthesizable. So that is what we have seen in the last part of the lecture. So let us so like we have come as far as the combinational circuit is concerned we have kind of completed the concurrent and sequential statement. You could start writing VHDL code for various combinational circuit you know you can I suggest you try write simple things like multiplexers, demultiplexer and now when you are adders when you like say I will give some 2, 3 examples so you write in multiplexer demultiplexer then you write a adder then you write a priority encoder. So for multiplexer and demultiplexer use when else and case when for priority encoder use if then and when else and for adder use the component instantiation and the equations you use generate loop and so on. So this can be practiced so that you get practice in modeling the combinational circuit. So let us look at the sequential circuit or the flip flops and registers how this can be modeled in VHDL or coded in VHDL which will work for synthesis and simulation and so on. So let us come to take the simplest example which is the D flip flop. So first thing to note that you know that within a D flip flop there are 2 latches master slave latch and there are different ways of implementing it. One popular way of implementing is it is using 2 latches one is a master one is a slave if time permits we can have a look at that structure later. But in VHDL we are not going to write the flip flop in terms of the circuit that implements the flip flop. That means we are not going to write a structural code where you know the using the gates what is inside you know that is not on what we are going to say it in VHDL is that somehow the behavior of the edge trigger D flip flop is captured in a meaningful VHDL statement that is what how it is modeled. And if you look at the behavior of the D edge trigger D flip flop you see that there is a clock and on the active edge let us take it as a positive edge trigger because there is no bubble here. So upon the positive edge whatever is at the input is transferred to the output and it is memorized okay that is the behavior of the edge trigger D flip flop okay. So that is what is happening here when the clock edge come the 0 is transferred here and it is memorized till the next clock edge and the next clock edge it is 1 and it is memorized till the next clock edge and that is what is shown here. And here it is 0 again the 0 up till here then it is 1. So 1 comes here but then it is remembered till the next clock edge and again it is 0 so it becomes 0. So that is the behavior. So let us think how we can write this in VHDL. So we have to say first of all you see that the input goes to output only on the clock edge that means the whole process is sensitive to clock. So that say that you can write a process with clock in the sensitivity list okay. So whenever there is an event and we are talking about simulator now whenever there is an event on the clock that process gets computed okay. Now the next question is that fine if you write the clock in the sensitivity list if there is an event on the clock you know that gets computed. But then event on the clock can be the positive edge or the negative edge. So how do we specify the positive clock edge okay. So there is a trick okay what we do is that in the process we next statement after the begin we write is that if clock is equal to 1 okay. So that gives you know the clock is 1 only in the positive edge okay because there is an active edge then if clock is 1 that means it is the positive clock edge that is how it is written. And we write you know then I will show the code so this is the code which say that process clock. So whenever there is an event on the clock this process will be computed you say begin if clock is equal to 1. So this should be combined with the event on the clock even there is an event on the clock and clock is 1 it is a positive edge. Then Q gets D then if not we want it to memorise or the latch the output. So you say do not say else you say end if that means if this condition is not met you just memorise it and you say end process. So that is a perfect code for the edge to get flip flop as far as simulation is concerned okay. That is what is written here event on the clock will make the computation happen and if clock is equal to 1 will make it positive edge detect the positive edge Q gets D end if and there is no else end if so that will memorise it. And that gives you a flip flop VHDL code as far as simulator is concerned. Now the question is that we have told that the sensitivity list is a business for the simulator because it real time you know it simulates the behaviour okay. It has to simulate so it has to worry all about the event happening concurrency and things like that. But for the synthesis tool it looks at the code what is written and if you look at the code what it is written it say that if clock is equal to 1 Q gets D that means as long as clock is remaining high Q will reflect the changes in D and when the clock goes low because of this end if it will remember okay. So if given to a synthesis tool this particular code it say that as long as clock is 1 Q gets D and when the clock goes low it remembers and mind you that is nothing but a transparent latch. So for if you write such a code given to the simulator it is a flip flop given to synthesis it is a latch and the latch behaviour we know that when and that is what is written here okay. Because synthesis tool ignore the sensitivity list the above code would mean a transparent latch the event on the clock and all is not looked by the synthesis tool whenever clock is high Q gets D and on the negative edge it is remembered. So that is what is shown here as long as clock is high the Q reflects the D and at this edge whatever is the value is remembered till it is again enabled and when it is enabled the change in D is reflected and at this edge it is remembered till it is enabled so that is what is happening here. So the question is that given this code to a synthesis tool it becomes a latch and simulator treat it as a flip flop now the question is that how do we make a proper code for a flip flop as far as synthesis tool is concerned. Now this gives you a clue because here the simulator for the simulator it works properly because the simulator start when there is an event on the clock okay and this clock is equal to 1 will make a positive edge trigger. So it is enough as far as the synthesis tool is concerned this effect is captured that means that we have to say that if there is an event on the clock and clock is equal to 1 then Q gets D if you can write that then synthesis tool will treat this as a flip flop and that is what is exactly done by this code which say process clock is a begin and you write instead of clock is equal to 1 you write if CLK that is a clock tick this is called tick event and clock is equal to 1 then Q gets D if this means any event on the clock anything any change on the clock for us this is sufficient because we are checking some event and clock is equal to 1 then it is a positive edge maybe some other things can happen I will say in a moment Q gets D end if but for the simulator you know that whenever there is an event on the clock it starts computing when it comes here there is a repeat there is something redundant here this start whenever there is an event again it is a clock tick event so this is a redundant statement as far as simulator is concerned but does not matter still it is a repetition but it does not harm so that is what is so this is a code the code for flip flop which works the same for this I mean you know which works as a edge to get flip flop for simulator and synthesis tool but mind you there is one difference though suppose at the beginning of simulation the U like the output was U and somehow you know the output goes from the say the clock was flagged as U and clock started coming as 1 then there is a transit from U to 1 and this can false trigger as for simulation is concerned like when it when it simulates there is a clock tick event which is U to 1 and clock is 1 and that is true so a U to 1 transition can trigger a computation as for a simulation is concerned so there could be some false trigger when you simulate it not a very good idea actually because then the simulator behavior and the synthesis behavior will be different so at the beginning whatever hardware you really synthesize will work different from what you have simulated either you should you know know this fact and take care in the simulation or you should make somehow the simulation and synthesis you know behavior same maybe we will discuss in this in the appropriate time so I think we can we will it is a kind of the time is coming to a close so we will stop here we will continue with the VHDL modeling for the sequential circuit like flip-flops latches registers and so on with in the next class so what we have seen is that the VHDL the latches flip-flops are modeled by their behavior and we have come out with a kind of reasonable code for describing the behavior and one very important thing mind you that we have put some sensible syntax for that behavior but you know that we are human and we are reasoning that but for a tool this is just a template ok it means wherever there is a clock tick even clock is equal to 1 Q gets the end if that is treated as a latch it is not by understanding the meaning of that so this is taken as a template so you should not kind of take too much liberty with it you know so maybe there is a dumb synthesis tool which will work if you write clock tick even and clock is equal to 1 but it may not work if you write clock is equal to 1 and clock tick clock tick even ok so do not take too much liberty like we have put some sensible description for the behavior that is only the meaning. So we have looked at what works for simulation that does not work for synthesis tool then we have added some extra redundant statements so that you get a code which works for both simulator and synthesis. So with that I stop here now we have covered quite a bit please revise please look at this sequential modelling try to understand it we will build on it so please revise it I wish you all the best and thank you.