 So, hi, I will put on Spanish there, which is an alternative hardware description language for digital hardware So during this presentation, I will first give you a little introduction about Spanish there how it come how we can you how we can use it and Then I will give some different with the actual and very long and Then I will give you many little example to show you the inventory of Spanish del and how it is different What it gave you by using some abstraction and By using some software engineering approach to do hardware design So this presentation will okay this presentation will only be about synthesizable hardware. It's really not about Simulation thing You can simulate the output netlist so Yeah to simulate generated the hardware you can use Regular tools because the output netlist of Spinal is the actual and very long so you can do the simulation of tools output netlist So, yeah, this is the context. I don't have many time to to give you my opinion on that But basically what I think is the actual 2002 and very long 2005 are really bottleneck in term of engineering by many aspects and The actual 2008 and system very luck will not save all of us because of idea support because even of features that they bring That are not so good. Finally, so I don't really have many times talk about that. Sorry, but So Spanish there it is an open source project which starts in December 2014 It focus exclusively on RTL description and as you can see here there is a flow so You can describe your hardware by using some color files Then you ask it's a Spanish deal compiler to translate it into a regular visual and very luck that you can synthesize or simulate and so this made Spaniard directly compatible with all idea tools because it's regular vehicle and very dog and You can also integrate some legacy IP like a block ram for from tidings or from matter I don't know are some more complicated things Inside the Spaniard there Spaniard here keep using a blackbacking system. So it's quite compatible with existing flow and existing IPs Then about the abstraction level is it started the same level than VHDL and very long a Little bit different But the thing is then on the top of that you can build a new abstraction level You can go away from this mess of fire which is hardware design to really say what you want So yeah just before example some last points So there is no logic of a head in the granted code because by next day is not a each HLS approach It's really much more like an RTL approach as the idea in very long where you have to design gates Why you have to design registers and six like that. So there is no overhead. You will not lose performance by using it all names and all Your component hierarchy is preserved during the translation from Spain LXL to very long and VHDL so you can Simulate it by using your favorite simulator. You can look at the wave and then very easily Understand by understanding the wave catch up where is the bug in Spain LXL if you have one and Basically Spain LXL is not ready a language and this is the main point about Spain LXL Spain LXL is a language It's not is a scalar library So a scalar is a gonna help purpose programming language and Spain LXL is a library implemented on the top of it to allow you to describe being your hardware and It could seem strange to have a language into another one But it is probably one of the one of the best point of Spain LXL. So I will comment that later So yeah, this is a simple example a very random one which has no interest in practically But imagine you want to design this little piece of hardware with a single condition to drive some combinator logic Some register without reset some register with reset in VHDL and in very low because you have to use a simulation constrict to build hardware to infer the hardware because VHDL and VHDL were initially made for simulation purpose not for inferring hardware So you will have to write three different process You have a lot of redundancies because for example this condition is depicted three times Which is not very clean which is not very Safe because you can create bugs by having duplications at many place So this is how our user to do and This is how we can do with an hardware dedicated syntax and this is some Spain LXL example So first difference you can define things explicitly as signals like my register Is a register not because you are assigning it into a clocked process But because you define it directly at the definition. I want a reg of this data type I want a reg of the data type with a reset value to zero So because things are explicit now you you don't have to write process and these kind of things and You can write for example that that you want my signals to be false by default And then when the code is true, then you can assign all of those guys in the same conditional statement So Another little example This one is to compare and just to understand the abstraction level of Spain LXL right start So if you want to define a simple timer component as you can do in VXL and Verilog It's very similar like you can define. Yeah It's based on Scala. So it's much closer though to Software design in terms of syntax can define a timer class with some construction parameters This is like a generic or a parameter in Verilog Then this class with the extend component to say this class is a component So it's a yeshical element of my design then can define IO into input-outputs into a bundle bundle is the concept of hardware data structure in Spain LXL Then can define inputs and outputs of your components. It's very easy Then can define a counter into insane your timer, which is a register of this data type Then you can write conditions assign it all the conditions Reassign it so last assignment to it like last assignment to it like in VXL and Verilog then you can do assignment so If you know how to do VXL and Verilog, it's not so far. You can use it by the same way It's usually not have to care about process and things like that but then I will start with the fun stuff so imagine you want to Have a n-shake bus of color So by a n-shake bus of color I mean a stream of data which carry colors like a valid and already flag as arbitration and a payload as an LVB data structure and Okay, you have a source n-shake bus of color You want to queue it inside the 5.0 and then you want to connect it to the sink n-shake bus of color So in VXL 2002 it is really kind of boring because you have to define X signals one by one In many cases you can not really use records there because you want to have them Pametrized by Verix, so you can't really use records there in all cases Then the most boring part is probably about instantiating the component itself where you have to bend each signal one by one Which is very error-prone, which is very copy-paste work, which is a donkey work, maybe so In Spanish there things are much more object-oriented, which means So yeah, for example, if you want In Spanish there the concept of handshake bus is named stream So if you want to define a source stream and a sink stream you say I Want a source and a sink which are stream of RGB color with this parameterization So you can already much more use that as stricter which which have parameterization Which have inner parameterization you don't have you are not bound at this level and As instance to insert this FIFO you just say I want a FIFO, a stream FIFO with this data type has Element which are stored by the FIFO you don't have to bend all signals of your data structure into a single SD-logic vector anymore Then you say the depth that you want and then this is the thing if you want to access as a push port of the FIFO You say FIFO.io.push. You don't have to bend things. You directly have access to them By using this kind of object oriented way like a FIFO is an object You can say I want to access this attribute of the FIFO Then here for example, it's written that you take the source Stream then you connect it to the push port of the FIFO and here it takes a pop pot of the FIFO And you connect it to the sink so it is better than this Already, but it could be better and I will come and a better way to do it. So basically stream Is not something that come magically from spain-axial compiler It's something which is implemented on the top of it by using regular syntax of it of spain-axial So it is a class with a type parameter here Which extend bundle because this class represents a hardware data structure so it should extend bundle Then you can define element into your data structure has a valid flag and ready flag a payload instance of this parameter visible type so you can use this data structure has Slave input of your component or as master output of your component It's not like records where you have all signals that can only be in one direction It's not explained there how to do that, but it is really useful and easy to do and Then there is a thing these data structure you can add functions in functions in it like the operator that we have seen there to connect In in very long Function tasks and procedure are not that much useful because inside them you can't define what you want you have to define relationship between outputs and inputs of the function, but you can define inside them Register you can insorciate a component you can do all the tricky stuff that you want You are really limited with them But here you can really do what you want like you can define a queue function We take a parameter how many big you want the queue to be and then this function will create for example a new FIFO internally a new component so and then it will connect The stream on the one who you are calling it to the path part of this FIFO and This function will return the output part of this FIFO. So it is it is really simple But in fact there you go in place of writing all this stuff which is already better Than regular VHDL. You are just writing this like you want a source and a sync stream of RGB colors And then you'd say you take your source you want to queue it We have FIFO of 16 element and then you connect it to the sync and there you are starting to going away of the mess of wire of Hardware design you are just saying what you want and this is working You can you can write a bug like in that you can do mistake in wiring. You can do these kind of things So it's it's not only you can go further than Like imagine you want to do this hardware like you have a Source stream of color. This is our random example, but it is an example Imagine you have source Handshake source stream of color you want to draw a transaction of this stream when they are black So you need to add this arbitration gates and this check Then from this point you want to add a pipelining stage to have better maximum frequency or to have a one Depth FIFO storage. I don't know So you need to add that So in real there Probably if you have to do that you will do it by hand and it's really error problems If you do error in the arbitration, it's always a lot of time to find out where is a bug in your arbitration, but here There is how you can do it in spain agile I mean how you can do it by using the library which is implemented on the top of spain agile Like you can define a source stream of FGB color. Then you can say I take my source stream I want to draw a transaction when the source payload is black and then which this function through and we'll return this stage This this point and then you say I want to stage it and this stage function will create this hardware for you And then it will turn this this node and then you name it sync So really you are you are you are saying what you want and not how really it work Signals by signals and this is not magic here. You can do You can navigate this to the implementation of this function and this is pure RTL implementation It's not from the spain agile compiler so another example state machine so You can design sit machine as you do in vex then and very log by using switch statements and things like that But you can also use the state machine tool so sit machine tool is one time again implemented on the top of spain agile It's not something integrated in it and If you want to do to state machine So you can say I want a new state machine. I want state ABC, which are states state air is my entry point then you can define some signals inside it and then You can say state be an entry. I want to set my counter to zero State be when it is active I want to come top when my counter is for I want to go to state C and then on state B When it exits, I want to put my IO result to true So it's just an example that Spanish they'll allow you to rise your level abstraction But it's not because it's implemented in it. It's because its syntax is flexible enough to allowing you to build this abstraction state machine is not magic really is just software engineering with How do I design combined together? So another example imagine you want to do that you have A bus like an axi lights on a PB one I don't know then you want from this bus be able to drive a signal A and B which are inside of 32 bits So you want to have some register here which are right only from this bus Then you do some calculation like multiplication between both and then you want to be able to read the results from this bus so if you want to do that in the engine very long you will have to Yeah, to manage the bus timings by hand to do some switch cases So it could be a right, but it's not the only solutions So here is an example for example if you want to create an axi light for this you can write it like that And then you can use an axi light slave factory tool So this tool is one time again content of the top of spin axi It's not integrated inside it and this tool will allow you to specify your register mapping by an app by an abstract way without having any any knowledge of the boost timing then Like you can say a is Something created from the factory has a right only register of this data type mapped at this address and the same for B and Then you can do some calculation here with results and then you can say I want my factory to make the result readable at the address 8 and So this specification here is completely abstract from the fact that it is an axi light one You can replace it here by a PB one and it will work directly so and behind that there is a Lot of software entering like there is Ash map that you can use to elaborate your design and this is used behind the center there is Abstract classes there is abstract functions. There is a written see heritancy. Yeah Inheritance, exactly and yes, there is many things that you can do So a last example This is just a demonstration project that I have made fully in Spanish there just to check that it's work correctly And it's not too much buggy and so this is a kind of little SOC Which work on FPGA with an RISC 5 CPU with instruction cache, a GTAC chain to debug it Some SRM controller, one chip RAM, a PB bridge for low-performance peripherals, GPIO, timer, UART and VG This is an axi For interconnect is in a PB interconnect and there is some sample of code which are interesting inside it Like for example to implement to sample to instantiate this a PB bridge from axi light from axi 4 It's just writing that you say I want my bridge with this parameter section and this is done and to instantiate all this Decoding stuff for the a PB with all those connections between components is just saying I want an a PB3 decoder My master is the a PB bridge IO a PB and there you can give a list of save like Timer controller IO a PB is mapped at this address with this address range and you know, it's Invigil it's and in very luck is so boring to do that. So Here it is Saying what you want and you get it Then there is another pattern though. It is for the axi 4 side and this one use a data model Like you can create an axi for crossbar factory. Then you can feed it with some data model by saying I have this list of slaves I'm up there. You have this lift this list of master and They can access those slave and then you say I tell you everything. Please build yourself so you can really do software engineering to design your hardware with this approach and Yeah, this is this is all for this presentation about Spanish deal You can find everything open source and teeth repository. There is out like the commitment which start to be Good, I think there is some ready to use project to help you if you want to trade and some communication channels Or do not hesitate to To comment them if you have some issue to start up with tools or anything so This is all thank you Sorry To compare it with chasel so basically I start to work with chasel I was happy some months with it. That was two years ago and or three years ago but basically It appeared that there was a lot of issue with it and like for example clock domain support which has very Badly done and there has regularly some issue about it, but no No, but there was no move on the chasel stuff so You can also find a list of things that I don't agree with chasel in the design on the fact section of the online documentation and Yeah Maybe chasel is much more about a very large implementation of the idea Spain actually is much more about a VHD and implementation of the idea which is with check more things and most of But really it look like in surface is the same but really there is many difference behind the same like Yeah, you have to check the fact So So basically Yeah How to map some pure scala into hardware? It's your question like using hash map and things like that No So you If you can writing Software and make it able to run in hardware and software. No, it's not the case So Spanish Dell is not an actualist approach It's really an ethical approach where you use scala as an elaboration tool to design what you want by saying I want this register I want this register I want to do this operation but Spanish is not about translating and algorithmus into Hardware it's much more about saying what you want Explicitly and you get it but you can use hash map to do the elaboration of your hardware You can use all these kind of things like dynamic list and but has an elaboration tool like a for generating vex. Del or if generate in vex. Del This kind of things Yeah, so how I specify a clock for flip-flop though, but it really it's much better than vex. Del because It is implicit so you can define area of your design Which are under the effect of a given clock and reset configuration and then everything inside it all Subcomponents will automatically get it So, yeah, I had a slide but I haven't the time to talk about it So which are a message you get when it doesn't work so basically you have much more confidence when you generate the Spanish deal Netlist you have then much more confident than it's working physically in for real than a handwritten vx. Del one because Spanish deal do a lot more check by default than I think yeah, it do a lot of check directly than Like for example, it's like that you don't have comment wall loops. You will check that you don't have with mismatch these kind of things and If you have an error it will print you where in your Spanish. Del description. There is something wrong It will give you the name of the signal. So really it's made me even less easy than vex. Del to remove bugs from a Spanish their description because Yeah, I made though it check a lot of much more things and I put a lot of intention to have nice printed error message with the print stack of the execution of spain a little description And these kind of things so it's not really messy it Right have to try to give and I could get a good idea of it Put in the discussion session So there will be three process granted from it exactly like that exactly the same Oh It's better like they're all is How did this thing is in between blocking and not blocking so if they're in Spain like they're by default it is I don't know which is one, but it is like the default Well, like this one here. Yeah, you can do the other one by using another syntax, too So how the multiplication is translated into vex. Del exactly the same than in vex. Del so Then if you want to use SPGA the ticketed blocks and things like that You can associate a black box or you can try to Write it by the way that's the synthesis tool we understand it But there is no magic between in the translation so it's one to one So if you to about formal revision between the input spin ideal and Output there is no formal verification about it because basically it's not required because you are verifying the output netlist You are not doing your verification stuff on the spin ideal description. You are verifying the vex. Del generated Five so it's why I don't really care about it being formal, but I have a good confidence in the translation process