 Hello friends, welcome to you all to the 14th session of the course. I hope you are enjoying trying out with the simulator various instructions that you have learned. And let us start with a new concept though you would have heard about this in your earlier organization computer organization courses, but as far as ARM is concerned I will talk about how it is handling ARM. So, this discussion is going to be with basically on interrupts and exceptions. In this section I am not planning to cover how to write interrupt service routines. This section is only to tell you about how interrupts and exceptions are organized and what are their relative priorities and how to take the control to the interrupt service routines ok. We will stop with that and then I will come back after a few lectures on how to write the ISR ok. So, that will involve understanding about exceptions about you know having a little bit more clarity on that and then then you will be ready to really see a interrupt service routine how it is written with a real piece of code and then I will run it through to make the things better for understanding ok very good. So, these are the topics that we are going to be covering today ok. First we will see what are interrupts and exceptions and how it is handled in the ARM processor. In the I have heard both in terms you know used these words are used without having a clarity on what the difference between these two at times. So, I thought I will first clear the difference I know what is the difference between interrupts and exceptions ok. Basically both try to take away the control ok if they are some special kinds of control transfer. What I mean by control transfer? Take an example a PC is pointing at some code ok which is in the code memory and then the processor is upon fetching the instruction and executing it and if the if it encounters the branch either branch with link or branch it jumps to that location ok and then starts executing it from there. So, basically it keeps on executing what it encounters in the core memory which are some instructions which the processor keeps fetching and then start executing that happens continuously every cycle when the processor is executing. Now these interrupts and exceptions are some special kind of control transfer. That means, it takes away the PC from what it is currently doing to some other place. Where do they take away? They take them that the control ok to some other subroutines which are called ISR ok interrupt service. This is the short form of this subroutines ISR this is different from the normal subroutines that you write in your core which you access it using the branch and link label right. This label is a subroutine when the PC in the program counter encounters this instruction it jumps to that particular address and then it executes the subroutine there. What happens on after completing it? It is returning to the instruction following the branch by copying the R 14. Because branched with link would have put the address next to this instruction into the link register which is the link register it is R 14. So, this instruction automatically stores this address in the R 14 the address which is next to the branched branch instruction branch with link instruction. So, it executes this and then PC is loaded with the what you have to execute this instruction ok it is not automatically done. Please remember copying the address into R 14 is done by the processor whereas, coming back to the place where R 14 is pointing is done by the program. You can decide not to come back and ignore the value in R 14 and then keep on executing something that is left to you. But processor always shows this value the where the control is supposed to come back in R 14 ok. So, this is the normal flowwhich gets deserve using the branch with link and then the control goes here. But this is all done by the programmer this is intent of the programmer who decides how the program flow should go ok. This is what we saw in the control flow instruction in the last session. But now it is it will what we see as interconnect exceptions are also changing the flow of instruction, but some are intended and some are unintended ok. I will explain what I mean by that ok. Andsome are under the control of the programmer when it is supposed to happen is the whatever you see here the BL instruction and all that it is known to the programmer because the programmer only has written and put a BL here and then when the execution is coming here the program is aware that this is going to be executed and it is the control is going to be flowing to some other place. Whereas, when the instructions and exceptions happen it happens at a random time you know when it is supposed to happen is not known to you ok. There may be some reason behind that you know it is not arbitrary, but sometime it is because of some error or some condition it happened. So, it is that is why it is called unprogrammed. You you change the flow based on your program then it is programmed control flow changes. Whereas, this is unprogrammed because the when a reset is given to the processor it is not under the control of the programmer ok. C2U processor is here reset signal is here when the user presses the reset button and then the signal is generated it is not under the control of the programmer. So, it can happen anywhere in the program you cannot decide ok when I am executing no particular piece of code may be from location 100 to 200 I expect this interrupt you cannot say that. Nobody can predict when this interrupts on exceptions are going to happen, but there is one exception to this logic which I will tell you that is a software interrupt which is SWI that instruction. There you can generate the exception by putting an instruction SWI ok except for that everything is unprogrammed. Maybe this is called as a programmer because as a programmer you are trying to put a SWI which is software interrupt. So, through software generating an interrupt that is why it is called SWI except for this ok everything else is unprogrammed. So, let us see I hope these two are clear to you. Now, they alter who alter the interrupt and exception alter the normal program flow to handle external events or to report errors or exceptional conditions. Let us see what I mean by external events. Let me give you an example where typicalexample where interrupts are used ok. You know that ARM processor has two inputs ok to refresh your memory. I talked about this sometime back when we talked about the processor ok. So, the soft core ok the soft core of the CPU ARM has two inputs ok. This is coming from an external world one is called IRQ and is FIQ. What is IRQ? Interpreterquest. Fast Interpreter ok. Now, do not interpret fast Interpreterquest means the interrupt processor and IRQ means the interrupts come slower. A faster means that does not if this fast business does not correspond to the way the interrupts come it is a way ARM processor responds to you ok. The fast Interpreterquest means this interrupt whatever is coming from the external world needs a faster response from the processor ok. What I mean by faster response that means, let us say ok a timer is there ok ok timer. Timer is an independent hardware which is counting the clocks ok and then you have programmed the timer to interrupt the processor after counting some 100 cycles ok. It could be to so, suppose one cycle corresponds to 1 millisecond in your air time ah ok clock ok. After 100 millisecond every 100 millisecond ok we want an interrupt to be generated ok this is correspond to 100 millisecond another 100 millisecond gap. Now, why do we need that interrupt? See when the processor is busy doing its no activities no ah executing instructions it does not keep track of the time. There is a separate hardware whose job is in the world only to count the number of clock cycle. Maybe it is generated by another crystal and the fed to the timer and then it counts that and then it interrupts the processor every 100 millisecond to keep track of some timer count RTC you know real time clock maybe a 32 bit value ok is reserved for counting the time ok. So, it just incremented every 100 millisecond. So, to do this incrementing maybe we can have an ISR in the service routine and then timer is connected to FIQ. So, when this particular 100 millisecond elapses this gives a signal FIQ signal and then the processor whatever it is doing ok it stops the execution when does it stop after executing the current instruction ok. Let me tell you suppose there are pipeline fetch more decode and execute. So, it is doing some execution let us take a most case of some LDM ok. You know that lower multiple maybe it has given you know we have given all 15 registers or 16 registers to be loaded from memory. So, it is busy doing a memory transaction with the memory using the LDM instruction it is transferring data LDM is into the processor how many words 16 words. Now, the interrupt is raised on processor if it serves to interrupt in the middle of transfer then it will lose track of how many how much of data is copied from the memory. So, you watch it does it completes whatever the instruction being executed come fully ok yeah that means, if it has to fetch 16 words it has to do that and then after that is done that execution is done ok. There is some other instruction here some other instruction here, but it ignores all of that ok though it has already come into the processor it ignores all of them after this LDM is done it jumps to some known location that is what we are going to see how it is going to be done that that we will be covering in this session. So, to understand this where the interrupts come and then how the exception happens this is the way interrupts are generated you could add a you could connect a timer a hardware unit maybe you can connect a serial port you know you are I will be talking about this in the later part of this class. So, which is connected to the PC ok through a serial port. So, you have these job is to receive your data and then maybe every data it may respond it may know lies an interrupt and then the we respond back by executing the ISR. So, basically whenever any external device needs the attention of the processor it generates an interrupt and then it is connected to the IRQ or FHQ input and then processor is already you know programmed to the way it is supposed to handle that interrupt and then it will do the job and come back and execute the instruction. So, what happened IRQ on IRQ request or FHQ request it goes to ISR executes ISR and then interrupt service routing and comes back and starts executing the next instruction as if nothing has happened. So, this control flow this flow of instruction though it gets interrupted in between it continues your ISR should be written such a way that it continues without any problem ok. What I mean by that let us talk about it later, but understand the background of this ok that is about any external events it could be a timer or a serial port, but what is following in the error? It could be that when it is fetching an instruction it is encountered an error that could be a fetch error. So, instruction is being fetched, but there is there is the memory is giving an error back saying that you have reached the end of the memory ok. There is no physical memory, but you are trying to access beyond the memory limit. So, it depends on the hardware and then how memory is considered you know to which address it is mapped it all depends on those things and then the memory system may respond back saying that if there is a data abort while they accessing a data there is a problem or while accessing an instruction there is a problem. So, based on this specific input will be given to the processor and CPU processor responds back by executing the instruction. So, that is what is called exceptional conditions ok. Let us see more of this. So, what is the different between interrupt and exception? Interrupts are coming from the external word ok. It could be a reset given by the you know user or it could be generated because of some irrecoverable error this could be divided given by the you know sorry for else ok. So, they are all coming from the external word external word means it is outside the CPU ok. Outside the CPU CPU is ok we I can call it as outside CPU or it could be outside the processor if the nomenclature is to be followed processor is ARM right CPU is with all the peripherals. So, we cannot say outside the CPU because of our nomenclature that we call the ARM SOC ok system on chip ARM is in this one ok. All the peripherals are here they may generate a IRQ inside inside the IOS SOC it is of the chip you know the interrupts can come or the reset can come from real in a external to the chip ok. So, any of this event ok anyway it is outside is a ARM processor ok a signal is generated by them which is generates the interrupts whereas, exceptions are the handy conditions detected by the processor itself ok. This is the condition detected by the processor which is executing the instruction it could be a pre-patch apart while executing an instruction it found that the instruction is not there or it is an illegal instruction or the memory as given actually detected by the processor with the help of memory unit ok. So, memory unit only will income the processor saying that hey there is a problem in a way you are trying to access the memory maybe you are giving me underlying address or you are giving me address which is not valid in my memory ok. I can only give you you know I am a 1 kilobyte memory suppose and then you are going and it is mapped to some 1000 to 2000 hex ok 1 kilobyte. If you are trying to access beyond this and then you are giving an access to this memory it will give an error because there is no other memory which is mapping to that address or it could be a ARM sitting in the chip you know in your board the ARM core is trying to write into ARM of the ARM memory you know that read only memory only can you can read from the memory, but you cannot write into the memory by by by chance some error has happened and the illegal pointer is trying to write into RAM then the memory system will respond back saying that there is a data apart you are trying to write into me I am only a read only memory. So, this kind of different things could happen in the system ok. So, because of that there will be a error which is caused by the some instruction ok being executed by the processor that is why it is called processor generated because these are all generated by something which is being done by the processor itself ok. So, these are all unprogrammed ok I told you this is unprogrammed this is the whole all these are all unprogrammed data about or undefined instruction they are all unprogrammed where this is programmed. Suppose you have put an SWI instruction then this interrupt is generated as whenever the SWI is encountered. So, this is known to the programmer and if the programmer has put it internationally in the program flow. So, it goes to the SWI service duty ok we will see what is done in that let us now. So, these are the different things about interrupts and exceptions ok. Now, let us see how it is handled in the processor. Interruptor table it is a new in which you are encountering now I will tell you what it means ok. When an exception or interrupt occurs the processor sets the PC PC was to be to a specific memory address based on which exception or interrupt has occurred. The address is within a special special address range called a vector table ok. Assume there is a fixed address location the physical address location within which you know different addresses are given and based on whatever interrupt or exception has happened the particular address will be accessed by setting the PC value to that address ok. It is done by automatically by the processor ok we are not writing codes for that. The entries in the vector table are instruction that branch is specific protein ok. So, basically what happens you take an example IRQ has happened. So, let us give a you know ARM SOC here IRQ is coming from this you know some peripheral. Now, the instruction currently the processor is executing this instruction assume that it is a LDM instruction for the worst case. Now, after the execution is done see every after completing every instruction the processor is up we will check it do I have any interrupt spending for me ok. So, it encounters it sees that the signal it looks at the signal at IRQ and then sees that it is a you know it has become low. So, that means, that NIRQ is some interrupt is waiting for me. So, I am supposed to run the ISR interrupt service routine what what we need to do it is the set of actions it will do, but after that what it will do is it will go to the vector table and then to a fixed location it knows that in this location only there is a branch to the ISR ok. An instruction actual instruction is put here. So, a processor is supposed to just access this hardware instruction and start executing it then automatically the control is taken back to the ISR ok. So, that going to that location specific location is designed by the processor designer. So, that is fixed location. So, based on that it goes there. So, that is being done by the processor ok very good 1 second ok. Now, the memory map address 0 0 is reserved for the vector ok and then 4 bytes each for every instruction every interrupt. So, one instruction only can be put in 4 bytes you know that ok. When an exception are interpreted the processor sustains normal execution as I told you and starts loading the instructions from the interrupt table. Each interrupt table entry contains a form of a branch instruction to the point in the start of a specific looping system ISR interrupt service ok. Let us see how it is detected. So, these are all the addresses ok 0 0 is reserved for a reset vector ok. Whenever a reset happens the processor will come here and then access the instruction showed here which is the happen happens to be a branch instruction. Similarly, other other undefined instruction if it encounters an undefined instruction or FWI. So, these are all the different interrupts and then these are all the different addresses where it accesses the particular instruction. So, there for handling this various vector you know interrupts and exception. So, you know that there are different modes in the processor. So, this is called supervisor mode is undefined ok this is also for supervisor mode abort mode and IRQ mode and SPIQ mode. So, what is the relevance between these exceptions in the mode? Please remember the register branch discussion we had let me recall that for you you know that there is a user mode and the system mode ok. So, there are 16 registers and then you have a CPSR correct. So, these are all access the access by the system mode or user mode ok. User mode is the lowest privileged mode and system mode is a privileged mode that it can change the mode bits in the processor CPSR CPSR by modifying this you can change to different mode ok. Now, you know the register branch right FIQ there is a register branch you can go back you know some set of registers are without herein SPIQ this will become visible where it is in the FIQ mode and there is a stored program status register SPSR. Please remember that basically they are these registers are there and these registers are there and this is also there in those modes ok. Though it is available all throughout the processor, but it will be visible and you can access them only when you are in that mode. So, let me erase this ok it is too much ok. So, maybe a small one R 14 and R 13 ok if you recall I want you to go and see this different modes ok. This can be IRQ mode and there are abort ok similar thing ok and then we have supervisors ok SCC mode and undefined ok. So, these are all the different modes and different registers are available. So, so this is indicating that which mode the processor enters on receiving these instructions ok. So, automatically this is also modified for the processor and I will explain these things in detail, but this is only just a recap of the register branch. You have to remember this you know for the especially to understand the abort instructions and all that you should have this register branch in your back of your memory ok fine. When instructions arises on complete the current instruction I told you as best it can what does it what do I mean the as best as it can I will give you an example ok. I always like to have an interrupt when LDM is being executed because that is the worst case scenario and 16 registers are getting loaded from memory to processor ok sorry this is the memory only ok this is instruction. So, I am sorry 16 to CPU ok it goes to CPU. Now, what happens suppose if this accessing this instruction this data memory itself if there is an error ok. So, maybe off way through it encounter an error then it cannot complete the instruction before the data abort happens because while accessing this data only the exception has happened. So, it cannot complete you know I told you that when interrupt happens it will complete the current instruction in execution and then only government you know respond to the interrupt, but that is not always true if it is coming from external world it is nothing to do with the instruction being executed then you could afford to do the completing the instruction and then come and you know respond to the interrupt which has come from the external world. But if the exception itself is due to the instruction being executed may be a instruction fetch or instruction data abort you cannot wait for this to be completed because that itself is causing the issue. So, it will be immediately responded to ok that is what I am saying as best it can if it can complete the execution it will do otherwise it will immediately respond back on receiving initial signal ok. Suppose you are executing a LDM ok again my example LDM is being executed you have the memory from memory it is transferring some call to the CPU ok it has only transferred some 4 words ok from the memory it is supposed to access few more that means, 12 more. But the CPU is here right the research signal has come ok somebody has passed the research signal imagine it could come at any time in the cycle. So, it could happen while just 4 words have been transferred. So, when the research signal happened that is something to tell the processor that enough of what you are doing ok there is a catastrophe you have to reset the whole system now ok. That means, whether you are executing any important instruction or you may be you are executing some data of what are you are executing somethingprocessing some timer interrupt does not matter. Reset is the most highly valued or highest priority in the lab that is why it is sitting at the top ok. So, by chance it is there because of the 0, but I will show you the priority list where the reset will be at the top. So, when the reset happens the current instruction is not completed it will not wait for this current instruction to be completed it will just come out of the execution and then start accessing the instruction from this location and then do whatever is that to be done on reset ok. I will tell you what has to be done on reset I can just tell you some few things ok. So, normally the virtual addresses will contain a branch to the relevant routine ok I told you, but though FIQ loading can start immediately what I mean by that maybe you will make it it will make them become clearer in the next slide. See FIQ vector is here ok end of these are the you know possible exceptions and interrupts that can happen and these are the locations where the specific address is reserved in the memory for putting the branch instructions to the ISR ok. This will jump to FIQ or ISR this is going to IR IRQ ISR, but here if you see after only see the address you know IR addresses there is no reservation ok it could be used by anybody. So, FIQ ISR told you this is the this has to be responded to faster. So, if you put a branch instruction it will be again flushing the pipeline and then go to the ISR because it will take more time. So, you can start your ISR itself here in this location ok, I will explain you in the next slide. So, that is the that is why FIQ is kept in the end so that you can start your routine immediately. So, this is the typical memory. So, I am giving the lower address here and higher address here. So, all the lower addresses are reserved here after this FI know one one see there is no specific reservation from the processor perspective. So, you could write the FIQ interrupt ISR itself here without dumping that is what I mean bywriting it here ok. You can even have a code or data anything start or whatever you know I missed the start. So, please do not think that only code data is there and start is somewhere everything has to be within this limit ok this is 32 bit address limit. So, everything is in given in hexadecimal. So, this is the maximum address that the ARM processor can access ARM 7 TDMI and within this let me put stack also here ok you have to reserve stack space also here very good. Now, you understood. So, what is the in each of these vector branch to this branch to this branch to different handler ISR a handler or a synonyms ok you can use any of them. Now, you may wonder what is this know of sitting here in between see this is some backward compatibility this is for the earlier processor when there were 24 bit addresses where supported prior to ARM 7 TDMI there was some exception this was used for illegal address generation will be on 64 bit. So, it is no longer valid. So, you know from we are starting from 7 TDMI. So, please ignore this particular vector this is not handle now ok very good. Let us go to next topic. Now, this is a typical example how the code and data is you know please remember that stack is also here ok ok sorry about handwriting it is actually stack ok you have to believe me ok. Now, vector table is here vector table is expanded here ok this is the expanded version of what is shown here and then you could keep anywhere as a reset init code ok or SCC the supervisor code ISR and then code and stack stack can be here and FIQ ISR can start immediately ok. So, it is free you can free to locate it. Now, how you may wonder how do I decide where everything is you have to use the tools ok. The tools come coming with the ARM processor not only the compiler and assembler illocator init loader all the tools are there which will help you to mention where you want to keep any of them and then you will be mentioning some OR in your based on the assembler syntax you may define exact location of where your service pertains or data should be sitting based on that the linker will place them all and then the code will run on the processor ok. So, let us not worry about them now assume that it will they be taken care of ok good. So, this is how when an interrupt happens the control comes here to the particular based on the see you may wonder how does it know which input it is very simple. If IRQ is there on the signal and then input thing then it knows that IRQ has come if it is a input has come from FIQ it knows that FIQ is generated or if it is a fetch abort it will know that when memory is saying that there is an abort ok memory is giving back an abort and then it knows that which cycle was going whether the instruction was being fetched or data was being fetched. So, it will know that it is because of which data abort or fetch abort we fetch abort or if undefined instruction is encounter it will know. So, SWA is there then it will know that it is a software interrupt. So, it knows which has caused this interrupts or exception and based on that processor comes to the predefined address and simply purchase this instruction and then gives you to the pipeline. Then pipeline takes care of taking it back to the ISR and then start executing whatever you are writing in the code ok. I hope this is clear to you now various types of interrupts ok. Though I have explained something let me formally explain that ok. This is the research ok once is the location of the first instruction to be executed by the processor on user signal. It could be some because of on power on ok please remember when power on happened what is first executed there is a it generates a reset ok and then is a processor jumps to the reset location and then unit code is executed after that only anything happens. So, the processor branches to the initialization code please remember on reset power on also reset is generated ok or it could be generated internally by some activity based on some this is a probable error. Now, what is undefined instruction? So, undefined instruction is exception is raised when the processor cannot decode an instruction. So, let me define it here only ok assume that this is the ROM ok where code is there in the memory ok code is put in the ROM, ROM is here processor it is accessing the code leaving the address and then getting the code and then executing them. Suppose if it goes beyond this what happens? It will give a either illegal it will give a pre-patch abort ok or if suppose your memory is corrupted and then it gives an instruction which is not understandable by the processor then also an undefined instruction exception is raised ok. Software interrupt whenever it encounters the SWA instruction it a it generates the software interrupt. So, it is basically used for operating system routines. So, basically whenever you want to call some fixed routines written by the operating system and that you can plug in the code here and then SWA will be taking that control to the SWA ISR. So, basically if you want to transfer the control to a to a OS to a controlled manner then this can be used ok normally this is how it is being again used in the typical program. Now, pre-patch abort I explained you earlier ok. If suppose you are trying to access the area without you may not understand what I mean by access permission. You will understand when I have explained you MMU and memory memory protection unit MPU ok. So, till then please keep your inclusive you know the background we will cover it later. So, there are some areas in the memory which can be protected by not to be accessed by the user routine ok. Suppose you are in a user process and as a user we might make a mistake in the in writing the program and then try to access the area which is not our you know within our limit maybe it is a OS area ok OS code is here or maybe OS data is here and then through to a wrong data manipulation you are trying to access that. What happens you may correct the OS operating system. So, to prevent it the memory protection unit will be trying to see whether you have enough access permission to access this addresses it will be accessed only when supervisor mode is there. If we are running it in supervisor mode it may allow you to access it how will you go to supervisor mode you will execute a SWA. So, SWA is a controlled mechanism to access the OS code ok. So, if it is accessed using the OS code then the OS code knows how to access its data and what to do with the data OS data, but our user program may not know that and it may corrupt it unintentionally or intentionally. So, to prevent it there are some you know memory protection unit and the other hardware units are there which will continuously be monitoring what is being accessed and which mode the processor currently in is in and then whether it has a enough permissions to do the job ok whether reading or writing. So, based on that it may give a abort. So, then this when the contents of that virtual address is not available. So, this is another in the case of where you have virtual memory ok that memory is not brought into the RAM and then you your code is accessing it then it will say that this code is currently not in the memory it is in the hard disk may be or it is in the flash. So, it has to be copied into the RAM and then given access path to the processor to run the code. So, this will also be clear when I talk about physical memory and virtual memory. So, I will give you the background if you are already aware of this you can understand what it means otherwise do not bother we will anyway touch on this later. So, the actual abort is handled only when the abortor instruction is enter execute stage ok. So, what I mean by that see I told that suppose a LDM instruction or LBR instruction or SBR instruction something to do with the load or SWAT instruction ok what are the instructions can cause these are the instructions can cause a data abort. We are talking about prefetch here, but what I am saying is in the prefetch case suppose an instruction which is may be you know one of these instruction ok when you are accessing that when you would have got the abort actually when you are in the prefetch mode ok that time it is of the memory would have said that I am not able to access this instruction you are interested in, but the processor knows that there is a abort prefetch abort has happened the memory has given the error when I try to access this instruction, but it will not write the it will not execute the abort SBR or the exception handler in this case in here it is in this clock itself please remember it has happened in the prefetch case ok. Currently some instruction is getting executed here ok e this will not be affected ok it will carry on and then the decode in this what it will do the processor will make this as a invalid this instruction is invalid and then some prefetch instruction as being caused in when I was trying to access this instruction it will leave that information along with the instruction. So, through the pipeline the registers it will cause on that information ok. So, this instruction will be executed the prefetch instruction and then the the you know the instruction we after that you know will also be executed and then when this comes here then only the exception happens you may wonder why it is delayed anyway I know that it has happened here why should I delay it you think it over maybe I will ask this question and then we will clarify that why the prefetch abort has to be delayed please remember if you do not understand this I will explain again prefetch abort is what it is a happens when the prefetch this is pipeline I am drawing ok please remember this is the pipeline this is the fetch more fetch stage and decode stage and execute stage prefetch abort happens when I am trying to access an instruction ok. Let me explain you a set of instruction being executed currently the PC is executing this instruction, but when this was accessed ok the abort has happened see assume this is 100 again 104 and 108 when it was successful 108 the prefetch abort has happened. So, immediately it will not be generating an abort what I mean by generating an abort going to the abort handler accessing that particular vector table and then going and executing the ISR ok the data prefetch abort ISR it will not happen immediately here. So, it will complete this execution successfully if it can and then this will move here this will move here, but it will indicate that this is invalid do not try to execute this instruction. I encountered a problem when I try to execute you know fetch this instruction. So, please when you get a chance to execute this instruction solve this ISR prefetch abort ISR. So, when this instruction 104 comes here it will also be executed and when this 108 comes here immediately the abort will be right ok. Tink it over why it is delayed I will explain you later. Now, data abort ok data abort when is when can it happen when you are accessing a data when you will be accessing a data will it happen in the prefetch will it happen in the decode or will it happen in the execute stage. Please think it over when will the data abort happen ok. Suppose I said when you are doing a LDM instruction a data abort can happen ok, but this LDM instruction can be in three things right. Given an instruction it will come to you know prefetch stage and then it will be in decode stage for some one clock and then it will come to execute. When will the data abort happen actually can it happen here here only the instruction is getting executed actually data is not accessed. Please remember accessing a instruction is different from accessing the data. This LDM instruction itself is accessed here, but actual data transfer happens when will it be in data mode sorry decode mode it cannot be decode mode only then you know generates all the decode signals what is required for the execute stage to take care. So, actually when a LDM comes here when it gets executed that I am only it is actually going and doing what is the requested by the instruction. So, it says I am interested in accessing some registers know some memory whether I want to write into the memory or read from the memory something I am telling in this instruction. So, the processor is going to do that and doing that time the data abort can happen. So, data abort can happen only when the data access happens and data abort can access can happen only in the execute stage of which instructions. So, I mean what all the instructions can cross data abort oh very good LDR can SCR have also can generate of course, it can it can be a LDR is a read abort read from memory SCR is a write to the memory can LDM and SCM can cross the data abort of course, it can pass can you think of some other instruction apart from these four ok. If you have it in mind do you think this can cross the data abort what does it do swap swap does the exchange of data right it reads the data and then writes the data. So, there is a read memory read and there is a memory write. So, it can cross the data abort agree. So, swap can cross now I will ask you another question can the ok thumb mode you are not as aware. So, I can make a statement that these abort can happen both in ARM mode and thumb mode please remember ok that will matter which mode it is may be the bit of the data or code access the code access may be different, but it can happen in both the modes. So, these are the ways a data abort can happen ok in thumb mode there are other instructions which which is not listed here. So, I will not confuse you now, but please remember these are the instructions are there any other instructions which are access the data in the memory I do not think. So, if you remember let me know. So, these are the instructions which cross. So, that also happens only when they are in the execute stage of the in the pipeline please remember that ok. So, when the contents of the virtual address page is not available. So, again MMU related stuff. So, keep in mind it could happen because of some page missing we will come back to this. So, whenever an instruction data abort ok especially when data abort happens the abort handler does something recovers the instruction tries to execute the same instruction I did that is what I am saying restarted. Suppose LDM has caused a data abort. So, I told you that it will come in incomplete instruction it will be incomplete and then it will come to the abort handler abort handler does something and then comes back to the same location to try executing this instruction again ok. So, it is because maybe because of some memory is not available some page is not available. So, it can be recovered and then the same instruction can be tried out. So, that is what I am saying restarted the same instruction will be restarted. So, the you have to know you the abort handler has to save the proper value to come back and execute the instruction ok that is in the hands of the abort handler ok. Handler only it has to decide where it has to come back and execute the next instruction whether in a same instruction or the next one is decided by the handler based on the situation ok interrupt is used by external hardware. So, but is which instruction will be executed when you have this ok interrupt ok. Let me explain you have a processor here I told you that interrupts are coming from outside world IRQ or maybe FIQ it is executing the code. Now I told one difference between abort and accept means interrupt is whatever is being executed is completed and ISR is responded to. What I mean by ISR? It is responded to vector table is there is a vector table if it goes the IRQ or FIQ handler ok handler gets executed or ISR and then handler after handler getting executed it returns the control returns back to the instruction which is next to the previous instruction at which the interrupt happened ok. So, this is completed anyway I said that when interrupt happens the processor completes the execution. So, it is supposed to now execute the next instruction as if nothing has happened it should the control floor should have carry on with what it was doing. So, after the handler it should come back here. So, please remember to handle the interrupt after the handler is done the control comes back you know you are supposed to make the controller come back to this next instruction whereas, in the exception hand you may decide to come back to the same instruction ok. Why do you think on interrupt you have to come to the next instruction because you do not want to execute the same instruction again ok. If you do it again the behavior will be totally different what the programmer intended and what happens will be totally different. Second example suppose you have put a instruction called add R 1 comma immediate 0 2 ok this was the instruction which was being executed and interrupt happened. Now R 1 has been added with R 2. So, R 1 was having some value earlier 10 and then it has become called now it has executed this instruction and then went to interrupt. Now after the interrupt if it comes back to the same location what will happen it will get instrumented again which was not intended by the programmer. So, you should not execute the same instruction when interrupt happens you should come come to the next instruction following this those are the normal flow happens ok. So, please remember that so, that is the way interrupts are handled ok and then it can only be raised if I R 3 ok. One more thing is if you remember there was a CPSR register there was a 2 bits ok. I think if I remember 0 to 5 it is mode bits ok and then thumb mode bit e bit and this is f i cube bit and this is the IR cube bit. This is bits bit 0 bit 6 bit 7 sorry ok this is 4 and wrong this is 4 this is 5 and this is 6 and this is 7 bit 7 that means, 8 bits ok. So, if this particular bit in which one which is this CPSR ok if this bit is 1 that means, even if f i cube signal is given to the processor will ignore it I do not care about that interrupt I will continue with whatever I am doing. If it is disabled if it is enabled then the interrupt can be will be processed by the processor if the signal comes ok. So, so, you can control the whether to respond to interrupt or not by setting this bits or clearing the bits. So, that is what I am saying if you only write if I have been if you are not masked in the CPSR ok I hope it is clear to you let us go. Now, I explained you already ok what are the different modes of this different exceptions and interrupts. So, I have reset execution supervisor mode and then SWD also software interrupts are reset both execute in supervisor mode abort both pre-catch and data abort goes to abort mode f i cube is f i cube mode i r cube mode and undefined it undefined there is a separate mode. So, why I am very particular about saying these things because you should know that which bank will be visible on which interrupt. So, if you remember f i cube mode has more registers in it f i cube mode. So, that means, you do not have to save those register because new set of registers are high registers are visible in the f i cube mode. So, you can use them freely without getting worried about the user mode previously whatever was the register those registers will not be impacted when you are using this in the those modes. I will explain them clearly in the when I am handling the abort handler right now this is what it means ok very good. Now, relative priorities these are the relative priorities. So, reset is the IS priority. So, I told you that even if any instruction is getting executed it will not be completed reset will be answered immediately. So, this is more important and data abort is the next higher priority and f i cube i r cube are the you know priority way. So, what do I mean by the relative priorities a relative priority the exception is not given above multiple exceptions interrupts can happen at the same time. Please remember it is not that anybody outside the world or the instruction being executed or aware of anything happening with the other part of the things. So, i r cube is happening independent of i r cube event is happening independent of f i cube event. So, they can all happen at the same time that is a worst case scenario. So, are the abort can happen also simultaneously. So, everything can happen together ok, but some things are mutually exclusive which are mutually exclusive a free catch abort and a data abort can happen together at the same time. See remember your memory is accessed right either data is accessed at the time you agree it is a on on an architecture right or a code is accessed free fetch. So, memory when you are accessing it either you are doing a data access or a code access. So, when will the actual abort happen during the actual you know the memory unit MMU memory memory or not memory system it forms the CPU that a there is an abort. So, that abort signal is generated based on either a memory read or a write it could be for data or it could be for code, but it cannot happen together right. So, they cannot happen the event cannot be generated by the memory for both ok. So, that is what I am trying to say that, but some thing you know during this time an IRQ can come there is no there is no relationship between when IRQ is generated and when abort has happened or the processor may be executing SWI instruction and that time a FIQ can come. So, these FIQs IRQs and these abort can all happen together. So, when these things happen together how will the processor know which one to add task first because I told you that there are vector table and then the processor can do only one job at a time ok. You can access either a FIQ handler or you can go to the IRQ handler or you can go to SWI handler you cannot go to everything. So, it has to resolve at that particular moment a clock which one should I look at. So, it is actually hard wired ok the priority of relative priorities of E. So, the processor knows when there is an instant signal given there is a data of what happening and the FIQ happens and IRQ happens it will honor this ok it will ignore them all ok. Sometimes if reset is not there it is other things are happening it will not ignore them it will wait. These abort will wait and maybe the first one will be acted upon and then after it is done with that job it will come and act on this and act on this. So, there will be some sequence followed. So, that sequence is what is given by the priority given here ok that is why I what I mean by relative priority. Um or while one is being handled another one might happen if we remember when it is in FIQ handler where is it can happen nobody can prevent it or even FIQ handler itself ok FIQ handler it is doing a memory read and it creates a data abort or it is fetching the handler code and it results in a prefetch abort. So, while one hand one exception is being handled another one can be generated. So, during that time this relative priority will resolve how the processor is supposed to respond to. So, if during this FIQ data abort happens it will respond to it whereas, if prefetch abort happens it will wait for ok. It is a very mixed thing ok here those low priority if you are not able to access the code you cannot complete the handler. So, it will it will know which one to respond to. Suppose if it is IRQ handler interrupt that happened when it is being handled it will not respond to IRQ until the handler is done with that and IRQ will be enabled and then it will do. So, these things I will explain you in detail when I am handling the how to write handlers for all of them ok, but have this idea in back on the mind it will have lower priority exceptions are handled only after the high priority exceptions are handled ok. Now, I am just going to give a brief idea about how to call how the handlers are called ok from the interpreter ok interpreters are there and then you are calling the handler I told you right this is vector table and then by each location you are calling the handler. Now, how what is the instruction you are supposed to put I showed you some branch instruction, but there are different ways you can pass the control back to the handler control. So, there are number of ways an execution can be transferred to start the interrupt handler using one of the instruction in the vector table. Say how many instruction can be there only one instruction because if you recall the vector tables are all only one four bytes are reserved for each other. So, only one instruction can be there. So, you have to transfer the control to the handler in one instruction you cannot have multiple instruction then you will be writing into the adjacent neighboring vector. So, that is not correct. So, it is one instruction. So, this you are aware a branch instruction ok is it required link ok, we will not worry about this now, but you will not normally use the link register here that is a branch ok. You do not want to come back ok I will explain you why BLE is not normally used. This is a vector IRT vector suppose ok you are free to use B to the handler branch to handler or BL to handler. BL to handler means what you will say that the next instruction I I will put it in the link register right, but in this case if you are not executing a normal subroutine flow right, then you want the control to come back after the subroutine squad here it is an interrupt. So, you do not want to the next vector you know one one interrupt has happened you do not want to execute all the you know service routines of other interrupt. So, you will not put a BL you will put a B and anyway this interrupt are handled in a different way than I you knownormal branch to link ok. So, you can have a branch instruction to come to handler that is why I mentioned the branch instruction not a branch with link instruction ok. So, you can put a move instructions also. So, what I how sorry ok see how do I put a move instruction. So, I can say move PC come on some location ok. I can put a a byte address ok a byte shifted value if you recall the instruction format I mentioned you can mention a byte value ok which will be rotated by you know if suppose you have mentioned it 4 bit value and then it will be multiplied by 2 and then that many rotation ROR will be done and then that particular value will be loaded into the register right. So, there was a instruction byte shifted instruction even number of bits it will be rotated. So, that you can use if it if you can place your handler in a fixed location then that constant can be if you can generate that constant you can use that otherwise we may have to use a different instruction based on where the ISR is located. Otherwise you can do LDR LDR is with respect to PC. See it is very simple here see current PC anyway you know if you are IRQ vector you know what is the fixed location of IRQ vector. So, that PC value you know current PC value or maybe it will be because of prefetch it may be plus 4 or plus 8 ok yes it will be plus 8 anyway normally say please remember the prefetch does not know whether it is accessing the interpreter or not. Once this branch whatever you are writing here this instruction is put on it will start doing that same plus 4 plus 8 ok. So, when it is doing it you will be able to base on the PC value you can put the object and then locate it somewhere closer to the current PC. That is why I told you that ISR ISRs are written very close to the vector table ok. So, that the pressure may be any way you know you have whole bit of that. So, it is a little lower than the 32 page, but you can need the access the code ok. So, you can with respect to PC you can add an object only add is mentioned here because anyway already in this vector table is at the lower address you cannot go below this right you cannot go below. So, you have to go up only. So, you have to put the positive offset only which will be sitting somewhere in the memory higher than the vector table ok. So, you can use this instruction also to transfer the control to the handler please remember these are the instruction which can be used to transfer the control from the vector table to the handler that is what I am trying to say ok very good. Now, what all things the processor does when it is handling the exception? The current instruction instruction being executed is completed I told you that. If a current instruction is a multi cycle instruction it is completed before responding to interrupt it does not matter whether multi cycle whether LDM or LDR it does not matter or just an add does not matter that instruction will be done. Please remember when there is an exception or interrupt you do not have a control on which instruction is being executed at that time the interrupt or exception happens ok especially interrupts you do not have a clue when IRQ will be generated or FIQ will be generated you do not have any clue ok and when which instruction is executed. So, any instruction could be there at the time where the IRQ happens. So, but the processor will sincerely execute this instruction will be and then only look at the IRQ or FIQ ok and that is what I am trying to say. So, if you want to reduce the latency what I mean by latency suppose the hardware I told you the timer or a serial port is generating in interrupt it would have generated at particular time t as in that it is t is equal to 0 that is our clock starting ok, but processor will take its own time sweet time because it is currently executing this LDM instruction which is a 16 words of transfer. So, it will complete it and then when only it will realize that oh oh there is an IRQ which is coming. So, let me go to the vector table ok and then let me access this branch instruction or move whatever you have put in and then go to the ISR. So, there is a finite time in elapsed from that time that signal actual hardware signal of IRQ or FIQ has has been generated and the time at which the first instruction of the ISR is executed ok. So, it has there it has to wait for this current execution to be done then it has to put it has to do some saving of some values which I will explain you and then access this instruction it has come to the pipeline and then gets executed then only it will come to the ISR and then fetch the first instruction and then start executing it. So, lot of time is elapsed and that is the called inter latency. So, this clock cycles how many clocks it takes for responding to an interrupt means how responsive your system is going to be. It is like when I say that there is a fire alarm and I have connected the fire alarm to FIQ ok and this arm processor your embedded system is supposed to switch off the this is now remove the control to have the access to the door and then switch on the fire extinguisher. So, that fire extinguishers are activated and then switch on the alarm. So, that know there is a hoops sound. So, that the increment the people who are inside the office can escape or take action on the fire. Now that time you know how important it is to have this latency to be lower. You cannot take few seconds or even know to respond to this and then activate all these alarms and then inform the people who are in the building. So, the latency latency is very important. So, especially when there is a controller which is controlling your car engine or it is controlling your brake system it has to respond it in a few microseconds or preferably much earlier than that. So, the number of clocks decides how fast the process can respond to your external events. So, you have to take care of it when you are designing your system operating. Data about generated if LDR or SDR is encountered a problem which I explained you already ok. We will have a detailed discussion on this later on. Now one more point I want to highlight here when these different upwards are happening what happens to the IRQ and I bit. I mentioned to you in the CPSR there are two bits which are maintained which you remember bit 7 and bit 6 ok. Now I remember it. So, this is the FIQ bit and this is the IRQ bit ok. So, these bits are set that means, those particular interrupt is disabled. So, when the reset happens both interrupts are disabled ok. So, is one the reset is the IS priority and then you have to do a know recovery. So, all the above all the interrupts are disabled. So, IRQ is FIQ's are disabled whereas, if you are processing a data about though it is higher priority than cost interrupt cost interrupt is not disabled it is sorry this is not disabled it is enabled. If you are if you are in FIQ itself you are processing the FIQ then FIQ is disabled and IRQ is also disabled because in the higher priority than the FIQ. So, that is disabled if you are in IRQ if you are already servicing in IRQ the you know the subsequent IRQ is disabled ok. Similarly, if you are here ok the IBT set ok when you are into the abort. So, inside the ISR you may have to handle this and then enable them based on the priority ok. So, that I will be explaining you later, but this is how the default the processor does it and then ISR handler should they undo it after taking some action ok. It do performing some operations in the abort handler ok. So, when an exception is there is disabling of IRQ if it is done automatically by the processor on entering the exception handler ok. So, what are the four tests? The CPSR stability, SPSR mode what I mean by that see you are in a assume that you are in user mode executing our user code the IRQ happens ok then this current execution is done and then the next instruction is to be fetched, but you know it is to be executed, but it does not execute this instruction it goes to IRQ handler. So, while doing that it has got a CPSR right. So, it see when I say that when you come back after the ISR is executed to this location ok next instruction it should go as as if nothing has happened in between ok. When you are using this instruction after that this instruction, but in between the ISR has come and then you are come back from there. If the you do not want any impact of that then you have to make sure that CPSR is also not used up. Why? Because you have a in a ISR you may write a move less ok you may do a add S which will impact the CPSR flags ok or you may do some other operation which will impact the mode bits of the processor ok. Because you are going to IRQ vector that means, the user mode to IRQ mode you are going. So, the mode bits will be affected. So, condition bits flags will be affected. So, this I would know as a user I do not want this to be impacted at all because of some interrupt coming in between. So, how does the processor take care of it? It it knows that there is a stored SPSR available in that mode to which it is going it copies the CPSR into that. So, after you handle the ISR you restore it back ok you mean the handler copy the SPSR of that mode to CPSR and then pass the control to the this location. Now, you see as if nothing has happened the code is executing now the flags are same as how it was earlier. So, from the programmer perspective or from the user the program perspective there is no impact of this input happening. That will happen only when the CPSR is saved and restored back after you come back in the ISR. So, it is very important to save them ok that is what the processor does. I will explain the reason for that I hope it is clear to you. One moresimple thing you should remember is it is always the exceptions are handled in ARM state. Again you do not know the ARM or thumbs mode means ARM the exceptions are handled at 32 bit instruction ok that is all simple. It does not teach them at 15 bit always the exceptions are in ARM mode. And then it does the CPSR because you saw in the previous slide I showed that IRQ is you know disabled in all the exception to that when it disciples IRQ. It disciples FHQ if it is FHQ or insert and all the other places FHQ is not disabled because we do not want a force interrupt to be disabled because that is more critical interrupt is attached to that ok. As a system designer you are supposed to make sure that FHQ is what is you know connected to a a critical module. It could be a timer or it could be a sensor ok this ARM. So, you have to make sure that FHQ is connected to the most critical interrupt module which will indicate to the processor that please take a immediate action. So, that is why FHQ is not disabled untilyou know except for the treatment insert. And then one more thing is I told you that it will come back to the location. How will it come back until it saves it right? This PC value ok R15 is saved in the LR. See it is not actually saving this insert it is press this plus 8 because when this is executed PC would have advanced to plus 8 already ok please remember it would have alreadywant to plus 8 ok. So, this PC value is stored in the LR. LR of what? LR of that particular mode. If IRQ is the cause of the interrupt you know that there is a bank R13 and R14 of IRQ mode ok in the LR the R14 is LR register. So, of that mode ok of that mode the value who does it processor does it it shows the PC current PC value into that. So, the handler has to take remember this and then come back load the PC back into back with this value. So, that control comes back to the code which was being executed okit should adjust it such a way that it comes back. So, it will become clear to you when I am explaining about, but remember this is what done by the processor ok. These steps are very important please understand this read out and then make it you on the make sure that you understand this properly ok. So, it saves the CPSR to the exception mode. So, it saves the CPSR first will have the old mode what was there and then it changes the CPSR because current mode is controlled by the value in CPSR is removed by the current mode of the processor is controlled by the mode bit here not on the SPSR ok. SPSR is visible based on which mode you are in, but the mode bit here does not have a control on the processors status. So, processors mode status is controlled by the mode between CPSR. So, what you do is current mode you copy into the SPSR and then change it. So, that to reflect that you are in the IRQ mode or IRQ mode ok and then PC is address the exception handler. Now, I interpret a table that 0 to C one of the addresses will be loaded into the PC. So, that the control goes through that language that is all with this I think we are done with the most of the discussions. So, let us see whether you are able to understand this quiz take up 5 minutes break ok come back ok welcome back tell me what has happened what is the all expressions are handled only in arms I told you that it all is all handled in arms state why are you clear with the answer though you do not know about ARM you know that it is a 16 bit no some more is a 16 bit instructions. So, the answer is D ok the reason being please remember the vector table is only one ok vector table is only one which is at the location from this 1 0 to C 1 C or whatever. You have a you have know as a programmer or as a system developer you have to fill in some instruction here every. So, that branch instruction whatever you are putting or move instruction you are decided whether you are going to put a capital bit or 16 bit because if it has to be supporting in supported in some mode you have to put a 16 bit instruction. So, when you have only limit one only one place and then you have to put the you know branch instructions here based on which interface happening one thing you have to remember when the interrupt happens ok IRQ or exception or whatever happens you do not have any control on which instruction is being executed by the ARM processor not only that you do not have a control on which cross which instruction is executed you do not have a control on which mode it is in which whether it is in the arm state or it is in a thumb state it may be executing a thumb instruction or it may be executing an ARM instruction ARM instruction makes 32 bit by thumb means it is coming 16 bit by that is all you have to know. So, some through some means of CPSR you have you have you have changed the mode of the processor and it is in thumb mode it is executing 16 bit instruction. Now, interrupt happens you know suppose if you say that I want now every ISR handler or the record table it should be independent of ARM or thumb mode then what happens because ARM processor continues to be in thumb mode ok and then tries to access the record table it will interpret this instructions as a two 16 bit instruction is not it it will not interpret it as a one 32 bit instruction then what it will conclude from it something else not what the programmer intended. So, that that is a conclusion right what you store here you can decide to put either 32 bit instruction or a 16 bit instruction you cannot have both. If you have if you want to have both you have to change it whenever the mode changes you have to come and you you know reload it with something else which will be time consuming and it is not suitable for a a real time system or another option is these are one more table which will be a 16 bit mode table ok that is another option. But so, the processor will not I am in thumb mode. So, let me go to this record table and then access this then what happens this handler also should be in thumb mode. So, effectively you will be managing two things both handler as a record table and not sufficient right. So, and it is actually impacting the performance of the system. So, ARM the rightly decided the designer that all the exceptions interrupts everything will be handled in ARM mode irrespective of whether current mode of the processor is 32 bit or 16 bit mode on thumb mode or ARM mode. That means, it will remember because you are saving the CPSR into SPSR. So, that CPSR has a T bit there. So, you can come back after the vector after the handler is done you can come back to the previous mode that you are executing. So, the thumb instruction or ARM instruction it will not get impacted at all please remember that only thing is when it is jumping to the handler it is in the ARM mode whether it was in thumb mode or ARM mode both will execute the handler exception vector everything in ARM mode. So, that is what is the reason why it cannot be done ok. So, now you can only you already read it. So, you can read this again that means, only one vector cable can be managed and then it has to be done by one more only ok. Now, you have one more quiz take another 5 minutes it may be may need less than that, but no harm take little more time do not discuss them then come back. Welcome back I hope you might have noticed the reason correctly ok yes it is the a while see the above the vector vector table is 0 to 1 c it is not reserved for any other purpose ok this location. So, instead of putting a branch and then going somewhere I can execute the FIQ handler here itself what is the advantage I get the branch is a waste actually you know if it actually takes the control to something and then only actual job is done that in the handler. So, effectively it waste lots of pipeline because you know pipeline because of that. So, you can as well write the code here itself. So, the reason is that why the other reasons are not making sense all our exception handler need memory space where FIQ handler normally needs a few words that is not true everybody needs space in you cannot decide no the program as a develop persistent developer you may decide to put a a long routine in a FIQ you are not supposed to do a long execution there, but it all depends on the program whether you are connecting a which particular particular to a FIQ intra. So, you cannot decide on this ok only FIQ needs faster response time others do not it is not it is not true with either reset needs a much faster response to because that is the highest priority ok. But why it is not put here you are saying that reset is the highest priority, but we have put FIQ here to put the handler just after the table why because reset is a very catastrophic event once this happens you have to react to it immediately, but it is going to take its own sweet time to complete the initialization handler and all the job that you need to do. So, it is it is much more than you know this one rank instruction ok whereas, FIQ is going to be more frequently you know encountered when you have your system running in the processor. So, you want a faster response for the FIQ than a reset that is the reason why they chose that FIQ has to be in the top execution of exception handler will be slower if all the handles are placed in the respective that is not true. It is not that you if you execute from the vector table it will be slow it is the real problem is how will you say how much of space I need to allocate for IRQ, then of leaving out some space I had to put a handler for this. So, if I decide that the vector table is split into multiple thing it is like a fragmented space and you do not know how much space to reserve. So, that is why they put all the tables in one place left to the programmer to design where the ISRs are. So, so this is also not a valid reason ok very good. Let us ok this is very simple reset on reset signal can be generated either on power on ok or on recover error on receiving reset signal ok. This is what is that on receiving reset signal ok let me explain you this you you may get a reset signal from any anywhere ok you may be in any mode ok. I am taking an example where user mode you are executing your program is executing and then a reset has happened reset has having a two registers ok in the reset mode there is reset is a if you remember it is a supervisor mode right. So, it has got a SPSA as well as R 14 and R 13 is also there R 14 is there is a link register. So, this particular register is loaded with the instruction ok current instruction being or not the current instruction the PC plus 8 ok. You are executing this instruction plus 8 is what PC is the that is stored here ok immediately that is stored and then when it jumps the reset look a vector ok. And then mode bits are changed to supervisor mode and both are disabled if you remember I told you this T bit is also cleared why because all the exceptions are handled in arm mode please remember it cannot be executed in thumb mode. So, research can happen when the processor is already in a thumb mode the time T bit would have been you know clear. So, it is reset ok. So, it is not in thumb mode and then forces the PC to fetch the address 00 that is the reset location vector representation. So, after all after the reset all register except the PC and CPS are are in that PC you are loading with the value ok and CPS are mode bit you are setting ok and T bit also you are setting. So, that way it has a meaning to that very good. Now, one more quiz for you before we end the class please take think it over 5 minutes again one more 5 minutes break we will come back. Now, now this also option is A ok why see when the research signal is generated maybe as a diagnostic the purpose you want to know when the research happened in the handler maybe if it is a power on it is coming up for the first time you know it may not make sense, but if you can sense that the research has happened not because of power on, but in you know maybe you may have an external security or some mode bit to say in the system then you want to know what I was doing at the last you know just prior to the research signal chain whether it was doing some which operation. So, if it was acquired if it is acquired by the handler then this value which is stored in the SPSR and R 14 of the SCC mode can be used ok. I hope it is clear to you it is only just a diagnostic that does nothing else. So, what all research handler does? Now on entering research you do the following setup other exception vector table entry. So, first time suppose if it is power on remember the memory is having no value valid value. So, vector table has to be initialized with a branch to the ISR ISR needs to be loaded in the memory please remember RAM is not loaded when the processor comes up. So, it has to be vector table has to be initialized all the program has to be loaded in the memory ok and then the peripherals have to be set you know program to a particular value timer if it has to run it has to be program to run and then you know actual code where it is supposed to run all those things needs to be done. So, that is done by you know what then you may wonder if it is not said what will happen to the 0 who will set the value with a reset vector that is a good question. So, I will tell you what that normally in a system then this is a ARM system SOC ok. You what you normally as a system programmer do is you put the ROM or a flash ok which is a which will have the contents even when the power is lost and then when power comes. So, initially to start with may be the address the 0 x will be pointing to the ok location which is already loaded with some value which could be a ROM location ok. Later on you may use a MMU or you know some circuitry to can change this to a RAM location ok. This will you know some more knowledge on how the different memories are handled in the power system real system, but for a moment you can think that in a system a embedded system on reset the first reset vector and the code has to be loaded first it should be available in the ROM and then what will happen is this code in the ROM will inform the processor to copy it into the RAM because accessing the code from RAM and running it from the RAM is faster and then you can also write into data area you have to keep it in the RAM only. So, they are all done in a RAM. So, the initial code will be in ROM or a flash and then after that the control is taken to a RAM and then the whole thing comes up. So, that is why you know it always the first location the reset vector table will be ready. So, it will initialize the memory controllers it will initialize a MMU and cache it is there and then the reset controller has to do a stack for each processor ok. Each mode there is a R 13 I said R 13 the stack pointer each mode ok. They will all have different stack ok. I will explain about the stack later on in more detail when I am handling the abort right now you assume that the reset handler does the initialization of each of the R 13 of so, each mode each mode is having R 13 and they will be initialized to valid stack value ok. That means, it is an address allocated for the stack of the particular mode. So, all the devices have to be initialized and then copy programs from into RAM from flash or ROM I told you and then after that only you should enable interrupt because if you enable interrupt before initializing the vector table if the different happens the way it comes to vector table it does not find the you know proper branch instruction it will generate another research abort which will not have its own thing then the system will never come up. So, you have to do all this before we enable the interrupts. So, to start with it will be disabled and then it will be enabled after that in the interrupt handler ok and then user mode or it will go to user mode or a system mode as as you intend to do that ok. This is what normally done on a reset handler ok this is not if you understand this much that later on may be if it happens we will talk more about this ok. So, so we have come to an end of the class today. So, we have handled most critical modules what are vector tables how they are the ISRs are enabled and how different you know banks are used for the vector table and where are different instruction you can use to jump from vector table to the ISR or handler and then what are the functions handled by the user ok. So, with this we will you know we will I will talk to you in the next class. Have a nice day. Thanks for your attention. Bye bye.