 We will continue from wherever we left last time, the way now my actually whole plan is I will finish up with this particular part, then I will go to what we call buffer delta. So the problem is that there are no close form solutions for that, but if you want to for example even simulate that this is a complicated thing. So we will try to understand that thing now you can build up the complete simulation by actually understanding the state transition diagram of a 2 by 2 switch which is going to contain one buffer per input because so far in our switches either the buffers are only at their input or at the output. But remember in this Banyan network category there is if there is one path being setup it actually blocks many other paths who are sharing the same link those paths cannot be all permutations are not possible ok. So the only way you can get higher throughput is because it is not a strictly non-blocking switch it is a blocking switch technically. So we need to put buffers. So buffers at input and output we do understand because it is a blocking switch if there is it cannot go through just stop at the output. Now this is different than speed up factor and speed up is what the at one single output if you want to pass through something then only you require a speed up more than one. But if the permutation is such that there is no conflict cross bar will always permit this but this particular switch will not permit that actually there is a map which is possible when there is no conflict for an output port but still you cannot set up the connection because that permutation is not permitted. So people thought of putting adding into the buffer so we look into that particular thing. So that is actually from a paper again I will tell the title of the paper when I will come to that and then I will probably move to voice over IP basically SIP based system how does it operate. So that is a current day telephony structure. And if I am able to finish SIP before the end of semester then we will come back to again switch architectures and I will probably do something more on these. So which are basically knock out switch and other kind of switches which have been proposed in the literature none of them are actually implemented as such in hardware as of now except this particular one the buffer delta is technically implemented by in almost all packet switching systems. So even if it is IP switch what we do is we do not actually IP switch remember IP packets are variable length packets and whatever we have been doing is only for fixed length frames. So people used to call them ATM switches but technically in the core we always built this fixed length packet switches and if you want to implement a variable length packet switch through this at interface board you actually supplies the packets into multiple fragments put some identifier for them for reassembly then put the tag for each one of those fixed length fragments and those fragments are routed to the output board only condition is now you require an output interface board also in the switch. You are encapsulating this fixed length packet switches and outside input and output interface boards these will again reassemble back the IP packet into its original size and send it forward usually I am looking at the switching efficiency within the given amount of hardware how much I can pass through the output of the switch we call it throughput number of packets going out of the switch per unit time per unit slot ideally it should be if there are an output ports it should be n packets per output slot I should be able to push through but that really cannot happen because of the statistical nature of the traffic with buffering and something you try to improve but still getting almost one is impossible if you put a load of one means all there is always a packet available at the input in every time slot you will not get one packet per output slot coming out input output king we have seen that particular case for input king this does not happen we actually limit to a certain value you cannot exceed that well that is again a statistical because what will happen once in a while you will get very large throughput and other times you get very low but average value will be maintained at that we always compute a statistical averages. So, now let us go back to where we left I think what I had done was I had taken this case of the switches there was some switch which was having some input address and which was represented by I think this is what was there. So, that was the input address and this was to go to an output address this was B. So, that is that was our objective after the first switch we know that this particular digit will be used for in the first switch for routing purpose. So, before you do the shuffling what will actually happen is I will find out the switch number from this switch the finding out the switch number is you divide by A and take the floor function and that will give the number number is 0, 1, 2, 3 and so on. So, multiplied by total size here whatever is your current switch number because this is actually less 1 number it is if you count. So, if this will come out to be 0 there is no but it was 0 into B plus whatever is d n minus 1. So, that is what we did. So, that was term known as L 1. So, because I am dividing by A per floor function that is what we got. So, this is nothing but the floor function part plus d n minus 1 and this have to be multiplied by B that was L 1 this was just before the at this point. Now, you have shuffle network shuffle interconnect basically and this is a shuffle. So, once I did a shuffling I use the formula that what will be L 1 prime. So, I simply used L 1 into A plus L 1 this has to be if you remember for a q shuffle it has to be an R q into R is total number of elements. So, it has to be whatever is total number of elements here divide by A because I am using a shuffle. So, this A raise power n minus 1 into B. So, this will be A raise power n minus 2 into B modulo operation. So, this is what was there. In fact, what we did is we actually took this particular thing out we wrote the whole expression it turns out to be something like S n minus 1 plus then everything divided by A raise power n minus 2 B what we did is in the numerator we put the all possible maximum values and we figured out after doing all summation that that value is less than this. So, this is always going to be a fraction and when I am taking a floor function if this is a fraction and this is the integer this is what I will get actually. So, I can replace this whole thing by S n minus 1. So, you will get I think that is the point where we finished last time when I closed. So, you will end up in L 1 prime which is given by L 1 into A plus this is the only thing which will be left here. So, I think that is the point where I ended. So, we have to now solve this modulo thing. So, let us find out what is L 1 A plus S 1 we expand this as an expression we will try to understand if I do a modulo operation whatever is a component which is integral multiple of this factor will be removed and whatever is left over that will be the outcome of this modulo operation and that whatever is left over has to be less than this value. So, we will do that. So, L 1 A plus S 1 this will be now what is your L 1? L 1 you have to understand is this. So, I have to multiply this by A. So, this will become S n minus 1 A raise power n minus 1 I am I have multiplied by A already now S 2 A square plus S 1 there is already a B in front of it S 1 A right this is also fine and ultimately this S n minus 1 will be there that is a term which you will get for this you have to essentially handle this and then by using a similarity principle and following the same thing you come to the proof. So, remember there is one term which has which will go out and this is another term which will come in that is what is going to happen. So, at the input of this second stage I want to find out a switch is here what happens here that is what I am interested in actually. So, every stage what happens this is a one state transition or you call it at this stage what happens and after the next interconnect what is the number here keep on doing it, but ultimately I am interested in their total how many this is L 1 I am interested in their total n stages I am interested in L n actually. So, now solving this expand you just observe this this will be n minus 2 B now this particular factor is divisible by A is power n minus 1 B. So, if when I will do a modular when you I divide by some this thing there I will get a integer. So, when I do a modular operation this has to be removed. So, I can forget this and live with the remaining step. So, I have done the modulo I have to only now check if this is greater than A is power n minus 1 B u. So, whatever is this can probably written into some integer multiplied by A is power n minus 1 B plus some k. So, I just want to find out that k actually. So, doing that let us find out what is the maximum value of this particular thing. So, in fact is still better the way I can do is I can take this B out with that anyway does not matter now the modulo of this is what will be the answer to me. So, I am now look focusing going to focus only in this thing which is there in the inside brackets. Now, what is the maximum value which I can achieve? So, put all the maximum values of S n d n whatever it is. So, we will end up in let me do it here this side. So, maximum value of S n minus 1 S n minus 2 and so on is A minus 1 actually. So, I can put all that value. So, the maximum value of this thing will be this what will be the maximum. So, I can solve it. So, total how many terms n minus 2 terms obviously and first term is A. So, this A will cancel with this and because I have taken B out of it. So, if I multiply it by B this will be this whole thing now technically the maximum value will be A raise power n minus 1 B minus 1 conclusion for the from this actually what you get is this whole thing can never be greater than A raise power n minus 1 B. So, if I take a modulo operation I will get the same thing which is here in the argument. So, the modulo operation ultimately will give me nothing, but. That is a maximum value of d n minus 1 this goes from 0 to B minus 1 S n minus 1 also goes from 0 to A minus 1. So, I put the maximum value I am trying to find out what maximum can be achieved by this argument. So, B cancels. So, there is a A into this A raise power n minus 1 minus A A B B cancels so it is a plus A minus 1 over B. So, this actually cancels. So, final result will be of this modulo operation obviously is nothing whatever I am writing here that is what it will be that will be l 1 prime first term will not this will not exist S n minus 2. So, I can keep on doing this and I can find out l 2 and so on. So, but only now I think I have got the structure. So, now what is l 2? l 2 will be nothing, but l 1 prime divided by A into B plus d n minus 2 that is the operation at the second stage. I will find out which switch the input is going to by doing this flow function dividing by A doing the flow function or the output side how many was already covered by all earlier switches in my current switch I am going to go to this particular port number that is the second stage. So, I can write down that whole expression here and this will turn out to be S n minus 2 I have divided by A. So, again the powers will reduce that will be the flow function plus sorry there will be B also which will be l l 1 prime you divide this whole thing by A actually all terms can be divided by A this term can be divided by A this is what will be the fraction S n minus 1 divided by A will be the fraction and when you will take the flow function this will go away. So, you divide everything by A and multiplied by B and that is what actually has to come. So, I can just multiply this thing by B this can be multiplied by B and of course, this d n minus 2. So, remember that I am actually removing one time is being removed here another term getting added here that is what is happening now at every stage. So, ultimately all these terms will die away with time every stage and only these d n minus 1 terms will come and whatever is the output will tell what is the port number 2 which it is mapping. If that port number is what is being governed by d n minus 1 this power B n minus 1 plus d n minus 2 this power B into n minus 2 and so on till plus d 0. So, I am actually going to an output port address. So, it gets proved actually in that process this will be B square B square first term in brackets multiplied by B square right right it is a B square agreed this will be B square because this B has to be multiplied by that. So, from here you will get A shuffle of now number of outputs which will be shuffled are these earlier it was A is power n minus 1 into B outputs. Now, these many outputs will now be A shuffled. So, is a second shuffling interconnection this will give me nothing but L 2 prime L 2 prime is L 2 A plus L 2. Now, what will be the numerator this divide by A Q is already A R you have to find out. So, A is power and this has to be done a modulo operation over this. So, you will get L 2 prime as once you solve for this if you have to just remember the symmetry now the structure of the earlier expression this actually comes from there. So, L 2 prime is one term has actually again gone from here n minus 2 S n minus 2 has gone now is no more there plus. So, you multiply that whole term by A. So, it is a modulo operation has to be taken. So, we now know which terms will go away during modulo operations or during floor functions. So, L 2 A will give this d n minus 1 B plus d n minus 2 B into A this will come from your function this will come from your floor function the earlier it was S n minus 1 this time it has to be S n minus 2 you take the floor function of that you divide that whole thing by A raise power n minus 3 into B square. So, this term will be completely deleted rest everything you take care and you will find out that does not that is a fraction that is less than 1. So, that can be removed. So, S n minus 2 will be the only one which is left out on that side. So, from here. So, you can now just use those clues or if you want you can actually put the actual values compute the series and figure out yes it will be always less than 1 and then of course, from here once you know this L 2 prime you can find out what is L 3 L 2 prime divide by A into B plus d n minus 3 you divide this whole thing again by A which can be done all these will reduce by that value this can be divide by A this will be lost because when I am taking this floor function here n plus d n minus 3. So, what you will get you can actually directly get the clue S n minus 3 you will multiplied by B. So, it will be B cube this thing will be divided by divide by A. So, these are being wholly divided by A. So, does not matter last one will not remain there and then I multiplied by B. So, I will get this value plus d n minus 3 very similar to that this expression you can see every time I am adding now I am forming a series at every step. So, I think so far we do understand how it is happening. So, by intuition you know this is going to work, but formally if you know I you have to prove for I plus 1 and hence forth you will say because it was working for 0 it is working for 1 it is working for 2 and it works for if it works for I it works for I plus 1. So, it works for everything for all integers. So, what is it for n and get the estimate that is what has to be done. So, at l i is the line number just before the stage I. So, that l i is 1 we are doing after first stage and before a first stage. Right after stage I agreed it has to be after stage I. So, look at the similarity of whatever was the earlier expression from there it comes this is what will be there after the stage I. So, from there you can actually find out what will happen after stage shuffer interconnection and then what happens after stage I plus 1. Again following the same principle first of all you have to do the shuffling. So, shuffling again says it has to be l i whatever shuffling you are doing plus l i divide by whatever are the number of lines in that which are being shuffled this will be a raise power n minus i plus b raise power i I think that is what it will be minus 1 right I hope it is right here no. n a raise power of n minus i minus 1 sir b raise power i total sum of these two is always n. Yes. So, this is the total objects and this we divided by a. So, this will be a raise power of n. That is for R actually when I am taking in the basic this will be n minus 1 i minus 1 this I think what it should be. So, for i plus 1 I can now find out what is l i prime and from there I can get l i plus 1 because that is a step which is required for induction. So, this will give me nothing but l i prime. So, I can just multiply this thing and I will get. So, it is b raise power i plus I have to find out this operation. So, you divide this whole thing same l i by a raise power n minus i minus 1 by b i only this thing will be the whole thing which will be available rest everything will become a fraction. So, what you will get is s of n minus i now when you take a modulo operation only this a raise power n minus i into b i is complete rest everything will still remain a fraction. So, what I will get is l 1 l i plus 1 first of all l i prime only I have to solve this because l i prime will come after modulo operation. So, I have to do a modulo on this. So, once I do a modulo. So, s n minus i 1 will actually go away rest everything I have to write. So, this one will be write these things will also come as t is intact this what will be l i 1 prime. So, l i plus 1 you can again use same formula you divide by a take the floor function plus whatever is the next digit which is the d raise power n minus i minus 1 So, n minus whole bracket of i minus 1 that is what it will be. So, when you divide this whole thing by a. So, what goes out this thing is wholly divisible this thing is wholly divisible s n minus i which what comes out s n minus i divided by a will be the fraction. So, that has to be removed rest everything will be there. So, it will be s n minus i minus 1 because everything has to multiplied by b to get l i plus 1 and of course, the last one. So, I think this fits if it is for i it is for i plus 1 is proven. So, now I can go and estimate for i plus l n after nth stage sorry I am using I think small n everywhere. So, what will be l n I can just use this expression. So, when i reaches to n all these terms will actually go away this for i plus 1 remember. So, n minus i plus 1. So, when I am looking at n so s minus n minus n that will be s 0 a raise power something at that. So, how it should actually come in fact that term will not be there. No that cannot be b this is the actually from at this stage after that there is a interconnect and after that I am doing a switching operation. So, which is the digit which is used there for routing purpose that is that one n minus i. In fact, you should always write this thing this way for clarity this particular digit is used for routing there actually. So, all these terms will be actually almost gone by the time you come to n and you will end up in getting d n minus 1 b raise power n minus 1 because the i plus 1st stage it was b raise power i. So, nth stage it will be n minus 1 and so on and this is nothing but the output port address. So, shuffle interconnection actually is a delta routing network delta interconnected network. Of course, if there is a confusion you always try to find out what will happen for n minus 1 stage find out what is going to be l n minus not l n, but l n minus 1. So, from here you should be able to get there will be only one term left which will be done away within the next step and you will end up always in the routing at the destination output port address. So, that was the example that shuffle net s does work like a delta routed network, but so far you follow the principle you can always create anything interconnection is your choice how this kind of switch will be implemented. So, if it is a 2 by 2 switch it is very simple you look at the inputs which are coming in there are only 2 inputs and they will have a bit which is deciding bit actually. So, there has to be always a controller setting in. In fact, I can make a parallel interconnection also keep on sending the control bits one by one separately as a parallel line or it can be attached as a tag in front of the packet. If it is attached as a something in front of packet you require interface processor it receives the whole packet gets the tags out these tags are being sent to the controller. So, d x d y interface board has been designed to take specific bit out of the tag depending on in which stage you are putting in. This can only keep an action of whether it is in cross or bar state if it is in cross state the mapping is this bar cross is this and bar is this. So, that control has to be exerted that is it nothing else has to be done. So, if there is a conflict both of them want to go to the upper port or both of them want to go to lower port you just randomly pick one and forget about the other this is inefficient in that sense actually. So, how do you delta n cross means delta n cross if this is x and x prime connection that is a bar a cross actually means your this input is now connected to this input is connected to that is a cross state. You can actually in electronics it is pretty simple you just can build up a AND gate and put it there that is acting as a switch, but it is a non-relational switch actually because is a AND gate switching how fast AND gate can change state from 1 to 0 it basically will decide because what is happening is logically in AND gate only one input you are using as control other one is this, but this is actually changing every time it goes from 0 to 1 this transient bandwidth is decided by this gate itself gate design it is not a relational switch. We call it a non-relational switch there is no relation it is all governed by the hardware how fast you can how what is a bit rate which can be put in. There is another kind which is one example is optical coupler. So, if you use a for example, a optical coupler typically these are built over electro-optic materials and if you apply electric field. So, if you do not apply electric field this may be in bar a state when you apply electric field you change delta beta beta 1 and beta 2 are basically difference of propagation constant of two modes two Eigen modes in this coupled system is actually are like this one is this one is this. So, one is with beta 1 other one is beta 2 and the difference between them is known as delta beta that is known as delta beta coupler actually this delta beta can be changed by applying electric field. So, usually when you put profile here this will excite this is not the mode of the system these are the only two modes. So, this has to be now represented by uniquely by a linear combination of these two modes. If these are both of equal strength and you add them you just make a 180 degree phase shift for this one. So, these and these will become in phase component in the correctly what is there out of phase this is going to be there if you make it 180 degree phase shift these two will be canceling each other and these two will be adding. So, these two modes will be excited with equal strength actually and as you propagate and if you ensure this length is sufficient and I am so that you will have a pi phase shift what will find out these two will come in phase and these two will go out of phase at the output. So, whatever power you are inserting here will come out at this port that is a cross state. If you change your voltage your delta beta into length it becomes 2 pi or integral multiple of 2 pi power will remain in the same fiber, but one of the important thing when I am going to cross to bar state that will take say a few milliseconds, but this time taken to go from cross to bar state does not decide what will be the bit rate which can be injected into the system because this is not changing the state of system. So, this is transparent to input to output this is a relational system in case of gate this is not a relational system input and output are not at all related bit rates the system actually tells what is the maximum bit rate which can be there. So, that is also another one kind of configuration which can be there, but scheme usually will be very similar to this and if you have a kind of not a two because in this case logic is very simple if both are same choose one of them randomly other one you simply drop, but where you will drop what does that drop means. So, if it is a gate based implementation only one path because what will happen is you will have going from here you will have a gate going from here also you will have a gate with or option here similarly from here there is going to be one gate something like this if you put a not then there is a problem actually because both of them cannot be switched off simultaneously. Sometimes both of them might have to be switched off if there is a contention because you are dropping that packet. So, that packet will be lost. So, it has to be received analyze and then retransmit it again by this interface board you have to repeat it multiple times in the switch it is not that you it is not like a cross bar where only interface board does the analysis then internal just set the cross points things passes through know you require basically all clock recovery putting into memory analyzing everything at this point and every 2 by 2 cross point requires this. So, amount of hardware required is higher actually compared to a simple cross bar that is a penalty which you pay for tech switching. So, every 2 by 2 cross point require a processor however small it is, but it requires a processor cross bar one processor is good enough and every interface board there is to be a processor. So, technically a number of interface boards which you require are one is the main interface board in the beginning where the tags are inserted and if it is a IP packet variable length switching it also does a splicing into constant fixed length frames output side it will be spliced back joined together at the splitted stuff to join make the again variable length IP packet these are 2 special kind of interface board then every stage will require interface boards at the input side that is a complication here and this is I think is a problem, but with the good now in VLSI it is technically possible to implement all these details. So, this has actually taken off as such now can we improve this further we are implementing 2 by 2 by gates using VLSI that is now this however the whole matrix itself is built in VLSI now, but that will not have a processor built in VLSI. You can build the processor also just repeat the same thing same design multiple times now we can connect them with the buses now we are done away with crossbar now that it is implemented in packet switches are all implemented this way no crossbars crossbars actually are no more used in fact for even speech signaling we do not require crossbars anymore because speech is now communicated over a packet switching system. So, underlying switches still remains this transparent to your voice transport system earlier voice transport system was knowing that there is a switch beneath you are setting up paths now for you setting up path actually means a bus simply putting a forming a packet and putting something in the header that is the switching functionality as far as the voice transport is concerned. So, hardware takes care of that now how to improve the functionality I have to introduce buffering ok. So, buffering means if this is there I am going to have one buffer now if there are two packets coming two packets coming to the system then what will happen there is a contention one of them can go out directly other one can be buffered actually now here slightly a different thing because I am now introducing for the first time the feedback system ok. So, there is a feedback loop which is there. So, there is nothing actually gets lost you only transfer the packet to next stage if you have got a buffer available otherwise you do not do this actually is as simple as that. So, do we put an output buffer or an input buffer the question is this if I want to build up a buffer I am going to still build the same delta network, but now every intermediate switch will have a buffer. Now if I make this as an output buffer I am connecting to some other switch now look at a situation when the buffer is not here, but buffer is here and they are on the same chip or a same substrate or same board. So, distances are very small they I can build a backward communication also. So, whether you put the buffers here or whether you put the buffers here actually same it does not matter now question is how to analyze the performance. Now there is a one ways to actually build up a simulator with this, but doing simulation you have to now build up a model of this system of every switch how this is going to operate. So, the model which we are going to look is basically based on a mechanism called feedback. So, if this buffer is there is this buffer is free I can send the information back and this can maintain a state whether buffer is available here or not here based on that whatever is occupied in this buffer can move or cannot move. So, there for example, there can be at the input the packet for the same output if this buffer is going to be free then only this flag will say the buffer is free and both of them will be told one of them will be picked and will be pushed into this buffer other one will still remain. Now packet from the previous stage can only come when this buffer will get free. So, it is like packets are hopping from one buffer to another buffer and the buffer if the packet in front of you actually moves ahead then only you get the chance other you just remain there under this situation under given load what is going to the throughput performance that is a basically is the issue. At some point of time you will find out you cannot achieve higher throughput throughput is limited it cannot be unity here obviously, because there are contentions. So, what I will do is actually I am now ending here because I think I will cover up this thing I am not taking 2 hour class today honestly only taking 1 hour I will take up another Saturday sometime and then actually take 1 hour extra there. So, the paper which we have to follow for this one I am just giving so that you get actually can go back and read it before you come to the class, because this is slightly tricky part especially it is a transitions and how to change the matrices and how to compute simulator is not given code here, but once you understand this then you can write a simulator. So, doing simulation is not a trivial exercise you have to build up a complete mathematical model. So, this paper actually large part of it is actually on how to build up a model of a switch so that it can be simulated and you will be using a patterned model for this actually. So, patterned is what I taught in the previous semester same thing will be used here again. So, this one is Dias and jump this is IEEE transactions on computers actually I write this one because it actually shows tells for the first time the complete details before you start doing the simulation part and theoretically also an analysis actually can be built for this that is one good thing title is analysis and simulation of buffered delta networks and simulation of buffered delta networks. Basically we are doing input queuing with the output but now in every node and with the flag at the output which corresponds to the input of the. So, you can move at only if the queue is in front of you is empty otherwise you remain in block the state. So, input also cannot come see even if a packet arrives at the input, but it cannot enter because somebody else is already occupying your state. I am not dropping the packets in intermediate switches remember I am not dropping the packets here, but that is a different case again. But if you use output queuing you will have to draw packets at a particular stage, if you use output buffering. How I will do there is nothing like output and input what is the output of a switch is the input for the next stage. So, this. So, model is same you take either input or output. So, this is actually input queue is being considered for every switch. A packet comes in only one packet can be buffered here and the packets from these buffers will move to further stage. If for example, this buffer and this buffer both are free both flex will show and this packet has to go here this has to go here they will go immediately. If both have to go here only one go and one will remain blocked. If both have to come here one will go and one will remain blocked based on that this signal will go back. So, continuously state signals are moving in backward direction packets are moving in the forward direction. So, it requires exactly n steps to move to n stages out of the switch. So, there are some steps which are being defined for movement and after this I think we will then go to wipe or say base systems actually.