 Hello everyone, Myself Prithviraj Thambe working as an assistant professor in Department of Electronics Engineering at Vulture Institute of Technology, Singapore. Let us today learn Programmable Logic Arrays. At the end of this session, you can examine the general structure of Programmable Logic Array and you can implement simple Boolean functions using the PLAs. So what is PLA? It is a combinational programmable logic device an integrated circuit with a programmable and array and a programmable or array and this combination provides and or that is SOP implementation of the given Boolean function. So this is the general structure of programmable logic array. So input lines, programmable and array, programmable or array and output lines. So when you compare this structure with the PAL, you will notice the difference that in PAL array is fixed and in PLA this or array is programmable. So programmable and array accepts n number of inputs and their complements and multi input AND gates are used to produce at max 2 raise to n number of AND terms but in PLDs the number of these AND terms is far less than the n variable mean terms that is 2 raise to n. So you can go through the specification of any PLDs available in the market to understand how many AND terms are possible. Programmable or array. So the AND terms from the AND array are fed to the OR array. So this OR array is programmable when you compare this with PAL in PAL as I mentioned OR array is fixed. So together AND array and OR array realizes a set of outputs in the SOP form. So let us design one example but before that let us go through these some of the points. As we have noticed in the previous slide that these AND terms are very very limited. So the Boolean functions which we need to implement needs to be minimized. So that we can have less number of product terms and those never exceeds the number of AND gates in a PLA. So realization of this Boolean function using PLA is totally based on the product terms and it is not always necessary the mean term. So fuses are programmed depending upon the product terms which we have obtained after the minimization and this realization is also totally based on SOP expressions. So let us implement this example. So take few minutes and minimize this expression. So f1 is a function of ABC. So this is a 3 variable function and the mean terms are given 0, 1, 5, 5, 6 and 7. So you can use any method for this minimization. So let us see the answer. So I have used here a K-map for the minimization. So after putting these mean terms in the K-map I have formed these groups and the final function after the minimization is AB plus A bar B bar plus AC. So for group 1 is AB, for group 2 is A bar B bar and for group 3 is AC. Let us implement the second function. Again this is a 3 variable function 0, 1, 3, 5, 7 are the mean terms. Let us minimize this function also. So in this session we are going to implement two functions using PLA. So again after using K-map f2 is equal to C plus A bar B bar is the minimized form of the given Boolean function. So for group 1 I have a group of four mean terms which gives me C and two pairs M0, M1 gives me a product term A bar B bar. So now these are the two terms f1. So in f1 we have three product terms AB, A bar B bar and AC. In f2 again I am having two product terms. One is a C and second is A bar B bar. So let us implement these two functions using a single PLA. So this is a simple PLA drawn here. You will observe here AND array is programmable as well as OR array is also programmable. So let us implement f1. So three product terms. So we require three AND gates from this array. So first term is AB. So here you will see that this AND gate accepts A and B as inputs and generates AB as a product term. Second term is A bar B bar. So again this particular AND gate generates this product term A bar B bar. So these fuses are kept intact and the remaining fuses are blown. Third term is AC. So here you will see that these two fuses are intact. So the output of this particular AND gate is AC. So the function f1 three product terms three AND gates are used here to generate these three product terms and they are all ordered together using these three fuses. So these three fuses are kept intact and the remaining three fuses are blown. So the output of this OR gate is nothing but your f1 which is AB plus A bar B bar plus AC. Now let us go to the second function. So here this f2 is a combination of two product terms. First is the C and second product term is A bar B bar. But if you compare these two functions you will notice that this product term A bar B bar is common. So instead of two AND gates for f2 you can use only one AND gate for C and you can reuse the AND gate which is used to generate A bar B bar. So f2 you will see here to generate C product term this first AND gate is used. Here this fuses kept as it is and the remaining fuses are blown. So the output of this first AND gate is C and instead of using new AND term instead of using new AND gate I am reusing this AND gate output. The output of this AND gate is what A bar B bar. So here I am reducing the use of the AND gates. So again here these two fuses kept intact and the remaining fuses are blown away. So the output of this second OR gate is nothing but C plus A bar B bar. So if you compare this design with PAL you may have required more number of AND gates to implement the same function. These are the textbooks you can refer for the further reading. Thank you.