 సినేసి టార్ందర్. నినార్సి ఇనేదిందుత్నాలు మిడిల్చా మార్దార్టిబి ప్రలిల్దార్చిసి్దిసింద and moving forward how to estimate how to analyze multi states are involved and we come to choosing in a best number of stages using this concept using this same concept we look at one example and we will come to this topic. Now when we let us say you are in initial phases of starting a design that is you are starting you are building up these gates and building up a circuit from those gates and we are we are faced with a array of choices we should choose what is the best circuit topology for a function how many stages of logical could be played how big the transistor should be and so on there are lot of choices. Now logical effort is a method which allows us to make the business it uses a very simple model of very that is it uses only gate delays it does not mention anything about the network it allows the calculations on a paper it helps us making rapid comparison between various alternatives available it we can we can choose number of stages with you the great type with the command or more of use inverters how many inverters to use and so on it takes advantage of the symmetry the symmetry which are already existing in the circuit topology during the course of this lecture it will be advisable to get hold of a pen and paper because there are some formulae here and there will be some calculation so it will help a lot if you already have a pen and paper only. Now just to give you a big picture this logical effort is purely a method which is used on pen and paper it is the usefulness of this method in present times is limited to understanding the multi stage networks in doing this course you will never use this method to do anything that is the synthesis tools will do everything for you for example if you are designing a let us say you are designing a decoder for example you already have a library of cells available we for example you have 2 input 9, 3 input 9, 4 input 9 depending on only kind of library to use plus you will also have these so the design compiler for example is a tool that steps into this also that tool will automatically do stuff for you that it will choose what date to use it will choose how many stages to use in the network obviously depending on some input constraints to use but just to emphasize this logical effort which only make us help us in understanding the multi stage networks how do increasing or decreasing number of stages affect delay and so on so the formula given here or the example given here they are just used to explain the concept they will not be used in a practical you know let us take an example of a design so there is a memory designer for when it is written he is working for a motor oil which is an automator processor now what this memory designer is asked to do he is asked to design a decoder for a register file register file is nothing but a memory all a bank of registers the specifications of this design we have only this example in this example we will only define the force of the decoder assuming the register file is already there so we will only look at this circuit so the specification are that this decoder is used to address 16 or register file so that means this memory bank here has 16 words and each word is of particular bits each bit in this register file presents a load of the unit size transistor we will see how that is used later we assume that 3 bit 4 bit address and 4 bit address complement bits are available now each input may try 10 unit size transistor we will see the use of this so the designer needs to decide how many stages to use how large should each stage be and how fast can decoder operate so let us see the concept of logical effort and we will call this property now let us extend the delay in a process independent unit that is it so we introduce a time constant called power this is the 3 Rc this is the technology dependent parameter so it has some values for example it is about 12 PS and 19 ammeter about 40 PS and 16 ammeter and so on now we extend the delay to be the absolute delay divided by time so delay absolute is technology dependent power is technology dependent correspondingly D logical delay is technology independent now a delay of a gate as or a network or a multi stage network has to company D is equal to S plus T S is the effort delay that is how much effort does a gate have to do to drive an external network this is called stage effort or effort delay again it has two components G and H G is the logical effort which measures the ability of the gate to deliver parameter this measurement is with respect to a unit inverter let us say we assume that the unit inverter has logical effort of 1 that is G is equal to 1 now we will compare all gates against this unit inverter and calculate the logical effort H is the electrical effort that is it is the effort of the fan out of driving the fan out it is the ratio of the output capacitance of a gate discounting the internal capacitance that is the output capacitance when calculated will not contain the capacitance the ratio is of that capacitance will input capacitance since the output capacitance represents the fan out or the load on the stage this is also called the fan out effort so F is equal to GH and delay is equal to S plus T T here is the parasitic delay just to repeat the concept parasitic delay represents the delay of a gate which drives no load it is nothing but the internal parasitic capacitance of the gate as seen by drain or source so this is a straight line on the plot of let us plot T versus H now for a particular gate in isolation H will be a variable since it represents the fan out T will be known since it is the intrinsic capacitance it depends on the intrinsic capacitance similarly G will be known since we know that since G is fixed for a particular gate type we will see that in the next slide so we plot D versus H and see how does it look like it is a straight line equation so the parasitic delay is seen here it is the fixed delay for example for an inverter the parasitic delay is 1 for 2 input fan gate the parasitic T is equal to 2 G is equal to 4 by 3 we will see how G is the right path so this is the equation D is equal to 4 by 3 H plus 2 similarly for inverter D is equal to H plus 1 and what this line represents here is the variation of the delay of an inverter and a 2 input fan gate depending on the so the the bi-action is the delay path depending on the x-axis value it is H it is nothing but the fan out so as we increase the fan out the graph here tells us how much the delay of a inverter or 2 input fan will be given similarly we could do this for any gate for example you could try and plot this type of line for nor 2 and 3 how does it compare with the 2 input fan gate obviously for that you would need to know the value of G and P we will come to that how the value of G and P is now let us come to the computing station of logical effort that is the value of G so by definition logical efforts or G is the ratio of input capacitance of a gate to the input capacitance of an inverter in the past lectures we saw we learnt how to size a gate for example the NAND gate here this NAND gate we have seen why the sizes should be 2 and 2 when compared to an inverter similarly we have seen for NOR gate why the sizes should be 4 and 4 and 1 I would request you to go back and again revise those concepts because they are very very so assuming these sizes are available how do we calculate the value of G now the value of G for an inverter is defined to be 1 or you could say that C input capacitance seen by inverter seen by input A is 2C 2C plus 1C which is PC so C input is 3 for a NAND gate let us consider input A and we have seen AC is the capacitance 2C plus 2C which is 4C the scene is 4 so G becomes the scene of NAND 4 divided by scene of the corresponding C inverter which is 3 so G is equal to 4 by C for NOR gate AC is the cap 5C so G is equal to 5 by C by the similar concept so this is the way we estimate the value of G by counting from the circuit you could also do that measurement from the day versus standout plots but this is the way we go we will see let us revise again we see the input capacitance and compare it and divided by the input capacitance of a unit inverter unit inverter sees the input cap of 3 so the input A here of the NAND gate sees the G is 4 C in is equal to 4 4 divided by C this is the table so for a 2 input NAND gate it is 4 by 3 for NOR gate it is 5 by 3 in NAND equation becomes N plus 2 by 3 NAND equation becomes 2 by 3 please note that NAND and NOR are symmetrical that is all the inputs are similar in terms of capacitance but for ZOR and NOR this becomes different so for a 2 input ZOR both inputs are same 4 and 4 but for 3 input ZOR one of the input C is higher cap we could actually go to the CMOS level and verify that this will deal with the gate similarly for prior state marks the input the value of G does not depend on the number of inputs it is only 2 we could again go back to CMOS level and we will do that now from this table one thing is clear that the lowest okay from the delay equations it is clear that the gate system lower value of G will have lower delay so from the table it is clear that NAND in CMOS technology NAND is superior to NOR when it comes to delay when it comes to being fast this is why we see what are NANDs being used in designs when compared to NOR now this is the characteristic of common gate to calculate the value of P so assume the value of P for inverted one let us go back to the so for value of the value of P represents the inherent capacitance that is inherent output capacitance without the NOR so output Y here of the NAND gate it sees the capacitance 2C plus 2C that is 6 output Y of inverter P is the cap 3C so P is equal to output cap of this NAND gate divided by output cap of inverter which is 6C by 3C is 2 similarly for NOR NOR C is 4C plus C plus C again 6C divided by P of inverter is 2 we see the table so NAND and NOR are same in terms of the inherent arithmetic capacitance so this is again in multiples of P inverter so NAND 2 input NAND gate is 2 2 input NOR gate is 2 it increases as the number of inputs in P so because the P MOS or the N MOS it also increases for tri-state MOS similarly it also increases for ZOR and NAR there is no need to calculate the value of P and G for every gate you could see that the most common gate and you could look at these tables and use these values in the equations by deciding the number of students let us take an example of ring oscillator ring oscillator ring oscillator is a very very common circuit very popular circuit to find out how different parts of it is very useful in qualifying the process what does this mean is that the tip part I am working on a chip it is a big chip a new technology so what I could do is that I could place ring oscillator at some side of the points in my chip and ring oscillator is nothing but a clock of some frequency that frequency is dependent on the inverter delay delay of an inverter so the N-stage ring oscillator N here is always on because N is odd this circuit will result into a clock output so the frequency of a ring oscillator depends on the delay offered by one inverter and it tells us how the process is going what how the NMOS will NMOS pass the PMOS flow or PMOS will pass the NMOS flow we can cage that the performance of the inverter by using the ring oscillator so let us see let us calculate the delay of this N-stage ring oscillator so the G since it is an inverter base circuit the G is 1 but H is also 1 since the sum out is 1 for all these inverters the dataset delay is 1 for inverter it is time to be 1 so the stage delay D is equal to G H plus P we substitute these values so D is equal to 2 now the time taken by this N-stage so for example you give an input you give an input here at this point the delay on this input to this output is 2 is N into D so the delay part is N into D this delay represents the width of so the output is a clock the output is like this so the delay of the high pulse or the delay of the low pulse is equal to N into D so the total time period high pulses is 2 N the frequency of the string oscillator becomes 1 divided by 2 N we substitute the value of D we get 1 by 4 N so we see that for a particular process that is we do not deal with the time independent technology independently so you have to put in technology numbers to get the actual frequency so example here is the 31 delay stage ring oscillator so we see that the frequency depends on the number of stages as we change the number of stages the frequency can be so we see how do we calculate the delay of some in-stage simple circuit using the concept of logical approach again please note that the delay offers the interconnect is not taken into account this type of expression is logical it is it does not have any physical data the interconnect the wires that connect the gates together represent the physical data because they represent these legs represent how the circuit is laid out but here we do not include that so we call this as logical that is why it is approximate and approximate in nature but it helps us in making time decision let us look at one more example it is a fan out of core inverter we estimate the delay of a fan out of core inverter again inverter is the simplest of that it will be the value of g the value of g is 1 it will not change because it speaks for a gate value of p is 1 but now h here changes because h represents the fan out so the definition of h is that p out divided by c in p out means this p out so it gives us the node of core inverter divided by c in it is one inverter so the value of h is 4 again d is equal to g h plus g so d is equal to 5 again there are some values given here depending on the process so this is the formula f by 3 ns and ns have to meet the process so this using estimating delay of an inverter based circuit as we saw it is very very easy because you see the value of g you see the value of p when it comes to NAND and OR it becomes slightly more complex let us see now we come to multi state network till now we have been seen we saw how to estimate the delay of a single stage or a fan out of core inverter for example which is two stages but a fan out of core so logical effort can be generalized to multi state network so we define two things here first thing we define is the path logical effort so g the path logical effort g is the multiplication of all these stages all the logical effort values of all these stages depending on the number of ways path electrical effort h is equal to the output capacitance seen at the end of the path divided by the input capacitance seen at the input of the path we define capital F is equal to again multiplications of all these individual F values so it is the multiplications of gI nature when I will present this example let us see this example so we have inverter now also note one fact that when we start calculating the path delay in most of the cases you will have no confluent terms but you could choose what inputs you want to analyze it today also for example the analysis here the blue line here starts from inverter goes up to the output and there are multiple paths in this network for example you could have a path from this input effects to the output or you could have a path from this input of Y to the output so the the path delay depends on the actual path that is what input do we choose here we are choosing the input of the inverter so the 10 in here represents the sizing of the inverter so X and Y let us say so G for inverter is 1 H becomes the load presented by this so X by load of inverter which is 10 here so H1 is equal to X by 10 X is equal to Y by X X is equal to Y by Y H4 is equal to 20 divided by 10 value of G G of non gate and G of on the table so in this way you could have so you could we could calculate the value of the total path delay by multiplying by having G1 H1 G2 H2 G2 H2 ultimately H still be nothing but C out that is 20 divided by input cap that is 10 is equal to 2 now the question is can we write S is equal to G H the answer is no but now let us see path that have branching which is very common happening it is not there that path will branch out let us say we choose this path chose by the dotted blue line dash blue line there so G here is G1 G2 so G is since being both are inverters so G is equal to 1 into 1 is equal to 1 H for this is 90 divided by 5 18 so G H is equal to 18 H1 the stage effort here is actually 15 has 15 that is 30 divided by 5 because this node here is seen the capacitance offered by both the inverters so it is actually H2 just that is this stage this stage is 90 divided by 15 so F by formula is G1 G2 H1 H2 is equal to 36 so the actual today is 36 but if let us say you assume that F is equal to 2 H it comes out to be 18 which is exactly half of it how do you factor that in the formula like this we introduce something called branching effort the branching effort B is equal to capacitance upon path the capacitance of path divided by capacitance into 1 or capital B is equal to multiplication of all the branching efforts now the formula is F is equal to GBH now in the previous example these 2 branches are symmetrical in nature so the branching effort using this formula will come out to be 2 so there are 2 branches here or we could say now this inverter here has 2 branches and both the branches are same you offer the same load so the branching effort becomes simply 2 we will use this concept in the coming time or you could also apply the formula that is this formula this formula and see that the value of B is impactful so now we define the complete path delay to be DF is the summation of individual is the summation of all FIs parasitic delay is the summation of parasitic delay of all these phases so path delay is D is equal to DF let us see or a multistage effort now using this formula this formula we say that delay is smallest when each stage bears the same effort how is this derived you differentiate it and make so is equal to 0 and you use differential calculus you do this you would come out with the same result that the delay of a multistage network is in each stage bear the same effort or in other words we say that each stage delay is let us say there are n stages each stage delay is nothing but F raised to the power 1 by n so when all these stages delay are multiplied together they will produce the least amount of delay therefore we say that since each stage delay is F to the power 1 by n then there are n stages the minimum stage delay of a minimum delay of a n stage path is number of stages multiplied by individual stage delay that is the parasitic delay seen by the delay this is the most important result of the logarithm this enables us to find the fastest possible delay without even calculating the gate size let us see let us see an example how it is done now one more thing is since we said that in the previous slide that this formula here it enables us to find the fastest possible delay without calculating the gate sizes but the second step of that process would be to actually calculate the gate size so how do we do that and that is equal to g h or g c n we know c out we will see how we know c out we know the value of g i and we have calculated the value of f so c n is equal to g i c out divided by this stage delay be calculated this stage delay let us assume that is the first step now working backwards we could apply the capacitance transformation to find the input capacitance of each gate let us solve one problem now in this case we have to select the gate size with x and y for the least delay from a and b now what we know we know the output capacitance we know the the size of the input input gate and in fact to start the problem to take some values what we could do is we would always know this mostly we would do the output delay from this specification mostly output we could start with any size gate then we decide the number of stages and then we calculate we calculate the sizes of the intermediate stages this is how the problem is solved now let us see how this is done so logical effort g is equal to the multiplication of g i of 2 input NAND 3 input NAND and 2 input NORS so 2 input NAND 4 by 3 3 input NAND 5 by 3 2 input NORS 5 by 3 input NORS so it is 45 by 8 branching effort now again we see that both the branches that is 3 branches here and 2 branches here they are both symmetric so we could use the formula of the capacitance or simply we could say that since they are connected the formula would come out to be branch effort of 3 3 into 2 is 6 branch effort is s is equal to g b h 1 by 5 g b h now here obviously it is not important to know the value of x and y it is not necessary to know the value of x and y to calculate the branch effort but assuming we know the values of the input capacitance and the branching structure if all these things are known then we can find out the size of x and y from the limit so we have the value of 25 which is the please note it does not include the f only represents the part delay of all these states all these stages now since it is a 3 stage part we mentioned earlier we saw earlier that the minimum delay would be when each stage makes the same effort there are 3 stages since the delay is multiplication then each stage makes an effort of new group of f then we have the minimum delay so best stage effort f is equal to as cap is equal to new group of f which is 5 now we calculate the characteristic delay we can look at the table the input bandwidth is 2 the input bandwidth is 3 the input bandwidth is 2 the p is equal to 7 so now the stage delay becomes 3 into 5 which is delay is now gph which is 150 15 which is since the delay of fan out of 4 is 5 so 3 into 4 is 4.4 3 into 5 because n is equal to 3 and the value of f is 5 so this is the formula we use I will go back to the last one so we use this formula n is 3 we calculated since n is 3 we calculated 2 group of f is we calculated p to be 7 so delay here is 3 into 5 is 7 please review this slide very very carefully it contains almost all the concepts of logic effort it also contains branching it tells you the method of doing it that is first we calculate the path effort then we first calculate the path effort this is the first step next we calculate the best stage effort and third we calculated delay now we go ahead and calculate the value f and 5 now we saw that in the previous slide so we now use this formula we use this formula gi c out time by stage delay the best stage delay this is the calculated to be f gi again will be date dependent c out we will work from the the output side we will know c out so we could know c so y now is equal to c out that is 45 into gi gi for a 2 input node is 5 by 2 divided by the value of best stage effort 15 now this represents the size that is the input capacity so 15 now we have to go and size north as that we have 15 so here for example the PMOS switch is given to this well you can compare this is the unit size inverter and size problem so the sizing concept once you know that you have to maintain the input capacity you can 15 c you can go ahead and size the north in such a way that input capital exactly 15 because size c and n must be some value where p is 12 now we calculate x x again the c out here is 15 we have to be calculated this to be 15 so man the 3 input man c is the value of 15 value of gi is 5 by 3 for a 3 input man again divided by s is equal to 10 again the 3 input is size so that is equal to 4 so this is the way to calculate the sizes of the NAND and NORGATE in the stage path now so in the previous example the number of stages was known beforehand these problem was calculated in the size of the NAND and NORGATE now mostly in most of the cases usually the question is that from an input to an output how many stages are needed a path could have lot of parallel so that the number of stages are known or a path could have could be a single standard path number of stages are known so how do we decide whether we need high number of stages or low number of stages given the fact that very number of stages is not always possible for example we are driving a 64 bit data path that means the path here is 64 and we compare the value of delay for 1, 2, 3 and 4 stages we could go ahead make this circuit on a paper and use the formula to do that you already know the number of stages we will just fill in the values here so N is equal to 1 the X is equal to 64 D is equal to 65 because the value of G is 1 P is 1 so D is equal to F plus G H so it is 64 plus 1, 64 here the D is 18 because we there are 2 inverters here so D still remains 1 so yeah F is equal to 8 these values you could go ahead on a paper and verify these values the important point here is that this is the equation we came up with we know the value of F to be 64 we know the value of P to be the number of steps in a number of inverters being N the value of P to be N this is the equation we have now we are trying to find the minimum number of the best number of stages we do not solve this equation actually here the example is that we assume some number of stages or and we find the value of the delay we find that for 3 stages for these particular stages the path is faster it has the delay in the value of 15 now see the difference between this number of stages being 1 and the number of stages being 3 and also note that the delay decreases when we go from 1 to 2 and 2 to 3 but delay increases when we go from 3 to 4 this shows that when you find the number of stages there will be some optimum number the rating from which will always result in an increasing delay that is the question now this is a derivation given for the formula but I will not go deeper to this you could this is not very important the important thing is to understand this kind of equation to understand how this method is applied so there is one graph here which shows that how sensitive it will be to using the exactly best number of stages so this is this graph is based on on this equation so on this equation where rho is equal to the best stage effort so this equation has no has no close form solution so it is best plotted and found that for some let us say for so this x axis here is normalized so n upon the past number of stages and then where is the derivative so this shows that for some value of rho between let us say 2.4 and 6 give the delay which is 15% of optimum that means maybe not always you will find the best number of stages but you need to be close again I would stress one point that for practical world where you are designing circuits which have millions of bits or even thousands of bits this cannot be done by hand this is a tool like design compiler which actually do that for you and we will see that it is quite possible that not all paths have the optimum number of stages it all depends on what constraints will be given so the number of stages depends on how much let us say from input to output let us say if we define the delay to be define the constraints that input should be the output should depend on the output after let us say x units so the tool will choose n number of stages I do not need x I need something more than x so now tool will actually change the value of n so the number of stages the tool choose is based on what constraints we get this type of analysis is very very difficult to do the shine when thousands of bits are concerned and number of paths are concerned but this actually will give you some idea the point to understand here is that 90 stage network it is not always fastest when the number of stages are there is one some optimal optimal value of the number of stages which produce minimum amount of delay and in fact this is this concept not in this form but in a slightly more complex form is used by the synthesis tool to determine the number of stages so tool has a choice usually tool has a choice using let us say an array of mandates or muscles or nuggets so it uses a similar kind of analysis to find out what should the tool use now we come back to the decoder example and now we see that how do we apply logical effort to find out the number of stages here how large should each state be and we will calculate the delay also now I will go back and forth in two sides so the decoder effort let us see the decoder design form so the decoder will work something like this we will have the address bit the complement of address bit each of them goes to inverter there will be a NAND gates so for example to select word 0 so we need 16 select lines out of which only one will be active at one point to get the value of the select lines we pass them through a network of NAND gates for example this NAND gate we will select word 0 then so it takes in the value of when a 0 a 1 a 2 a 3 are all 0 so we take all these four lines through one 4 input NAND gate connected to an inverter so that when all 4 are 0 this NAND gate will be 1 and yeah so when sorry when this all 4 are 0 this NAND gate will be 1 and correspondingly this will select this word line and so all these word line values all these word line outputs are excluded the point to note here is that each each address line will go to 8 such NAND gates now we go back and see so what is the electrical effort the electrical effort is the load offered by the bit cells so we saw in the previous slide that each word is 32 bit wide which presents 3 unit size from distance so the load seen by the select line is 32 into 3 so this is the load 32 into 3 which is it is the output load see out divided by input load input gap which is each bit input can drive upto 10 unit size from distance so it is branching effort is 8 why because the circuit is perfectly symmetrical one branch is same as other branch each input goes to 8 gates so branch is out to 8 gates 8 NAND gates so the branching effort is 8 so assume G to be 1 to make the calculation simpler we say that F is equal to GBH is equal to 76 by 8 number of stages now this is the catch here you will not know number of stages at first okay you can only estimate and then choose some value for example in this case N is equal to log F4 now N is equal to 3.1 and you could also 2 3 you could also 2 4 so let us try a 3 stage design according to this example so this design is again 3 stage inverter 4 input NAND and one more inverter so G is equal to multiplication of G I is of all these stages so it will be 1 1 for this inverter into 6 by 3 is the G of 4 input NAND this one represents G of this inverter so it is 2 G is equal to GBH G is 2 G is 8 H we calculated earlier it is the value of H was 76.8 so rounded off F comes out to be 154 each stage best effort stage delay we know it is a 3 stage thing so we take a 2 group of this it is 5.36 parasitic is 1 for this inverter 4 for this 1 for this inverter please note so parasitic you can you can go back at the table and see that 4 input NAND has in fact the 4 value of 4 for the value of P so this D is 22.1 again the calculation of Z and Y is very very similar the formula is GI C out divided by F so we know the value of F the example to know the value of Z we know the value here we know the load here which is 36 into 3 again divided by we know the value of F we know the value of GI of this which is 1 so we can calculate so it is 96 83 into 1 divided by 5.36 is 18 the value of Y so the C out here is 18 into into G which is yeah into GI which is 2 divided by 5.36 6.7 so this the calculation is very similar to the last example you know now the question is that we we chose yes we chose 3 phases which would have been optimal but what about the gates in those phases for example to start with we chose inverter 4 input NAND so inverter now this tables here shows the value of different stages so for example we could use a NAND an inverter based design the value here is 2 N is 2 similarly NAND and NOR N is 2 we saw this example where it is inverter NAND and inverter you could also have a 4 so we saw that the value of N came out to be 3.1 or you could start with 4 if you would have started with 4 in fact NAND inverter NAND NAND 2 inverter NAND 2 inverter you would have in fact got the least delay as the tables are list so yes this logical effort will help you in finding the optimal delay but not necessarily it will be least so there are options here available which are less delay than the value we complete so we see that actually choosing N is equal to 4 gives these values 21.1, 20.5, 19.7 which are in fact all 3 are less than when we chose the number of stages should be 3 so that is why I stress that this process is not easier in fact even if you see the number of phases in 5 and 6 the delay here 20.4 and 20.5 which is in fact less than 22.1 which is all so yes this process will help you in deciding something but it will not necessarily be the best that is why it is not humanly possible to do this for all the circuits of N so we review the definitions the number of stages for a path is N logical effort is G or for a path it is the multiplication of individual values of D electrical effort is C out by C in for a path it becomes C out path by C in path the branching effort formula is this for a multi stage path it becomes multiplication of the all the branches all the branching efforts of all the branches F is equal to G H for a stage F is equal to G V H for a path effort in a F D F is equal to summation of all effort delays of all the paths parasitic delay P P is summation of all the parasitic speed of all the gates delay is equal to D is equal to S less V D is equal to summation of all D S less V so the algorithm is we compute the path effort F is equal to G V H best number of stages log 4 of F I will come to this Y4 sketch paths with N stages estimate the least delay we determine the best stage effort F is equal to 1 by N we find the gate size now again estimating best number of periods we could start with the next slide will explain the limits are that it is a chicken and egg problem that means we need path to compute G but we do not know the number of stages without G so the thing is that let us refer for earlier decoder examples to compute the value of G and to compute the best stage effort we need the path but how do we decide the path let us say until we do not have the actual circuit this is why it is a chicken and egg problem so we you start with something and then compare it with the other options you have that is why it says log 4 F what it recommends this slide recommends is that you start with a 4 stage effort and compare for example we saw here so here we actually started with a value of 3 we could also have started with a value of 4 again this would come from experience so that is why you have to assume something start and compare it with the alternative you have it is a very very simplistic delay model it neglects the input rise time effect it does not have the value of interconnect it only tells it only works on the predict that we want to minimize the delay it does not work on any numbers when we come to synthesis we see that delay is not the only important thing there are actually three important differences in the process model in modern digital design the delay the area and the power this model is only only for maximum speed it does not take into account the other two methods so the logical effort is useful to understand how do multiple stage network work you could actually see you could appreciate few points you could appreciate one that NANDs are faster than NORs we saw that the value of G logical effort from NAND is better and sometimes not so NANDs are faster than NORs we could also see that part delay is sensitive to stages and values what this tells us what this you can appreciate more than you can actually come across a standard scenario you will see that a library has multiple flavors of cells it has NANDs it has NORs it has two input NANDs three input NANDs four input NANDs it does not go beyond four I have not seen beyond four NANDs combining of NANDs or NANDs it has different combination so since there are different flavors different types of cells available the tool has more freedom in choosing and coming up with a better area or a better timing based on what do you demand actually logical effort although it does not give you lot of tools to analyze it in your own paper it does not give you insights into how the tool would go we see that parts are faster on paper we saw that when effort delays are close to four that is why you had that is why this formula N is equal to log N log four of F and the number of stages are log four of F because we saw that now see the delay value is independent of the technology here so we saw that when N is equal to log of four F will actually give you it will actually give you very good starting point for the number of stages we saw that the fewer stages doesn't mean faster path actually this is very much used by the physical design tool to buffer the next so what physical designs tool do is they analyze long path and they have some algorithm it must be based on similar kind of model to insert buffers on inverters to speed up their path to actually insert the optimal number of buffers in effort so the delay of path is about log four of F fan out of four inverter delays the flip side is that it requires practice to master but as I told you don't just study these this lecture how does the delay depend on the output path how does the delay depend on the number of stages but don't take too much read if you are not able to calculate the number of stages or the sizing of the bits when we start synthesis which is the core of this course which is the core area of this course we will have two things available with us we will have a standard the library with different types of gates and actually the sizing of transistors is not visible to you what is visible to you is the capacitance at the inputs and outputs of those bits the timing parameters of those bits that means how path or how slowly they path that's what you have available with the interface tool which will choose the gates for you what you control however you control input parameters that go to that tool which helps it in making the decisions that is the decisions means what how many series to choose you will see that in much more detail in coming lectures just study these slides and understand how does the delay of a multi-stage network what does the delay actually depend on next we will see you will appreciate these concepts much more when you actually work on synthesis thanks