 Hello, and welcome to this overview of the hardware architecture of the STM32MP1 series. This block diagram summarizes the key features of the STM32MP157, which is part of the high end line of the STM32MP1 series. The STM32MP157 microprocessor integrates dual cortex A7 32-bit core with single and double precision floating point units, plus the ARM NEON advanced SIMD instruction set, and can run at up to 650 MHz. Each core has a 32-kilobyte level 1 instruction cache and a 32-kilobyte level 1 data cache, plus 256 kilobytes of level 2 cache shared between the two cores. In addition to this powerful application core, it also embeds a Cortex-M4 32-bit risk core with single precision floating point unit running at up to 209 MHz. Finally, a powerful 3D GPU is available supporting OpenGL ES 2.0 and running at up to 533 MHz. The internal SRAM memory size is 708 kilobytes with a scattered architecture split into 256 kilobytes of AXI system RAM plus 384 kilobytes of AHBMCU subsystem RAM plus 64 kilobytes of AHBMCU subsystem retention RAM in backup domain and 4 kilobytes of SRAM in the backup domain to keep data in the lowest power modes. This line also includes up to 37 communication peripherals in addition to an LCD TFT controller interface which can feed pixels to a parallel or display serial interface or DSI having two data lanes up to 1 gigabit per second each. The STM32 MP157 line also embeds low power 16-bit ADCs running at up to 3 mega samples per second 12-bit DACs as well as 29 timers. The STM32 MP1 bus architecture is split into two interconnect matrices ARM Cortex-A7 and ARM Cortex-M4 operating in different frequency domains which can be set in low power modes independently. One high-speed ARM core link 400 network interconnect AXI based performing interconnection between master and slaves on the ARM Cortex-A7 side called the MPU side operating at 266 megahertz CK-ACLK and allowing an internal bandwidth up to 2 gigabytes per second between each master and slave. This matrix is optimized for low latency and very high bandwidth master transfers to and from external DDR as well as internal SRAMs. An internal DDR memory provides a raw bandwidth up to 4 gigabytes per second. Peripherals belonging to the AXI domain are connected to AHB5, AHB6, APB4 through AHB6, and APB5 buses. One multi-layer AHB interconnect or ML-AHB performing interconnection between master and slaves on the ARM Cortex-M4 side called the MCU side with an architecture inherited from former MCU and operating at 209 megahertz CK-MCU. AXI interconnected matrix or AXM and multi-layer AHB or ML-AHB are connected together to enable the sharing of any peripheral by any master. Blocks with dashed lines are not available on all product lines. Security is not shown in this overview. The AXI matrix is enabling the interconnection between up to 11 masters and 12 slave peripherals. The AHB matrix is enabling the connection between up to 10 masters and 9 slave peripherals. Some memories are dedicated to Cortex-A7 core access, for example BootROM and DDR, and benefit from the optional access control using the ARM trust zone technology. The memory map addressed by any masters is the same. All peripherals are visible at the same address, simplifying the development and debug. There is no dynamic memory remapping. Only part of the MCU SRAM and RETRAM memories are aliased on two locations to allow Cortex-M4 access optimizations. The reset and clock controller or RCC manages the system reset and the peripherals clock generation. The STM32 MP15x microprocessor embeds three internal oscillators, two oscillators for an external crystal or resonator, and four phase locked loops or PLLs managed by the RCC. Outside the RCC there is also one dedicated PLL for the high speed USB. For STM32 MP15x lines with a display serial interface or DSI, one additional PLL is dedicated to the clocking of this interface. Many peripherals have their own clock, independent of the system clock, to allow maximum flexibility. The RCC provides high flexibility in the choice of the clock sources. This enables the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication BOD rates and also keep some peripherals active in low power mode. The STM32 MP15x microprocessor requires various dedicated power supplies to work. VDD has a wide range and is mostly used to supply the IOs. VDD core is the main supply for the internal logic. VDDA is used for the analog parts of the chip. VDDQ DDR is the IO voltage for the DDR interface. This voltage depends on the selected memory type and is 1.2 volts for LP DDR2 or LP DDR3, 1.35 volts for DDR3L and 1.5 volts for DDR3 memories. VDD3V3 USB HS and USB 3V3 USB FS are used to supply the embedded USB physical interface for respectively high speed and full speed ports. The STM32 MP15x also supplies some internal regulators to supply the USB and DSI physical interfaces. The core entering low power mode is controlled by software. When one core enters C stop mode the domain and system operating mode depend on the other core mode. LP stop system mode could be used to control external supplies to reduce the system power. LPLV stop system mode could be used to control external supplies as well as reducing the VDD core voltage to reduce the system power. External power supplies are controlled using dedicated power on or power LP signals in addition to some external software settings when an external power management IC or PMIC is used. Peripherals with IOs are mapped on GPIO alternate functions or AF MUX. Some peripherals are managed by boot ROM and can be used as system control or program download during the initialization phase. UART and USB are used to set up the system and or download code into the external flash memory. Note that FD can is not available on the STM32 MP151 line. SDMMC can be a boot source by using either SD card or SDMMC1 or EMMC or SDMMC2 memory cards. Quad SPI Bank 1 can be a boot source for serial NOR and serial NAND flash memories. FMC could be a boot source for SLC parallel NAND flash memories. Cryptography is not available on STM32 MP15XA devices. Securable GPIOs are only available on STM32 MP15XXAA, LFBGA 44818x18, and STM32 MP15XXAC TFBGA361 12x12 devices. The LCD controller can provide up to WXGA at 60 frames per second or 63 megapixels per second. Higher resolutions are available with reduced frame rate assuming the pixel clock remains in the allowed range. A 3D GPU is available on the STM32 MP157 line and can process up to 26 mega triangles per second or 133 megapixels per second. A display serial interface or MIPI DSI is available on the STM32 MP157 line and can provide up to WXGA at 60 frames per second or 63 megapixels per second. Higher resolutions are possible with reduced frame rate assuming the LTDC pixel clock and the data lane rate remain in the allowed range. OTP fuses are memory fields which could be programmed once and then cannot be altered anymore. The BSAC IP manages the control of the OTP fuses including reading, programming, and secure accesses. The OTP content includes product configuration and unique numbers. The OTP could contain OEM information such as the MAC address, secret keys, or any relevant data. Up to 1184 bits are fully available for OEM various purposes. Various blocks are managing the transversal system control. The major ones are the reset and clock controller or RCC, the power management or PWR which controls the system power modes, security which is controlled by trust zone inside the Cortex-A7 core as well as various blocks. The enhanced trust zone protection controller or ETZ PC defines which peripherals are secure or not isolated or not. The trust zone address space controller for DDR TZC blocks unwarranted access to DDR data. The main points to be noted from this presentation are the STM32 MP15x embeds a Cortex-A7 core able to run powerful operating systems like Linux or Android. The STM32 MP15x embeds as well a Cortex-M4 core able to run real-time tasks or act as a co-processor to reduce the Cortex-A7 load or power. The STM32 MP15x always needs an external DDR memory to run the operating system and the STM32 MP157 line includes a GPU which provides rich graphic capabilities for the operating system.