 So I will do like a quick intro first, I already did yesterday, just for people who are not there, I just want to kind of tell you what we are doing. So first, my name is Kody, I joined Google back 12 years ago. I'm a developer for Fodillation Engineer, which I focused on for many of the various kinds of developer products. And I work with a variety of products, but specifically I joined the other operations team, and I'm focusing on the other institutions for making it easier. So the mission of my team is to make custom SQL easier to build for everyone at scale, just at software. And like the vision is... Imagine that you could have an optimization flag that you could pass to GCC that lets you do a SQL design to optimize that stuff. What you are showing to me is software that you know where. Like sometimes when you optimize it in software, there is just so much that you can optimize in software, and you profile it like... At some point you will realize you will reach a point where you need to do an employer, etc. Which actually, there is a big gap. It's not even the same person who can do the big things. And the goal is to enable that co-design so that the same people that work on optimizing software will also work on helping design our work. And so for that, like there was a lot of missing pieces two years ago, but the ecosystem has a lot of problems. So now we have open source PDK, and the overall value of the stack for manufacturing in SQL is open source. Like we managed to develop and improve the open source solution for GCC, meaning that you have the solution to convert your design into a file that you can submit to the company. And there are more and more designs that people share, and a library that people share to an IP block that people share that you can reuse. And there are cheaper manufacturing options that you want to do because of SQL. So we really see that in those two years, like the growth of open source SQL in the system. And so I mentioned the open source PDK. So there is actually two PDK that Google has worked directly with the foundry for them to open source it. It's a PDK of 180, the 130 nanometer from Skywarder and the 180 nanometer from Global Foundry. So we work with them to enable the realizance and bring them open source something that works with the open source tool. But recently, we've seen also a new trend from other foundry that we don't even have Google talking to them that go and open source a PDK. And that's like what happened with HP. It's a foundry from Austria. And the release, if you look at their report, they try to follow the same organization that we did with Skywarder and the Raspberry. And I think it's great to see that. I think that there will be more and more options for people to do other stuff. And also like the Tushan we did there, because currently the Tushan were very skilled towards Skywarder and the Raspberry. And the process at HP is very different. There are two wheels on each other. The ecosystem will get better. So this is one example of the Tushan that at least we put together. Like for many projects that we have already done, there is that multiple way, multiple tools that you can substitute there. Just have one Tushan that works for converting your design to a file that you can submit to the Foundry. So when you come from a software background, you're not necessarily well versed into very low, like having to language like very low of the HDR. So sometimes people use what they call the Nile Level Synthesis. And Google is actually developing that Nile Level Synthesis to keep content shared. And so there is a little language in there called DSLX that's only used to describe hardware with a syntax that's close to Rust. And so it's really approachable for someone who can be lacking from software because they can try to convert that algorithm that they want to accelerate into that language and generate some very good algorithms. So once you have your X file and you can convert it to very good, you can read the whole tool for doing synthesis that's called USIS. So it's a tool that we mentioned this morning that's also very well used inside the PJ world to do synthesis to map to an FPGF. Here you do the same operation that you map it to the actual pedicure that you want to use. So I will use USIS to make sure that to convert my design into a series of get net list that targets the process that I want to write. So in that case today, I'm going to show you more on how we target the Sky 1.30 process. Then there is a press and hold tool which you have a list of components that represent your design and want to map them on the silicon die so that it fits within that die and so that the gate are closer, close enough to each other to meet the timing that you want to do. So the open hold that does this place in operation. And then the last test is that you want to stream to generate a file that you can actually send to the program. And that file format is called GDS so this will detect the design data from open hold and that will generate a series of basically polygon and rectangle work that you can actually submit to the program. And for that there is two tools that we use called magic and periods. So at first, like two years ago, it was very difficult to install all of those tools. If we've made a lot of progress into packaging those tools that are readily available in two environments like Kodak. So like if today you run that inside a good environment you can get to pick an open hold tool that contains like a dependent hold tool for instance GDS streaming and not go XLS to go IOS. And there is also like a one other barrier for people to be able to share their design with each other. Like you might be, you know how to run the tool you know how to run that inside a correct order you might have a pretty picture of your from your chip that you maybe want to share with someone else. And there was nothing really that was tying all of that together. So we started using like Jupyter Mabu to do that because it's very convenient you have like a series of texts that you can put to this command that people need to execute instead of just being a really that people that could be people that could be that could snippets inside the terminal that's actually something that you can use again. And you can also use some trusting visualization about your chip which works. And so that's like what I want to do now today. And there is this project like on the multi-payment suite board where we store a lot of the books that I'm using in the solution. And I want to show how we do that. If you want to follow along if you open that URL and play with and then do it yourself, I will go briefly through one and then show how to all that work. Another aspect is that it's like you don't have to install anything on your computer if you want to do that if you're using a notebook or state service like Cora. So we're going to also have a notebook or state service called Collaboratory where we start the machine in the cloud to physically run the code that's inside the notebook. Is there a call-up link or something? Do you have a call-up link? Do you have this notebook or something? Yeah, so that's what's on the URL that I mentioned here. So if you go to that URL Ah, the URL that I just... So yeah, if you go to that URL here you would find like a series of notebooks that you cannot bring from the link. The actual one that I'm going to use today is that one. And so that's like a notebook that we used. It's too small. So that's a notebook that we use for when you go shopping in Tokyo, in the US to Tokyo, to get actually CS students that know nothing about our design, but familiar with the design and familiar with the tool that you can use. So the first thing that it does and that you need to do is to create this cell to install like the backup dimension. And after that, there is a small introduction text about HS. So HS is basically this high-level synthesis of the dimension before when you can like describe your information that you want to accelerate in either the source or the set, which is the source. It really works like a compiler. You could have like an intermediate presentation which will allow you to run some interpreters and some tests. So as a software engineer, we will write a tool because you will be able to validate your design by writing like our unit test. And then you can run a series of team musicians and finally like spit out like the video that you can cut through the rest of the session. So the design that we are going to do today is like very simple. It's going to be like a shape of the language I can write a function. It takes two arguments, one will be that are all like one, that are both like one bit what. So you want it to return another value which is a unit. So if you can go through and have a carry, so I need two bits to start. And I really describe my operation like I would describe this as the saying that the result is equal to a person. And because I want my, this function to be the core of my design but I want to wrap that into an actual chip. And so I could have decided that I'm going to use a chip that has eight inputs and eight outputs. So it has eight pin in and eight bit out. So I need to decide which pin I want to send to this other and which pin I want to send as a output. And because it's like code I can write a unit test. So I can verify that I can be working. So if I press here I can write, I can see that the test is working. So now that I have like this description I can run like the toolchain to convert to this alternative language called XLSIO. So here I see like a more a view of the lower of that operation that I will have to perform inside the operation. And then I can generate a query output using the same toolchain. It's a bit silly because that design is so simple but it's actually very similar to the way you would write that thing. You would just write a code. I want to activate the user specification. And then once we have that query output we can connect it to the rest of the open source system so I can text my query log, run it through the synthesis tool, run it through forward planning, it's all the way to GS streaming and get a file that I can send to the company. So I need to specify like what is the name of my project what is the variable file I want to use if I need a clock I need to specify the frequency on my shop and I also need to specify more physical constraints like how big would be my chip. So here it's going to be 50 mp and how perhaps I want a gate on my chip together. So here I see I want 30% density. I also need to decide things like where do I want my pin so here I'm seeing I want the IO pin on the left and the pin on the right and you notice that the IO pin here on the out actually corresponds to what I used inside my code. And once you do this you can run the first operation which is in this which will basically convert like for that query log over your description of the design that you want to do. That's all this I'm just using into the actual gate that I'm using to get at the multiple targets which is this kind of process. So once we run that flow now we get like a representation of this QMT it's got the gate and the month operation and how they are connected together and so here you see that for adding two numbers I need to get I need to absorb gates for computing the global and then get to compare the most efficient. And so I can see that those gates are where they are getting the wire from from the input. I can see how they are combining the wire and I can see how they are showing it too. The next step is to do floor planning so now I need to take those gates and put them somewhere I need to kind of compare the place for putting those gates on my chip. So after I run the floor planning I should attack like this an actual chip that does the dimension that I want you can see here I have the input pin this is the agent input pin the agent input pin I have the program that you can see the two gates are still here in the bottom there are no gaps but I didn't do it because I didn't do passing out so here you can see that there are gates here and the organ over there. I need to do displacement so now we are going to take those two gates and we are going to try to place them somewhere where there is space on our chip it's not very hard because no chip is on chip that's all so let me land up somewhere in the wheel so here we can see there are the two gates here we can look at the higher level and so the last step is the routing so we need to actually connect the pin of this gate together so that they are actually electrically connected like the necklace that we have at the beginning and so at the end of routing we get something like that so here you can see we have the two gates you can see that there is a wire that comes from the input that goes into the first stop gate the wire that goes from the input the second input there goes inside my gate then this gate is connected to the gate there and the input of the gate connects to the gate so now we have the physical representation using the process that I want to target to implement the circuit that we have and the next step is to stream the GGS and then you get a fully complete layout that you can submit to the form-reference application and a series of metrics and you get to check if this design, the way the polygons are mapped together, actually conform to the constraint that the file has for manufacturing matching so there is a series of forms that need to follow following that and so that was a bit of a toy design it's just something that we can also do more complicated designs like here for example we can easily turn this halo into something that we can try to remember but if we run that we can get the very log there and if we do the synthesis we're going to see that the application is not as trivial as the project and that I need a lot of gates to actually implement this application since you're going to have to fit on the screen and we're going to see that when we run the application flow you can see here I'm going to run the flow and try to put that inside the chip that I am and we see it fail and the reason we tell you that there is not enough space with all these gates on that chip so for it not to fail we're going to make the chip even bigger and now I can see the reports and I'm asking how many gates there were and so there is 69 gates and here we have a breakout of what we are actually using to do that so when we write the code we just write one shell at a time and we don't really relate it actually to the internet where it's a lot of circuitry so we have 7 gates that 7 nodes that 2 nodes 7 cores and that's 8 bit by 8 bit 4 bit type and if we take a look at the chip it's kind of look like this so you see that the 2 nodes have to do a lot of work there to actually get all these gates and we actually didn't have enough a single space to do that so if you want to fill and we do this tutorial at home it's all that inside that we know the dimension and then we do a few more towards the end where we actually go through the step of programming that design so making sure that we can execute this multiplication into multiple cycles to try to reduce like the seems to improve the output of both then and so let me try to continue and tell you how I think that book are also useful for so we've seen here they are useful for designing I can run a tutorial workshop I can share a design with you I can use my chip and run your computer get a pretty picture but it's also very useful for research and so like inside the VLSI field there is actually a problem for reproducible research like when someone publish a paper at a conference I'm seeing like a breakthrough into a computer architecture that usually what they submit to the conference is here and there is a little table in there that say oh on this process you need this property to like those results and the table is the only thing that we invented the result and it compare like the research order project that may mean an order project to mean submitting the property at this conference and there is actually no way that you can compare the things together because I'm not using the processing you cannot run the same thing to reproduce it yourself and so like you can also be a useful thing for that instead of submitting a pdf that's static that just presents your result you can actually submit a recipe that people can reproduce it might target an order process so it will have like the same performance as like a state of the art thing but it could help people like build on top of the research and also help people to collaborate together and so like the IEEE society at least started with something that I think is a great initiative so they are based on the same tools and they basically invite any student or any university to submit that book to get it in by hand to their conference and usually those are like confirmed but you can't really get in if you are another because it's like two procedures to get in and that's an easy way to actually to get inside of this and to get familiar with the construction and they put like 14 projects just a minute last week for the coming days I think that was like great and like the other thing that the book are great for is for doing experiment and visualization and actually like if you can analyze your own book you can run like the same recipe that I was bringing here with a fixed size I can try to run the same book with many many different sites and analyze for example things like the power consumption and here it's the experiment I did on Google Cloud where I run tens of a job like I've just shown you with different size and different density for a much more complicated design like the RIS 5 core and I analyzed like the power consumption on each of those designs for assimilation and here you can see each of those dots is like one of the jobs that we run together there and like the the Google of the dot is like the RIS 5 function and you can see here there is like a kind of a nice sweet spot there between the density and the area where I consume the less energy and it is something that's very well known inside the field if you have a 10 or maybe 30 years of experience you know that if you have an area and density like you know that consuming less but for me that's like new to the field or for anyone that they can start using the struggle source and start occurring in the future without spending 20 years just by consuming like a lot of resources and like in order to fabricate this design we run like a program like during 2 years that allow people to submit designs that have been created using this open source tool and to get them manufactured as long as the design is open so Google has been running those shutters like for 2 years and we've run 9 of them and we've seen an increase in number of engagement since here at the very beginning we were getting only 3 projects now we are getting as much as for the projects we did to the last shutters and like people are submitting from all over the world and like currently we are busy trying to bring up the design for the second month and so people go back to their city hall I have an example here of one of the chip and like they are trying to run like validation to make sure that the chip is working so we are like we back into some issue with the tool chain we back into some issue for some of the parts that we are coming by before inside the city hall that was like some time impulation that people needed to work on but the community can look at together and it should produce a right characterization logic to bring it to work on the chip and we've seen like the result of people that are getting working sequence one example that I wanted to show you is like actually this chip out there which I think is very interesting so here you see themselves with 40 chip that got submitted to the shutout so each of them is like one of the source design inside of this one you can see that there is like many other elsewhere it's actually a design from non-line course to someone run a non-line course for designing chip in one of the space there and like putting 16 designers inside of it and so as part of the curriculum of that course you have to produce a design and then at the end of that course you will manufacture the design on that shutout and that person has like no interaction with Google they need like totally that on top of the infrastructure that they want to run and I actually got like a copy of that chip that's like here and so it's the one that's inside the corner here it's a very trivial design and so it's just the history of the design and Google is actually connecting on a digital cycle but I wanted to verify that this chip is actually working and so I could run like a bring up segment that left the designer on my computer it was difficult for me to share the results so I ended up creating like another notebook that's all we need to do that so it kind of goes through the setup and the configuration of the IEO that actually work and I can show you each file has some firmware that we initialize the IEO so I actually registered a list of chips from the chip that we have here that's here for the IEO and connecting to the logic that the designer is putting together so I configure the IEO pin there and I start the design and after I'm done with that I'm going to go to a board that's underneath here so you see that the chip that you have and underneath here is a little like a nuclear board and on this there is actually a micro-byte that's right so I could write some Python logic that will try to read the pin of the design and verify that the IEO is right so here I'm connected to one of the pins that represent the clock of that chip and you can see on every iteration a clocking the device so I'm just turning the clock from 0 to 1 and so that will step through the logic of the chip to get the clock and execute that very well and we put the next function number and on each clock cycle I'm reading all the GPIO and putting them back inside the number so you can see here all the number that I was able to read and then I can execute some Python on my computer to actually like, take these files that I got on the device and put them into the Pondata file that I can read so that Python is great to read and then I can on the local computer I do the real Fibonacci thing and like try to see if the result power is same it kind of looks similar and then I can try to visualize and see for each of the bits of my design of each of the IEO and so that's one example of how you can create a booting up sequence that everybody can reproduce and you know when you manufacture something called control just ship by echo some of them just ship out somewhere I think by the way though I might get not a scenario and I got that actually another chip that I got there, I re-run the same thing and you see here goes a lot and there is some of the things that I'm attaching so that's like, if you see something that's convenient so I can get that one, three test them and like I got this little sheet, they are taking the chip and I run it and I'm written down and they work on it and so yeah that's what I want to show I invite you to join like the community, we have a slide continue with that number there is this portal that we put together they have a product that comes in a sheet and there is actually an opportunity to take out this month with a project called technique about so they take out one slot of a similar shuttle, but instead of putting one project in, it's a 200 project and so they are able to bring down the cost of this shuttle really dusty, so you can get the design there for only $5 and if you want to actually get a chip for that's actually the 200 project you can just pay it one you have to pay $100 but you can't get that cheap and so yeah that's not something that we can just try to do now but it's just that we put the initiative inside of the material we're going to find out and later today there is a talk from Shen Cross that we use our institution and we did a lot of experimentation which we try to integrate ourselves using this open source tool and so yeah thank you questions? I'm sure there is the question is about the high level of construction I assume that that same structure can be used because it's really pretty high yeah it's pretty high and one interesting characteristic of it is that it has this intermediate languages that can be cheated and so you can execute on your computer, like native code that you can understand so for like very fast simulation that's actually pretty good any more questions? yes so if we talk about like a supplementary way to program the chips it's similar to how we did it no I didn't have any programming there so there is like multiple layers so the lowest level that you design you can actually design your own CPU and put it on that chip it's like a kind of code like your own firmware that get executed on that custom instance the architecture that you design the code is comparable specifically for that chip so like on there is a niche to go back to that one so yeah so you can see here that's like one of the chips that helps me deal with the shuttle like underneath here is like a management that comes on every single project there is a little RISC file on every single project that will allow you to kind of verify that your design is working so that's like something where you can put your own firmware and that's your programming you have a flash at firmware and it get executed on that chip and then there is like your custom logic here which is connected like a source that is a pin to that RISC file and so from your RISC file firmware you can actually send some value of your custom design and verify and there are cases for example like this project where they ended up implementing like a RISC file CPU inside the user area so you have like the little RISC file CPU here that we provide that's here for the diagnostic but the user design itself is also a RISC file CPU that they have in some firmware and that one is even more fun because like using the SkyWare of the process they are able to implement an FPGA and so like they actually design the fabric for the FPGA where you can like flash a bit stream that's done using the open source tool and then from the little RISC file that's over there you can hold the FPGA like the RISC file and actually do what the bits are doing and so they run some pretty interesting things around that FPGA so there is really like multiple layer where you could program that thing you could have that designing and it's even there it's a lot of programming because you can describe it with this in fact that's close to code but there is also like the thing that you run on the thing that you design which is another way of programming Alright, any more questions? Otherwise we have to wrap up Okay, thank you very much Iran