 So, welcome to this lecture on digital system design with PLDs and FPGA. In the last lecture we have seen a case study what we have seen is and we have seen the design of an 8 bit unsigned integer multiplier. I said you can extend that design. So, we have seen the algorithm, we have modified the basic algorithm, we have seen resources, we have seen the data path design at the top level, then each block we have expanded. And we have also parallely seen the VHDL code for it. We have designed the state diagram, then we have put together everything together in a VHDL code and some kind of you know concise way of writing the VHDL code and all that. Today and that has you know kind of winding up everything in the course you can extend that. And today I want to show you the FPGA tool and the same exercise on FPGA kit or FPGA board on a Spartan 6 board. But at the beginning I will show you the Xilinx ICE or ISC integrated you know system environment where we can do everything. You know we can do synthesis, bison route simulation, the programming of the FPGA timing simulation, timing analysis all that. I want to straight away go to the tool and show you with some simple example one combinational and one sequential. Then we will go to the real design wherein I will not simulate it because it is cumbersome to simulate it. I will just show you the program on the board. So let us go to this particular tool. So when you take when you install this program on the computer and you will have some you know the Xilinx ICE design suite 14.7 click on it. It is available in the program menu also maybe I will minimize it a bit ok. So that you can see it little bit full screen ok. I will make it resize it so that it is visible ok. So this is the tool and the latest tool from the Xilinx is called the Vivado which is only used for the 7 series, vertex 7 series devices. Since we are using some older devices we will use this particular Xilinx ICE and see this is the area where all the files and the related process will be shown. This is the area where all the opened you know files, waveforms, statistics everything will be shown and this area is a console where all the messages you know the process messages, errors, warning everything comes ok. So first thing is to start a project ok. Every problem is associated with a project. So we will open a project say new project. So let us you choose a directory to put that and I will choose some predefined directory. Say let us take a very simple example the equality comparator we have developed. So let us call it eq comp this was the first exercise we have looked at the VHDL. So this is the name, this is the location and all that and you say next and here very important is to choose the device family, device name and the package. You know that you have to choose very properly and this is the synthesis tool, simulator, what is the preferred language and all that and all that can be chosen you say next and you say finish. Now you can see that this is the project area where all the files will be shown. Now depending on what you choose here what all you can do the processes will be shown here ok. So first thing is to create a VHDL program and there are two ways of doing it. If you already have it you can right click and add source or you can create one say let us create one you know let a simple one let us create. Say new source and it opens up a menu for you and there are different files you can create like test bench, VHDL design, verilog design and all that. So let us take the VHDL module give a name and this is the directory give a name for the project. Let us call it eq.com again ok and say that is the file name of the VHDL ok we say add to project should be ticked we say next and now this gives a template instead of creating your file from you know from the beginning you can create it with a template. So it is already giving the entity name as eq.com architecture name as behavioral and it allows you to kind of generate ports. So let us call this port as a ok and that is a bus which is you know if you remember this is a 3 down to 0 ok it is 3 down to 0. Similarly we create a B which is input mode and this is also a 3 down to 0 ok. So and we have an output which is called let us call eq which is you select it is an out and it is a single bit. So do not do anything that is it and you set finish. See now you see that it has created for you a template code library and the use declaration the entity with all the ports a, b is a 4 bit vectors input port equal is out architecture is written here with a begin just write here the code you know say eq get shift 1 when a equal to b ok else 0 ok. So that is how ok that is a code ok so that is what is written here ok and now maybe I hope you can see that I have zoomed in if this is visible ok. So I hope you can see that now. So this is you see the entity architecture we say eq which is a output port gets 1 when a equal to b maybe you can give some space for readability. Now you say save ok it is saved. Now you select that the file now you see we have 2 option one is implementation one is simulation when you do implementation it will show the synthesis place and route all that you know the programming and all that. So here you see the moment I have selected that you know there are various you know you can specify the constraint you can synthesize you can implement and all that. Let us click open the synthesize and if you right click on it then there are lot of properties which you can go through there are synthesis option, HDL option, siling specific option. So there are lot of options you have you can choose it whether you can optimize for area, optimize for speed or you can kind of certain inferences like automatically whether the maxes are to be inferred all that can be chosen. Now the first thing to do is that you have to check the syntax ok. So let us introduce an error saying like this you know I will write like this double equal and I will save it and I say check so you can see that already it is flagging an error here which say that a syntax error near equal and I just click on the light and it shows what is the place where it is error. So I just delete that and save it and it automatically checks and it say that it is the parsing is completed. So if you want to double check you can say check syntax use a run so it takes a while to do that and it will show a lot of messages here ok. Now at that after checking the syntax when it is completed it is plus sign you can give a run for synthesize. So it will synthesize the following code ok that is what it is going to do and while it is doing it will show messages here. It is already showing a delay of 6.5 nanoseconds. So while synthesizing itself it knows that what are the resources used in FPGA so it estimate the delay and show it here ok. So here what you can do is that you can say in the process say if you click the sigma it shows the design summary ok. So it shows that number of lookup table used are 2 and the number of IO pins used are 9 because we have a 4 bit equality comparator there will be 2 lookup tables used we will see that and the number of pins because there are 2, 4 inputs and 1 bit output ok. So that makes it 9 and one way of seeing what is synthesized is viewing this RTL schematic. So if you click it you say start with the top level block you can say ok and that is the schematic of the what is inferred and you can just so it is detected as a comparator. So it is showing say A3 down to 0, B3 down to 0 it is an equal operator and the equal comes out because it is recognized so it is showing as a block ok. So another thing is that you can check the technology schematic wherein it will show how it is implemented within FPGA ok. So you go here and you say zoom to the thing and now you can see that these all are input buffers like A this is the signal like let me see what is the signal there that is A and this is B. So there are this is A is buffered and given to a lookup table B is buffered and given to a lookup table we can zoom in on that you know you can just so this is the lookup table which is going and you can click on that and you see you can see the internal the circuitry. And if you see the equation it will be a kind of XOR which is comparison and you can see the truth table say when it is you see it is 1 when it is you know when some pattern is there you can analyze that it depends and shows the kernel map of the optimization all that detail can be seen it is very useful learning exercise also. So once you have done that you know you have done the synthesis they can then you can go for implement the design so you just say run. So it will do something called translate map and the place and route ok. So it takes a while lot of things are done and that messages come here in the console and mind you this the utilization everything is updated in a quite a lot. So you can watch that what is going on here. So it is done now all that is done and you can see very elaborate statistics are written here. So there is nothing much because it is a simple design say registers 0 there we are not using any flip flop lookup table is 2 all that you know there is nothing much other than that is available here. A lot of resources none of like PLL DSP blogs nothing is used we have very simple example and I have chosen a ok this is a Spartan 6 device which I have chosen maybe I can change it to maybe Spartan 3 ok that because say I will change it to Spartan 3 let me see Spartan 3e because that is similar to the vertex we have discussed in the class so that we get some when we see inside we will have some familiarity with the lookup table and all that. So I have chosen now the Spartan 3e which is similar to the vertex we have learned in the class. So earlier what was default was Spartan 6 so I have changed it so that we can when we see the resources when we see look into the router design we become kind of you are comfortable ok that is done the first thing to do is that we can open this place and route and let us go and see the static timing analysis ok this shows the analyze post place route static timing. So click on it and you can see this one ok maybe I will magnify it so you can see that it is reporting the delay say source pad it is a pad to pad it is a combinational circuit so input pad to output pad so A02 equal it is 6.476 nanosecond similarly A1, A2, A3, B0, B1, B2, B3 all the paths are chosen I mean shown and the maximum delay reported here is 6.98 nanosecond which is somewhat similar to what is reported during the synthesis so that is quite correct. Another useful thing you can do is that you can look at the router design within the FPGA. So you click this particular menu view edit router design so if you click that ok this window shows the whole FPGA ok this is the whole FPGA with the IO pins around all the slices and the DSP blogs the memory everything you know special resources so you see some gaps and all that ok that is that so and it shows you know where are the where are the signals suppose I click on that it shows where is that IO pad is coming ok so you click on that that is the picture of the IO block of this particular device and which is ok so that shows IO block ok and one can zoom where is zoom ok so this one shows that IO block ok this is the pad these are the buffers and all that you know input it is an input so it input is coming. And now sorry I will open that again ok let us look at this particular so there are two slices used so let me click on that so you can see that this is the look table used there are say this particular slice is used because we need two lookup table and this is a slice used so you click on that and now you can see that particular picture we have seen the detail view of the slice so you see here so this is the one lookup table which is used you can see let us magnify it so you see B3 and A3 A2 and B2 are going. So this is a comparison of A2 B2 A3 B3 and you know combining them two so this is this implements say A3 XOR B3 A2 XOR or A3 XNOR B3 and A2 XNOR B2 so that is the logic implemented here in this particular thing similarly you can you know so this shows you know the various the architecture of the slice and if you remember if you care to remember these are the two lookup table two flip flops this is the carry chain so all that can be kind of you know looked at and you can clear your doubt it is very useful it is not only designing you can see very detailed picture of what is going on within FPGA. So let us now do a simulation okay now for simulation you can write a create a test bench as I have shown earlier like maybe you can say a new source okay and you can select a VHDL test bench okay and you say give some name say let us call it EQTB test bench it will show which is the entity to be assigned so it is showing EQCOM because there is only one entity there are multiple entity architecture you have to choose whichever one you are trying to simulate mostly the top level component say next say finish okay. Now what good thing is that again this tool will create a template code for you that I will magnify it okay so that is the library function this is the empty entity this is the equality comparator instantiated these are the sorry declared signal declaration this is the kind of instantiation. So it involves a clock which we will command it which we do not require so this is a clock process again this is not required so we will command it okay and there is a wait for clock period that also we will command it and here we can insert the stimulus okay. So I will just show a very simple thing A gets a say 0, 0, 1, 0 okay now both are 0 at the beginning and I will say wait for some time okay I will say wait for wait for 50 nanosecond and I will change maybe A back to 0 again so that you get equality okay and so on okay you can give delay sorry that has not come what happened okay fine okay. So just save it now the test bench is ready now what we do is that you have to select the simulation select this test bench and you see now you see this is the simulator isim simulator click open do a syntax tech okay. Now you can right click on the simulate behavioral you can see there are a lot of properties it in the default it runs only for 1000 nanosecond you can extend it if you want but our thing it is okay and also most simulation will have a whole state for 100 nanosecond to simulate the FPGA programming time so you should assign only the input signal after a 100 nanosecond delay. So now you click simulate behavioral model so it shows a window waveform window so that you can click open and you can zoom to this thing and you can see this you can select the radix as a unsigned decimal. So initially both were 00 and you can we can zoom in okay let us zoom in say here both inputs were 0 so the equality output was 1 that we made something for 2 the one of the input as 2 then the equality goes low then again we made it 0 it goes up okay. And this is a marker which shows the timing suppose you want to latch this on to the to this edge you click on this it latches you want to insert another marker say you say markers and add marker so you get another marker and you can move that any number of marker and it shows the you can measure the time in between and you can choose lot of things I think you can play with it that is what is this symbol combinational circuit I want to stop here. So let me close this and I will show you a sequential circuit a symbol counter which again we have discussed in the class what we have done was a 8-bit counter with a synchronous load okay when the load signal is high it gets loaded with some value so I just want to bring that thing and show you that okay. So let me close this project I close this project and I will open a new project okay again I will call it count okay same thing spot in 3 it remembers that will be in your profile and we say finish now what I am going to do is I am not going to create a file I just add the source so I will add the source which I have it ready so say which is a count 8 which I opened so this is the file you know I will magnify it okay. So this is the library 11 package 1164 and unsigned this is the input clock reset load is input D in is the data input which is 8-bit count is output which is 8-bit so we have a Q because we have to use Q is Q plus 1 count is assigned with the Q this is a process where the counter is there if reset is 1 Q is others 0 else if clock event clock is equal to 1 then we introduce a synchronous load if load is 1 Q gets D in else Q gets Q plus 1 okay I have shown you everything this particular thing how it is in the size you refer back to the earlier lectures you get the picture okay. So I just want to show you synthesize so I want to synthesize this so I run that so that shows an quite a bit now this will have you see a sequential timing so register to register delay it will show all that let us look at the technology RTL schematic and okay now this has identified as a counter so it is not showing so it is inferred the counter maybe we can look at the technology schematic so that shows the whole scenario. So there are a lot of lookup tables because you know that we have when we learned FPGA we have said that an 8-bit counter will occupy 8 lookup the carry chain and this is a lookup table if you look at let us magnify that okay. So okay so this is the lookup table for this is for D in 0 so this is the lookup table for Q0 and this is a flip flop for the 0th bit and also you will have this is the XOR combining with the carry outside XOR and if you look at you will see the carry chain mux and all that okay here okay. So there will be this is for the 5th bit this is for the 6th bit and if you can find it all over you know this is for the 0th bit so all that is shown here and if you click on this lookup table it shows the truth table with that addition okay this is shown here so you can analyse that so I will not spend time with this now we can implement it okay. So now it is doing the place and route initially it does some process called map and translate map and now it is doing the static timing analysis and you can see the summary and you see there are number of flip flops used are 8 okay and number of lookup tables used are 8 and you know that there will be carry chain used so 8 lookup table 8 flip flop and it occupies 4 slices what I want to show is static timing analysis. So let us look at the static timing analysis okay now here you see there are various different things which I think is of some importance so first thing is called setup and hold to the clock okay. So this shows the data input and the load signal it shows what is the setup and hold time of each of the external input up to the flip flop because data in is going through some kind of combinational logic to the flip flop and it shows that the data in 0 as a setup time with respect to the pad 1.469 second and the hold time is 0.8 nanosecond. Similarly there is a clock to pad which we have discussed this shows that given the counter output it is like equal to Tcq but all the way up to a pin because the counter output is going to a pin so from the clock edge what is the delay all the way up to the pin not just at the output of the flip flop so that say count 0 is 7.2 nanosecond. Similarly this is a setup time of the input all the way with respect to the pin okay and this shows the clock to output with respect to the output pin okay. And the lastly what it shows is that it is the clock to setup that is nothing but a register to register delay so this shows the minimum clock period okay the minimum clock period is 2.97 nanosecond. So basically our counter will work with the 3 nanosecond clock period but you see the since it is placed within FPGA for the count out to come on the pin it takes 7 nanosecond okay. So even if you simulate at 3 nanosecond though the counter internally works properly the input will not reach in 3 nanosecond to the output so you will be forced to kind of simulate it at 7 nanosecond or run the design at 7 nanosecond or 8 nanosecond. Similarly setup time is not a big problem because it is only taking 1.5 nanosecond that can be setup you know the load as 2 nanosecond so still it is within the 3 clock period but there could be some all that combination delay is accommodated here. So this is something which you have to realize though the clock frequency can be high because of the delay to the pin you will be forced to choose the slowest of this as the clock period when you simulate it. But nevertheless that does not shows the your designs performance because many a times you are designing an IP where these outputs are not taken to a FPGA pin that is going to a nearby another circuit okay or you know for an advanced user this can be these pins can be assigned very close to the location where this logic is placed all that is possible. So in when you do the static timing analysis of sequential circuit you will have the setup time with respect to the pin which is called setup to clock and clock to pad tcq with respect to the clock and register to register delay okay. So I am not trying to since I have shown you the simulation I am not going to simulate that because we have to complete that our case study on this particular tool. So let us look at maybe you can you know you can look at the editor doubted design which you know say here you see you come down and you pick up a slice for the q0 then that slice come and you can see this is it and you can very clearly see the q0 coming here the q0 data in load which we have discussed how a single lookup table can accommodate the data in q0 and load you refer back to the class that is the lookup table and that is coming with the XOR gate and this is a carry chain wires maybe I will zoom out a bit to be able to see that so this is a carry input and this is the carry marks which is going to the next stage here to the lookup table okay. So this can be very well analyzed whatever I have shown in the earlier lectures that you can try it out and verify what I have shown is correct or your own ideas are correct. So at this point I will close this project and I will come back to the slides we have the case study we have done briefly to remind you. So what we have done was a multiplier and we had implemented you know the data path multiplicand result add a marks then a counter to keep track of the count controller then we have it expanded multiplicand register, multiplier register, counter the FSM and we have seen the state diagram and this was a code you know this was the big code and the multiplicand register multiplier, the multiplexer, higher product register, counter, decoder then the next side logic and output logic of FSM adder and the FSM flip flop that was a code okay. Now what I am going to do is that I am going to program this in an FPGA okay. Now this is a state diagram okay. Now the particular FPGA board I am going to use is this particular Xilinx okay sorry for this mistake it is X okay Xilinx Spartan 6 at least board and this board as a Spartan 6 FPGA which is 6x Lx45 which the package is CST 324 pin you know the board grid chip scale you know the grid. That means there is concentric squares beneath the chip with the pin and it has lot of things you know it is a very powerful board you have a clock we require everything something clock. You have some LEDs connected to some pins you have some buttons so that we can give some reset start there are slide switches all that and there is Ethernet, memory, USB, HDMI, audio codec and all that. But essentially we are going to use the clock source because we are going to do something with the clock and because the state machine need the clock then the LEDs to display the multiplier output button to give a start to the multiplier we have discussed that what is a start, start comes from the external thing. So that is how the FPGA board looks this is where the FPGA is this is the FPGA and you see lot of ports this is the audio port, USBs, this is the Ethernet ports and this is a flash memory and maybe these are the the HDMI port, this is a program port these are the slide switches where you can give 1 and 0s and these are surface mount LEDs 8 LEDs okay and these are the buttons you know there is a reset button and 5 buttons like cross where you can give a push button okay. Now we have to show the result of the multiplier so what I am going to do is that I am going to give the multiplicand fixed okay so within the program I am going to assign hard assign the multiplicand and within the program upper 4 bits of the multiplier is assigned hard but the lower bits I am taking from the slide switches okay. So I can choose the lower bit say up to say 0000 all the 402 all the 4 ones okay 002 ff in hex okay that can be changed and see the result because we are implementing we have implemented an 8 by 8 multiplication which is 16 bit. So these are sorry these are once again there are 8 LEDs okay not the 7 LEDs 8 LEDs what we are going to do is that we are going to multiplex the 16 bit onto this LED with the 0.125 hertz that means say once in 4 seconds it will show the most significant byte then the least significant byte okay. So we are using there is a inbuilt clock oscillator which is 50 megahertz we will implement a clock divider okay and that will generate a 0.125 hertz and that is used to multiplex this LEDs and this 50 megahertz can be used for the state machine of the controller and one other thing I am going to do is that I want to give a start signal okay. So I can use a push button there is a push button on the board say these buttons okay. Now the problem with the push button is that when you press it it is it does not make a clean contact okay it just goes and bounds you know like that is a picture shown initially it is 0. So when you press it kind of goes up and down and make a 1 okay. Now we need to debounce okay we need to remove this glitches otherwise it will start many times okay. So what we do is that we will sample so what we are trying to do is that we will sample with a clock period which is which has a period which is higher than this burst okay. So we have to have some sense how long this burst can occur but for the most good switches it will occur say around 20 millisecond like that okay even less. So sometime it can very bad switches big switches can have more chatter but we assume that it is around 20 millisecond. So we sample at two points and if there is a 0 and 1 clean 1 then we will you know make it as a start. So that is what is done by this is a flip flop you see here the input is going and we are giving a 20 millisecond clock and I am tapping one of the cues of the clock divider with appropriate you know waveform it need not be very correct because this will kind of it is a mode counter after sometime it is going to become 0. So the waveform will be little bit distorted but does not matter not a very serious thing. So what we are going to do is we are shifting that to the output and the earlier one comes here the current one is here. So we are looking if it is 0 and that is 1 then we get a pulse here okay which is of the duration of the clock period because when it is 0 and 1 this is happening with every kind of so you get a pulse here that is used as a start and this pulse is kind of little big of the 20 millisecond duration if you want to make it narrow we can resynchronize it but this is this pulse is of 20 millisecond duration that could be a problem because if it is very long our multiplier will you know complete it and restart again because the multiplier works very fast and there are when you sample you know strain things can happen suppose one edge comes here and one edge is here. So if you are lucky it is both are 0 if it is this is 0 this is anyway 0 this is 1 we got a 0 1 transition it may happen that is very clean you know we sample here 0 and 1 then it is a clean thing may be that you know we you sample it here if it is 0 then this will catch 1 if it is 1 the previous one would have been 0 so that will catch it. So anyway it works this de-clitching work decently but only thing is that it duration is 20 millisecond maybe you can put another flip flop with a 50 megahertz clock to get an aero pulse that is possible I am not shown that. So I have done a little change to the to the state diagram I know that the start is going to be long so what I did is that when we come to the final stage I remain there till the start goes low and come back here. So that is how I take care just to demonstrate but in real design you better put one more flip flop here with the same fashion same circuit which is clocked by 50 megahertz and you will on the transition you will get a single pulse of 20 nanosecond duration that should be enough for our controller because the controller also work with the 50 megahertz clock and that is the additional the code required for multiplexing. So I have some start signal start signal debouncing clock like this particular clock I am naming as ST clock and you see this is the hard assignment MC is assigned A5 the ML most significant 4 bits are assigned 4 and this is the ML 3 round 0 which is coming from the input pin and this is a constant which is representing the 50 megahertz or 50 megahertz into 4 to generate 0.125 and you can see how that counter works the divider upon the reset that huge 27 down to 0 is made 0 upon the clock it is incremented but if it reaches this particular number it is reset and to make a square wave we make a d clock which is 0 at the terminal count it is kind of toggle not d clock. So you get a divide by 2 out of that you know that is the counter and this is the LED multiplexing. So we are using this d clock when it is 1 r7 down to 0 goes to the display and else r15 down to 0 goes to the display and this is the d count 15 is for debouncing and you see that debouncing here if reset is 1 that is dst is 0 upon the clock dst get so that is representing this flip flop and this AND gate is written here say start is nothing but st and not dst okay and that start goes to the state machine and I have told you about the state machine change. So let us go to the program okay and let us move it and let us come here and open this thing I will open a new project let us call it multiplication mult okay. Now it is very important that you select the correct device as it is on that board which is part 6 the correct package should be chosen then only it will work because the pin numbers change depending on the package xc6 as lx45 now this is a package cst324 I will say next finish now I will add the source file let me add it I go up I will pick it up from okay I will cancel it I will copy add copy of the source I will go here that is the VHD file open and done okay. So that is a huge file it is quite a bit huge so you can see the library package multiplier then the architecture with signal and this is the constant for the counter and this is the various multiplicand register, multiplier register, multiplexer, higher product register, counter then decoder this is a counter for multiplier adder this is a next aid logic and the output logic of FSM and this is the FSM flip flops this is a multiplexing counter LED multiplexing this is a LED multiplexing and this is the start pulse generator okay. So old thing is there and now very important thing now is that when we do this kind of thing you have to assign the pin because we are going to now you see put this program into FPGA. This FPGA some of the pins are connected one of the pin is connected to the clock some pins are connected to LED so your signal should be mapped correctly to this and there is a way of doing it graphically but there is also a way of doing it to the by a file called UCF file. So that file you know you can say you can go to user constraint and you can say IO pin planning pre synthesis you can click it and you can assign it manually and will create that UCF file. But for convenience I will I have prepared that UCF file so I will pick it up from what is pre-prepared okay. I will copy that UCF file here so and that if you see the UCF file this is the syntax I will maybe you see that it shows that net clock location is L15 that means the signal clock for us is connected to the pin L15 because on the board this particular clock oscillator is connected to the pin L15. So we are tapping that clock similarly you see display is mapped to some pins this is where the LEDs are connected similarly the multiplier input is connected to some pins that is where the slide switches program and the start coming from a button reset coming from a button. So this is very important now I am not going to simulate I am just straight away going to generate the programming file. So it will do synthesis, place and route programming I mean generate the programming file everything is done it might give you some warning but it does not matter because I have done some kind of assignment which is may not be most optimum. So that is doing the place and route the translate, synthesize, translate, map place and route all that okay and it will show the design summary it is using the 53 registers okay and the lookup table is 96 because it is quite a big design and we are using lot of counters you know counter huge counter to generate that debound multiplexing signal the counter 8 bit counters lot of registers. So it is 53 registers and 96 lookup table it is using so it is done complete the static timing analysis but I would not go through the other part like all that let us try to program that. So before that I just want to show you what I have assigned the inputs say come here you see the multiplier, multiplicand is assigned a 5 hex number multiplier higher bit is assigned 4 okay. Now I want to show you the board so this is the particular board okay. So this is what the picture I have shown so this is the FPGA with the heat sink this is the power supply these are the slight switch. So I will keep this 4 bit at 0 these are the LEDs okay. Now what I am going to do I am going to program it so let us go back to the tool okay. So let us come back to the software so how do you program is that you click this and open that thing and you say configure target device and you say manage configuration project you click on it and make sure that the board is switched on you connect the power the programming is done through a USB cable okay and make sure that this is powered on. Now come back to the tool okay and you see you click on this boundary scan okay it comes here now you say right click and say initialize chain. So it is detected the FPGA now it asks whether you want to assign a configuration file you say yes and it will open up the correct bit file in the project you click on it you say open. I will ask another question for flash prompt say no say okay now right click and you say program and you can see that it is programming the board. Now let us look at this particular program is succeeded when that happens you can see there is an LED which is a green LED which is called a done that LED is glowing okay this particular LED is glowing now. So now what I am going to do is that I am going to give a reset to it I am going to give a start okay. So now you can see that these LEDs are not lighted okay so I give a start pulse now you can see that LEDs are blinking which is A5 into 40 actually it is the real result is 2940. So maybe it is so small you cannot see from the camera but then it just shows the 2940 and if I can change the value say A5 and 4F and I give a start signal you can see these LEDs which is showing 32 and EB 32 is less lights and EB is more lights more lights now. So that is how you use the FPGA board by programming a lot more can be done I just want to show a quick kind of run through the tool. So we have seen today a simple combinational like thing we have seen the synthesis we have seen RTL schematic technology schematic static timing analysis inside the lookup table all that you know the all that detail we have seen as counter design a sequential design against static timing analysis. The whole case study we have with an additional some addition we have put the result on to the LED okay important thing to remember is that you have to do a PIN assignment and you can do something called a IO you have to do IO constraint maybe one thing which is reminding maybe come back to the tool you can do something called the timing constraints okay that I will quickly I will point out then you can play with it. So it is possible that you can specify the right timing. So here you see the create timing constraints and you can see that you can specify the clock period say the clock domains various clock the inputs outputs what is the setup time required what is the clock to output and you can group some pins and you can specify the setup time clock you know the period all that. So it is quite elaborate and when you do GUI this will be converted to the entries in the UCF file as timing constraint. So wherein you can achieve some timing performance you know you can say that your design should work at 5 nanosecond or 10 nanosecond or part of the design should work with 5 nanosecond another part by say 7 nanosecond all flexibilities are there that you can play with it but that is more to do the tool I suggest you go through a tutorial and get acquainted with that. So with this I am kind of completing the course I have covered you know the digital design very detailed how to design top down controller design issues then the VHDL for synthesis and the FPGA in detail how given a code how it maps to the RTL code how that really gets implemented within FPGA and we have wound up with a case study showing the tool showing it on FPGA board. So I hope that has been a good learning experience you can build on this you know I normally cover quite a lot in my course in the university I teach but I do not have time to cover all that and this was something committed at the beginning of the contract so I stuck to the syllabus. So please study well go through the material go through reference book work out lot of examples in the line I have suggested then you can master it you think you try to understand and then you can build on this basic which I have given I hope whoever as watching this watch this course will become an expert VLSI designer. So I wish you all the best and thank you.