 Hello and welcome to this presentation on the STM32 G4 High-Resolution Timer. It will cover the main features for managing the complex waveforms required for digital power conversion applications. The High-Resolution Timer essentially addresses digital power applications, such as switch mode power supplies that require high PWM switching frequencies. It allows the drastic improvement of the duty cycle resolution, typically for buck or boost converters. This results in a better output voltage resolution and regulation, and avoids the limit cycling issues which can happen with a regular resolution timer when the duty cycle accuracy is lower than the ADC accuracy. This also allows a finer frequency with phasing adjustments, which is a key parameter for resonant converters using LLC or full bridge phase shifted topologies. The table presents the differences between standard and high-resolution timer for a product running at 170 MHz for both the duty cycle and the frequency resolution. The high resolution is implemented using a delay locked loop, or DLL, which allows the division of the timer input clock period into 32 fractional steps. This DLL requires a calibration prior to the HR timer startup. It must be noticed that the DLL only operates between 100 and 170 MHz, yielding a resolution ranging from 312 picoseconds down to 184 picoseconds as the resolution is scaled with the input frequency. The high resolution is available for any kind of waveform adjustment, period, duty cycle, or PWM to PWM phase adjustment, but not for input capture, performed with the regular input clock from 100 to 170 MHz. Let's now have an overview of the HR timer architecture. Although we talk about a single HR timer, it is actually made up of 7 16-bit counters that can either be used independently or synchronized, each of them having an independent clock pre-scaler. It is equipped with a total of 28 compare and 12 capture units and can control up to 12 outputs. A large central crossbar unit allows the output pairs to be controlled not only by the related timing unit, for instance, timer A for output CHA1, but also by any external event, the other timing units, and or the master timer. A total of 32 set and reset events are available per output. The crossbar is followed by a versatile output management feature able to interface with any kind of gate driver, program the output polarity, the PWM idle and save state levels, insert a dead time, and or add a chopper modulation. A hardware burst mode controller facilitates the light load management with a built-in pulse skipping mechanism. It also features an ultra-fast and asynchronous fault protection feature independent from the system clock. The HR timer is able to handle 10 external events for dynamically modifying a waveform in addition to six fault cycles for protecting power stages. The 10 events can be selected among external ones on inputs and internal ones, typically from comparators. The events allow performance of output set and reset to reset the PWM counters or capture external timings. The fault signals are here to protect the power stages and shut down the PWM outputs. The HR timer is also linked with other timers as well as the DMA, ADC, and DAC peripherals via internal interconnections. Let's take a closer look at one of the high-resolution timers' five identical timing units. It is made of a 16-bit up-counter with a programmable overflow value to adjust the counting period. Four 16-bit compare units and two 16-bit capture units are linked to this counter, each with interrupt and DMA capability. A compare event is generated when the counter exactly matches the compare value. Several compare events can thus be generated during a single period to have the output set and reset multiple times per PWM cycle. The unit embeds all control features for a pair of outputs. It can eventually operate as an independent timer. Yet these outputs can also be controlled by other timers. The up counters can operate in three modes. In continuous mode, also called free-running mode, the counter rolls over to zero when it exceeds the value programmed in the period register or restarts counting if it is reset by an external event. This is the most common mode used for fixed frequency converters or for externally synchronized variable frequency converters. In single-shot mode, the counter is started by a reset event and it stops when it reaches the period value set in the HRTIM-PERXR register. Two options are available here. In non-retriggerable mode, the counter reset events are discarded if they occur before the end of the counting phase. Typically, this is to make sure an externally triggered pulse will always have the same pulse width. In retriggerable mode, the counter can be reset at any time. In this case, an externally triggered pulse may have an extended pulse width if it receives multiple triggers closely enough. Each timing unit includes a repetition counter similar to the ones available in standard STM32 timers. It allows offloading of the CPU by decoupling the switching frequency and the interrupt frequency. The counter rollover interrupt can be issued every single, second, third, and up to 256th PWM period. This feature is available both for continuous and single-shot modes. In this case, the repetition counter is decreased on each reset event. The crossbar combines the set and reset events to build the output waveforms, regardless of polarity programming. The events may come from the timing unit itself, from other timing units, from the master timer, or from external events. The timing unit contains two crossbar programming registers per output, one defining the set events, the other for reset events. Up to 32 events can be selected simultaneously. This allows building of periodical waveforms with multiple set and reset events per period. The programming registers are shadowed with preload registers so that the waveforms can be modified on the fly without any risk of having abnormal transient waveforms. In parallel with the compare units, each timer also embeds two capture units. The capture triggers the transfer from the current counter value into the capture register. This is useful for determining external timings and for the auto-delayed mode discussed on the next slide. Typically, it offers the possibility to measure the effective duty cycle in a cycle-by-cycle current-controlled converter where the PWM pulse is terminated when the current comparator trips. The capture triggers can be selected from among 28 sources. External events, adjacent timing events, adjacent output waveforms, as well as update and software events. It is possible to simultaneously enable several trigger sources. Half mode is a feature that allows reduction of computational burden when a variable frequency 50% duty cycle PWM waveform must be generated. This is typically the case for resonant converters where the operating frequency is continuously adjusted by the control loop while the duty cycle must be maintained at 50%. The half mode operating principle is to have a right access to the period register triggering a computation and an update of the Compare 1 register to half the value of the period. Let's consider a PWM signal set on the period event and reset on a Compare 1 match. As soon as a new period value is written into the period register, the Compare 1 value is also updated to the Period 2 value so that the output set event will still happen right in the middle of the PWM waveform. This is particularly useful for continuous mode fixed frequency operation, but it can be used in any other mode as long as the period register needs to be accessed. Auto-delayed mode offers the possibility to have set and reset timings referenced to external events and not only related to the internal time base. Still, a timeout mechanism can ensure a default waveform when the external event is not present or disappears. This HR timer computes a new compare value on the fly based on external event arrival time captured in a register as soon as the event arrives. The delay versus the expected event is programmed in the Compare register, but the Compare event is inhibited until the capture is triggered. When the timeout safety mechanism is enabled, the capture is forced when the counter equals the timeout threshold defined in the Compare 1 or the Compare 3 value. A new capture is possible once the auto-delayed event has happened or when a new period starts. This slide gives a practical use case of auto-delayed mode. The requirement is to build a waveform as follows. The output must be set on a Compare 1 match with a fixed timing versus the counter start value. Here, 2 clock cycles. The output must be reset 5 cycles after the external event falling edge. The output set occurs when the counter is equal to 2 and matches the HRTIM CMP1R register value. The HRTIM CMP2R register value is equal to 5 but is ignored until the external event falling edge occurs. The current counter value is 7. It is captured in the HRTIM CMP1R register and added to the HRTIM CMP2R preload value. This yields an effective Compare 2 value of 5 plus 7 equals 12. When the counter matches this Compare 2 value, the output reset event is finally generated. 5 cycles after the external event falling edge. The uncertainty of 0.5 cycle in the figure is the normal latency due to the capture signal resynchronization. The HRTIM CMP2R push-pull mode simplifies the management of push-pull and resonant converters. The two outputs of the timing unit are alternatively enabled and put in idle state to maintain the balance between the two PWM outputs. In this figure, two identical waveforms are programmed on output 1 and output 2. The push-pull circuitry disables the outputs every two cycles out of phase so that the signals can be built using a single compare value to set the PWM duty cycle. This is also possible without using the push-pull but it would be at the expense of two other compare registers and a larger CPU burden. Finally, it must be noted that it is possible to unbalance the signals and generate asymmetrical waveforms. For instance, a PWM using Compare 1 for output 1 and a PWM using Compare 2 for output 2. The HR timer counters can operate in up-down counting. This mode presents advantages for fixed switching frequency power converters and for motor control applications. The HR timer is able to control up to two three-phase brushless motors and three full bridge converters for driving steppers or DC motors. The up-down mode simplifies the ADC sampling implementation. At first, it allows a constant sampling period since the output pulses are symmetrical to the top of the counting pattern, also called crust of the counting. This is shown on the bottom part of the figure where we can see that the sampling frequency FS is constant from one cycle to the other while it is varying with the pulse width modulation using the up-only counting mode on the upper part. For many converters, the ideal ADC sampling point is in the middle of the output pulse to avoid any conversion error due to the ripple on the output current or voltage. This ADC triggering point positioning requires some calculation in up-counting mode. In up-down counting mode, this is not necessary as the ideal triggering point is always located on the crest, thus slightly reducing the ADC-related computational burden. The UDM bit enables the up-down mode. Most of the HR timer features are available in up-down mode at the exception of auto-delayed and balanced idle modes. The HR timer programming mostly differs with the crossbar programming. The events selected in the HRTIM SECXYR register are coding for both the output set during up-counting and the output reset during down-counting. This allows pulses centered in the counting period as shown on the figure for output 1. The events selected in the HRTIM SECXYR register are coding for both the output reset during up-counting and the output set during down-counting. This allows the creation of more complex waveforms as shown on the figure for output 2. A dead time can be inserted after the crossbar to generate quasi-complementary signals on the two outputs of a single reference, PWM. This allows safe driving of all topologies based on half bridges, including full bridges and three-phase inverters by inserting a dead time during which the two power switches are turned off. This avoids any problem of cross conduction and shoot-through. The dead time value can be individually adjusted for both the rising and falling edges, asymmetrically, to handle any kind of driver or propagation delay. For very specific cases, it is even possible to program a negative dead time and have some controlled outputs overlap. The dead time registers are pre-loaded so that the timings can be adapted in real time without any risk of spurious transitions. This is typically used for adaptive control to optimize the converter efficiency. Last, for functional safety purposes, it is optionally possible to write protect the values or the signs of the dead time with specific control bits. The master timer comes with the five timing units using the same architecture. Its programming is simplified since there are no directly associated outputs nor captures auto-delayed mode or external events management. The master timer primarily aims at synchronizing the five timing units for converters requiring more than two outputs. The six events from the master, period, compare one to four, and the global synchronization are available on all timing units and can be used to set or reset the outputs or reset the timers. The master timer also holds the counter-enabled bits from all timing units. This allows a synchronized start of all timers with a single write access. Last, it embeds the off-chip synchronization logic programming for interfacing with other HR timer instances in case of multiple MCU systems. External events play a key role in the HR timer. They dynamically modify the waveforms typically to implement a cycle-by-cycle current control or to restart the counter following a zero current detection. A set of 10 external events which can be chosen from among 30 on-chip or off-chip sources are used to set, reset, or toggle the outputs, reset the counters, and trigger multiple features such as the burst mode controller, the capture, and auto-delayed compare, the ADC start of conversion, or some protections. The 10 external events are available for all timing units while the conditioning, typically the edge sensitivity, is done globally event per event. A different event filtering scheme can be applied to each timer. The external event conditioning circuitry is a preliminary signal detection stage which is configured depending on the type of external interface or on the amount of noise and glitches present in the incoming signals. The first stage is a four-to-one multiplexer to select the source, usually an input pin or a built-in comparator. It is followed by the definition of the edge or level sensitivity. It must be noted that when the level sensitive option is chosen, the external events are continuously issued as long as the level is active. Last, a programmable digital filter stage allows removal of spurious transitions at the cost of a higher response latency due to the filter propagation delay. This feature is available for external events 6 to 10 only. In many cases, an active event coming out of the conditioning stage is not necessarily a valid event. This is typically the case for current feedbacks. The freewheeling diode's recovery current might be a source of spurious overcurrent detection. It is therefore necessary to apply a specific filtering scheme to the external events used in a given timing unit. Three filtering options are proposed. The blanking mode consists of masking the external events during a defined time window, defined within the timing unit itself or using the other timing units. This is typically the case for leading edge blanking. The windowing mode lets the external events go through only during a specified period of time, again defined within the timing unit itself or using the other timing units. An event postpone mode allows an event to be acknowledged and latched only if it occurs during a given time period and delayed to the end of this period. It is also possible to filter out events based on the number of occurrences. This is typically the case for valley skipping mode in flyback converters. A new period must be started only after a given number of oscillations or valleys. In this case, the external event counter allows the event to be taken into account only after a programmable number of occurrences from 1 to 32. Each timer unit has its own external event counter, which can be applied to any of the 10 available external events. Additionally, the external event counter has two operating modes. In the immediate mode, the event is generated as soon as n consecutive external events have occurred within a period. The event counter is reset at the end of the current PWM period. This mode can be used for implementing valley skipping, for instance. In the cumulative mode, the external event counter is not reset at the end of the period, but only if there's no event during a period. The event will be generated only if it has occurred during multiple consecutive periods, as shown on the right side of the figure after three rising edges on the EEV input. On the contrary, on the left side of the figure, the external event counter is reset after the third period, since there have been only two consecutive events without a third one. Each of the 10 HR timer outputs have three configuration bits. The output is enabled using the OEN bit and disabled using the ODIS bits. All bits are grouped in a single register to have the possibility to enable and disable multiple outputs in a single right access. A disable status bit ODIS indicates if the output was disabled because of a fault detection. The bottom figure is an overview of the whole output stage for a given timing unit. Following the set-reset crossbar, Output 1 and Output 2 reference signals can first be altered with the push-pull and dead-time insertion unit. In push-pull mode, Output 1 and Output 2 are alternatively in run or idle state. When dead-time is inserted, the Output 1 signal serves as a reference to build the quasi-complementary signals and the Output 2 signal is discarded. The burst mode controller allows both outputs to be automatically disabled and re-enabled for a limited period of time. The chopper unit can superimpose the carrier signal on top of the active PWM waveform. Finally, the fault stage can completely disable the output to protect the power switches. The polarity is programmed at the end. The entire HR-timer waveform can be programmed by just reasoning in terms of active-inactive switches, independently from the external gate driver and or interface sensitivity before the polarity is applied. The chopper unit superimposes a programmable carrier waveform on top of the active PWM signal. A carrier generator is started by the incoming pulse and added to the incoming signal by means of an AND gate. This allows interfacing with isolation transformer drivers without having to add external glue logic. The carrier waveform can be programmed with three parameters. The modulation frequency from 1.56 to 25 MHz, the first pulse length to adjust the settling time and the duty cycle to set the sustained current. Burst mode operation is commonly used in power converters when operating under light loads. The burst mode controller allows the outputs alternatively in idle and run states by hardware so as to skip some switching periods with a programmable periodicity and length. The burst mode controller can act on multiple timers in parallel. The outputs are disabled simultaneously with a programmable idle state and the possibility to have a dead time inserted upon burst mode entry to avoid any dead time violations. The burst length is programmable as well as the repetition period when the burst mode is enabled in continuous mode. The burst mode can be started on 32 events and it has multiple burst clock options either coming from the timer rollover event or from independent user programmable period based on the 400 MHz clock. In this example, once the burst trigger arrives, the PWM is active for three periods every eight cycles with pulses skipped for five periods. The burst mode controller counter is clocked and incremented on each timer rollover event. The fault management unit shuts down the PWM outputs and asynchronously forces a user-defined safety state. A software action is required to rearm the outputs. A total of five fault inputs are available each with a programmable polarity, an able bit and a digital filter. It is possible to have one fault input acting on multiple timers for converters requiring multiple synchronized outputs. On the other way round, multiple fault inputs can be merged to protect a single timing unit. The faults are coming from several sources the digital inputs, the built-in comparators for some channels only and the system errors. The system errors are indicating a chip-level abnormal behavior such as a clock security system error, an SRAM parity error, a Cortex-M7 core lockup or a potential brownout condition with the PVD detector. This helps to increase the functional safety level. Last, a global output disable register allows all the outputs to be disabled synchronously in a single right access for an emergency shutdown. The HR timer offers multiple fault protection options. Some are industry standard features. The analog fault uses a comparator. When reaching a user-defined threshold, the comparator tripping causes the PWM output shut down. In digital fault mode, the system is put in a safe state when receiving a digital fault trigger. For the cases where one of the output safe state is active, a dead time can be automatically inserted right after the fault to guarantee a safe transition to the fault state without a dead time violation. The HR timer, however, offers some unique protection features. For LLC converters, the delayed idle maintains the current pulse on the output and the fault state is entered only after it is completed. For the push-pull converters, the balanced idle mode guarantees a perfect balance between the two output pulse widths when a fault is triggered before the converter is actually entering the fault state. The output pulse, which is shortened by the fault, is automatically copied on the alternate output before stopping operation. The fault events can be filtered out by two means. It is possible to do fault blanking so that faults are ignored during specific periods. At the beginning of the PWM cycle, this is also called leading edge blanking or during a window with programmable start and width using the CMP3 and CMP4 compare registers. Another option is to do filtering with the fault counter. Do discard spurious fault information and consider only true errors. The fault counter can operate in two modes, similarly to the external event counter. In the immediate mode, the fault is generated as soon as n consecutive external faults have occurred within a period. The fault counter is reset at the end of the current PWM period. In the cumulative mode, the external fault counter is not reset at the end of the period, but only when there's no fault during a period. The fault will be generated only if it occurred during multiple consecutive periods, as shown on the right side of the figure, after three rising edges on the FLT input. On the contrary, on the left side of the figure, the fault counter is reset after the third period, since there have been only two consecutive faults without a third one. The HR timer has 10 ADC triggering channels with two channels per ADC for the regular and the injected sequencers. This allows up to 10 independent ADC processes in parallel for multiple converters. Each triggering channel has 32 sources, including five from the master timer, five from external events, and four or five for each timing unit. It is possible to simultaneously enable multiple sources for the triggers one to four, when the various trigger instance are clearly defined and do not overlap, as is typical in multi-phase converters. The triggers five to 10 only allow one event at once. Last, the triggering selection registers are pre-loaded for on-the-fly trigger source updates. The ADC triggering rate can be reduced with the ADC post-scaler. This allows the decrease of the number of conversions and ADC interrupt service routines for high PWM switching frequency applications. Each of the 10 ADC triggers can be reduced down to one conversion per 32 counter periods, as shown on the two figures. The right-side figure shows that the ADC triggers can also be positioned during the up or down phase of the counting period using the ADROM or 1 to 0 bits. The HR timer also offers DAC triggers. This allows the possibility to have the DAC values updated synchronously with the timer update events from the master and the slave timers. This is typically used for peak current mode where the DAC is used as a threshold for a comparator. It allows the new DAC value to be applied right at the beginning of the next switching period. Three DAC triggers are available and it is possible to have multiple concurrent sources for the same trigger. The HR timer allows the ease of implementation of slope compensation techniques. This is necessary for peak current mode converters. In this case, the PWM output is turned off by a comparator comparing the current level with a threshold set by the DAC. To guarantee the stability of the power supply in this configuration, it is necessary to apply a descending slope, a sawtooth, on the DAC output connected to the comparator as shown on the figure. This sawtooth must be synchronized with the PWM generation. This is achieved with two DAC triggers, one to reset the sawtooth signal, reloading a start value, and another one to regularly decrement the DAC values. The sawtooth start value and amplitude are defined in the DAC peripheral. The HR timer's dual channel DAC trigger circuitry can be programmed to adjust the trigger generation timings. In the default slope compensation configuration, the DAC reset trigger is sent on the PWM period beginning. The DAC step trigger to decrement the DAC output voltage is generated with the compare two matches the counter value. This register defines the number of steps during a period. The CMP2 value is automatically recomputed by the HR timer after each compare match as shown on the figure so that it can match multiple times per counting period. The compare two register value must only be programmed once, dividing the period value by the expected number of steps. Note that the staircase effect due to the small number of steps in the figure is not representative from a real application and is just for illustration purposes. The high speed DAC allows a much higher number of steps and quasi linear waveforms. All HR timer working registers are duplicated with a shadow register. This applies to the period and compare registers and numerous other configuration registers. It allows glitch free operation when updating multiple registers. The right accesses are done to the preload registers which are transferred in the active registers when an update event occurs, usually at the beginning of a PWM cycle. Two control bits allow handling of the preload mechanism. A preload enable bit preen in each timer globally enables the register shadowing. The update disable bits, MUDIS and TXUDIS can temporarily suspend the update event for complex HR timer updates or on the fly HR timer reconfigurations. Numerous update trigger sources are available within the timer itself from other timers such as master or timers A2F, other on-chip sources such as general purpose timers or following DMA burst mode. The HR timer is able to generate interrupts from a total of 100 sources. They are dispatched on eight interrupt vectors as following. One for each timing unit and the master timer plus one vector dedicated for fault management. The table lists all the sources and gives a brief description of each. The HR timer can also trigger DMA transfers from a total of 91 sources. They are dispatched on seven DMA channels, one for each timing unit and the master timer. The table lists all the sources and gives a brief description of each. The DMA can also be used to dynamically reconfigure the HR timer during converter run times. This is done using the DMA burst mode. Once it is triggered, the content of a table in the memory is transferred into the HR timer control and configuration registers. The DMA burst control registers specify the registers to be updated one by one. Once the transfer is completed, a global register update is issued to have the new values transferred from the preload to the active registers. The HR timer peripheral can be active only in run and sleep modes. In stop and standby modes, the HR timer must be disabled. This slide gives a practical use case of the HR timer. It shows how to generate the PWM signals for a triple interleaved converter. Three step-down converters are running in parallel with a 120-degree phase shift to minimize the output voltage ripple and to spread the input current demand. They must be synchronized to guarantee a constant phase shift and eventually switch off one phase, adjusting the phase shift to 180 degrees. This is done using the master timer. The events generated on master's period compare one and compare two, reset timers A, B, and C respectively. The pulse width on TA1, TB1, and TC1 outputs are then programmed using the compare one register of each of the timing units as per the control loop demand. If we consider the TA1 output, it is built with the output set on master period event, output reset on timer A compare one event. The output TB1 is set on master compare one event and reset on timer B compare one event. The output TC1 is set on master compare two event and reset on timer C compare one event. Note that it is very simple to have an ADC trigger issued in the middle of the pulse width using the spare compare registers in each timing unit. The peripherals listed here influence HR timer behavior. Please refer to the corresponding training for more information. Multiple application notes and user manuals are available for the HR timer for the STM32F334. They are partially valid also for the STM32G4 and can help developers better understand how to use the HR timer.