 Hello, and welcome to this presentation of the STM32 digital filter for Sigma Delta modulators interface. The features of this interface, which behaves like ADC with external analog part and configurable speed versus resolution ratio, will be described. The DFSDM peripheral is a new digital peripheral inside the STM32 products. This behavior can be described as a standard ADC with the analog part outside of the microcontroller. The DFSDM represents the digital part of the ADC which connected to the analog front end by a fast serial interface. The external analog front end is usually implemented as Sigma Delta modulator and is offered by many vendors. Each solution allows to choose a specific analog front end tailoring specific designer needs like galvanic isolation from high voltage in motor control or metering applications, low noise and high precision measurements in data acquisition applications or cheap analog Sigma Delta modulators for price sensitive applications. The digital part represented by the DFSDM peripheral performs the digital signal processing of the external data. By nature it offers a scalable ratio between speed and resolution but also an additional functionality integrated in standard like built in ADC. Like analog watchdogs injected in regular conversions, flexible triggering system, emergency stop signal generation or extremes detector. Wilmem's microphones providing a PDM output data format can be directly connected to the DFSDM2 which returns the decoded digital audio stream. The DFSDM is able to process the external serial data and on top the internally provided parallel 16 bit data provided by the core or TMA unit. Transceivers provide the serial connection to the external Sigma Delta modulator. They support serial connections with various protocols, SPI or Manchester and configurable parameters. Their function will be explained later in detail. Transceivers also have support for internal 16 bit parallel data inputs which will be written to the DFSDM input data registers by the CPU or TMA. Digital filters are the core of the DFSDM function. They perform a 1 bit stream filtering to provide a higher output resolution at lower speeds. There is an additional integrator behind the digital filter which provides additional data averaging. Applications can be designed with various types of Sigma Delta modulators from various vendors. The parallel data input feature allows post-processing of data gathered by another means, for example from internal ADCs, digital signal and audio filtering and so on. The entire filter for Sigma Delta modulators interface consists of 8 serial transceivers, 4 sync filter parts and integrators, 4 output data units for analog watchdogs, 8 short circuit detectors, 4 extreme detectors and 8 parallel data input registers. Serial transceivers provide the connection to the external Sigma Delta modulators. SPI mode works up to 20 MHz or the DFSDM clock divided by 4. There are configurable options including sampling edge selection, data rate measurement and clock presence monitoring. An wire Manchester coded mode where clock is recovered from the data works up to 10 MHz or DFSDM clock divided by 6. A synchronization detection feature is available in Manchester mode too. Manchester mode also offers the lowest system cost in case of optical isolation of the Sigma Delta modulator, only a single isolator per input channel is necessary. The DFSDM features a clock output signal to drive the Sigma Delta modulators. It can be used as a source for the SPI clock transfer internally, avoiding need of additional GPI open. The clock output has an adjustable division factor and can be driven either from the system clock or from the fine tuned audio PLL clock. Parallel transceivers provide a parallel input from internal data sources, for example from memory buffers. Parallel input are usually used for fast hardware filtering of data from the internal ADC or any other collected data from a communication peripheral or algorithm. When DMA is used for processing of memory buffers it needs to be configured in memory to memory transfer mode. The digital filter of DFSDM averages the one bit input stream from the Sigma Delta modulator into a higher resolution data with a slower data rate. The digital filter is a sync X type with an order X from 1 to 5. A fast sync filter type is also available for selection. The oversampling ratio means how many samples will be averaged in a single filter run. The oversampling ratio can be selected in a wide range from 1 to 1024 steps. When high filter order is chosen the oversampling ratio needs to be reduced to avoid register overflow over the 31 bit data width which is also the internal filter resolution. The integrator unit performs additional simple averaging of the data provided by the digital filters. With sums the incoming data the number of samples to be summed can be set from 1 to 256. The correct configuration must guarantee that final data length fits into the 31 bit width which is the resolution of the internal integrator. The width of the data coming from the digital filter must also be taken into account. The output data unit adjusts the final data before they are written to the data register. An offset value can be defined in the offset register that will be automatically subtracted from the data in each channel. The correct offset values are determined using the user calibration procedure such as measurement of shunt voltage when the power stage is switched off prior to starting the application. The maximum resolution of the output data register is 24 bits but the internal resolution goes up to 31 bit. Certain applications have their own constraints for example 8, 12, 16 or 32 and 24 bit data resolution is needed. Therefore there is an option to perform a right bit shift of the data to provide the final data result with the required width and to prevent the overflow of the 24 bit data register. Right bit shift is configurable from 0 to 31 bit. The final resolution depends on the digital filter and integrator settings as well as the bit shift option. The analog watchdog monitors sampled analog data to see if it remains within the selected high and low thresholds. The input to the analog watchdog function can come from the result of the final converted data or directly from the input serial channels through a configurable filter. If data exceeds the allowed threshold an interrupt can be invoked or a break signal generated. If an interrupt is invoked the software decides about the next actions. The break signal can perform a predefined safety action directly in hardware. For example it can stop a timer which controls the motor. There are separate high and low threshold levels and separate flags for each threshold to learn if a threshold has been reached. The analog watchdog can monitor two types of data. The first type is a standard output as with the internal ADC. The second type of data can come from a serial transceiver through a dedicated configurable filter. The second option allows to select faster signal monitoring when the required speed and resolution is set by the filter parameters. Each watchdog sync filter order is configurable from 1 to 3 and filter oversampling ratio in range from 1 to 32. The data from these watchdog filters can also be read by user firmware. The short circuit detector monitors input serial channels for a saturation. When an input signal is saturated it is outside of the allowed measurement range and therefore an overflow or underfall flow of the signal can be signaled. This event can be easily used to detect overvoltage or overcurrent. Detection of the input signal saturation is based on monitoring of the serial data stream coming from the Sigma Delta modulator and watching if there is a consecutive series of ones or zeros for a relatively long time. This maximum saturated time can be set in a range from 1 to 256 of samples with the same logical value 0 or 1. Monitoring is performed independently from the main conversion process that can proceed with another channel or can be stopped completely. All input channels can be monitored in parallel with their own timeouts. When a saturation event is detected an interrupt can be invoked or a break signal generated. Then just like with the analog watchdog the software decides the following action or the hardware break signal can launch a safety function without any software interlapaltency. In the example of the motor it can stop the timer if short circuit is detected in the wiring. The extremes detector monitors the conversion results and stores the extremes into minimum and maximum registers together with associated channel number. Monitoring of data extremes is performed only on selected channels to ensure that channels do not mix different input levels. Stored extreme values are refreshed each time the values are read from the register. Regular conversions have a lower priority and can be interrupted by an injected conversion. If the regular conversion was interrupted by an injected conversion it is restarted once the injected conversion is finished and this interruption is flagged for this delayed regular conversion. Regular conversions can be launched only by software and there is no scan mode available. Regular conversions can run in continuous mode where there is no channel switching and they can be performed in fast mode without filter refill. Regular conversions are used for measurements for which timing is not critical. For example when measuring temperatures or slow signals. Regular conversions are also typical for continuous conversions from one channel only. For example audio or energy measurement applications. Injected conversions have a high priority. They can interrupt regular conversions and start immediately after being triggered. Any of the input channels can be assigned in an injected channels group. There are available two modes of conversion scan and single mode. In scan injected mode all channels from the injected channel group are converted at once starting from the lowest to the highest channel number in the group when the trigger occurs. In single injected mode only one channel from the injected channel group is converted and the next channel from the injected group is scheduled for the next trigger occurrence. Injected conversions can be launched by software or by hardware. For example from timers or an external pin. Injected conversions cannot run in continuous mode but this can be emulated using a periodic timer trigger. Combination of injected and regular mode features make application needs an easy task. In this example the two MEMS microphones share the same data and clock lines. One transmitting on falling and the other on a raising clock edge. The DFSDM multiplexer can route their data to two independent channels. Using injected group both channels can be converted sequentially. The conversion of both channels is periodically started by trigger from an internal timer. For example timer one giving the application continuous data stream from both microphones at a defined rate. In the second example the DFSDM receives data from a single analog modulator. In a continuous mode it provides the data non-stop while application can still request high priority conversions on injected channel group. DFSDM performance depends on the maximum allowed input data rate because each input data sample causes the next digital filter operation step. The DFSDM allows operation at a maximum input data rate of 20 MHz in SPI mode or 10 MHz in Manchester mode. Parallel data inputs have the same performance so parallel data can be input into DFSDM at full speed of 20 MHz using either the CPU or TMA unit. Applications benefit from DFSDM high speed processing which now supports all existing Sigma Delta modulator speed. The STM32L4 evaluation board can be used to run two simple application examples to help you explore the digital filter for Sigma Delta modulator interface. The first example is a demonstration of the MEMS microphone directly connected to the DFSDM peripheral. Data from the microphone are processed by DFSDM with proper filter settings and then collected in a memory buffer using regular continuous conversion and the TMA. Recorded data from the microphone are then immediately sent by another TMA channel from this buffer to the I2S peripheral and they are played by the headphones. The second example is a PT100TM which uses an external STPM S2 Sigma Delta modulator monitoring two analog channels. One channel measures the voltage and second one the current through the PT100 sensor. Both channels are sampled using timer triggered injected conversion in scan mode. Software then determines the PT100 resistance from collected current and voltage data and finally computes the sensor temperature. The third example shows a typical one-phase electricity meter design using an STPM S2 device and STM32 microcontroller. The STPM S2 is a dual channel Sigma Delta modulator designed for electricity meter applications. It has voltage and current channel inputs. The current channel features a programmable gain amplifier to cover a wide range of measured currents. Sampled 1-bit data are sent by the serial interface to the host device which is here the DFSDM peripheral. Both voltage and current 1-bit data samples are sent on the same data wire but the voltage is sampled on the rising clock edge while the current is sampled on the falling clock edge. The clock is provided by the DFSDM and can run up to 4 MHz. The DFSDM then processes the voltage and current data streams into output data with a higher resolution and slow data rate. Finally the firmware uses FFT analysis to calculate the electric power and energy from the current and voltage samples. The last example shows a three-phase electricity meter design using shunt resistors for current sensing. There is no need to use expensive current transformers. Voltages are sent by three resistor dividers and external Sigma Delta modulators. Currents are sent by three shunt resistors. Each shunt resistor voltage is measured by one Sigma Delta modulator. Because each Sigma Delta modulator operates at a phase voltage, galvanic isolation is needed. If the Sigma Delta modulator uses the Manchester-coded serial protocol format and has an internal clock source, only one isolator per phase is needed. If the Sigma Delta modulator operates the SPI serial format, two isolators per phase are necessary. Each Sigma Delta modulator is powered from a separate DC to DC converter.