 So, what we are going to begin with is a brief review of the logic design part that we did and then we will go on to design of combinational and sequential circuits today. So, in this lecture let us see how we design combinational and sequential circuits. First to recall we had seen using TTL and using NMOS how we implement some basic gates like NAND, NOR etcetera. We also learnt what is called the series parallel rule and what it says is that the output must have a bar and for each plus in the expression you put N in parallel and P in series and for each dot in the expression you put N in series and P in parallel. We also had seen that for good CMOS like design which has low power consumption and reliable operation. We must observe a rule and that is that there is an equivalent switch. This equivalent switch could be a series parallel combination of several switches, but there is an equivalent switch which connects you to BDD and another which connects you to ground. So, this is the N equivalent switch and this is the P equivalent switch and we now have to ensure that in no case are both switches on or both switches off. Therefore, let us see whether any condition which turns on one switch automatically assures that the other set of switches is off and the other way round or not. So, let us take as an exercise a simple expression and let us say that we take the expression a dot b plus c dot d whole bar. It is somewhat simpler, but of the same kind that we had discussed yesterday. Let us now proceed with this rule. Notice that there is a bar on top. So, it is doable a dot b. Therefore, the N channel transistors must be put in series. For dot we must have N in series plus that means this whole combination must be in parallel with something. So, in parallel with c dot d because this is also a dot. Therefore, c and d must be in series. This takes care of the N channel transistors. Let us see the P channel transistors again scanning it scanning the expression a dot b and for dot p must be in parallel. So, therefore, I must have a and b in parallel plus for plus p is in series. So, in series with this combination c and d in parallel and this is our logic gate. So, it is quite easy to put down given a logic expression the actual implementation of these and let us see what happens. Now, should a and b both be 1 then irrespective of c and d the output must be 0 because a dot b is 1 and then 1 plus anything is 1 and bar of that is 0. Let us see how it translates to in an actual circuit because both a and b are 1 both these switches are on and therefore, output is connected to ground as we want it to be. But at the same time because both a and b are 1 both the P channel transistors are off and therefore, the equivalent switch towards b d d is indeed off indeed the same condition which ensures that this compound switch is on that means a and b are both on simultaneously assure that the switch towards b d d is off because if both a and b are 1 it assures that N channel switch is on and at the same time it is a sufficient condition to assure that the connection to v d d is in fact off the same thing applies to c and d. So, in short this rule assures all the good properties of T MOS that is to say exactly 1 of these switches must be on connecting the output either to v d d when the output is high or to ground when it is low. Now let us look at a few properties and while in the class you will probably go a little slow over these I am sure most of you are quite familiar with these. So, while for completeness sake I will go over them, but I am sure most of you are familiar with it and we will spend less time on it and a little more time on some other topics which require a bit of understanding. However, let us write it down once and for all one of the. So, this algebra by the way is called Boolean algebra which is named after the mathematician Boole who develop this algebra. So, now every variable is binary value it can have a value 1 or 0 or true flash false. Now, we define two three basic operations actually the plus operation is the or operation the dot operation is the and operation and bar will represent the not operation. The plus operation gives the true output if either or both inputs are true only if both inputs are false is the output false. Similarly, the dot operation gives one only both inputs are true and should either input be false or both be false then the output is false and the bar operation essentially turns a 1 into a 0 and a 0 into a 1. Now these are some of the things that we can prove ebb and issue. For example, we can say that the or of x and x bar should always be 1. The reason is that if x is 0 then x bar is 1 if x is 1 then x bar is 0 and therefore, in either case 1 of the two terms is 1 and 1 plus anything is 1. So, you can show it by truth table or by reasoning that this will always be true at the same time the and of these will always be 0. Of course, from the truth table we have already said that 1 plus x will always be 1 irrespective of the value of 1 and 1 0 dot x is equal to 0. So, this then comes as a corollary of this because at least 1 of x and x bar must be 1 and 1 at least 1 of x and x bar must be 0 and that gives us that x plus x bar must always be 1 and x dot x bar must always be 0. In addition to this follows distributive properties that is to say a dot b plus c will give you a dot b plus a dot c and so on. However, an interesting property is that you have if you have x plus x bar dot y then it can be written as x plus y the x bar is indeed not required why is that so? Because if x is 1 then it does not matter what this is if x is 1 because you have 1 plus something the result must be 1 and that is so on the left hand side as well as on the right hand side. If x is 0 then the left hand side does not matter and this becomes 1 therefore, the result is y and so it is on the right hand side. So, essentially for all values of x this relation is true that x could be 0 or 1. So, if you have x plus x bar dot y then you can simply drop the x bar that is not required it is just equal to x plus y this is a useful property of this algebra. Now, this particular thing has consequences which are important and let us look at it from a truth stable view. So, let us say that I have some function and this function is specified as a truth table. So, that means I have let us say a b and the possible combinations could be 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 and I could have a column of values which will map. So, for example, we have seen that NAND or etcetera were all defined by a truth table of this kind let us plot some other value. So, let us say that the value z which is the function of a and b could be say 1 0 0 1. What function is it? This is the equality function if a is equal to b then the output is 1 if a is unequal to b the output is 0. So, if I have this function how to express this function algebraically what we do is that pick all those cases where z is 1 what are those cases a equal to 0 and b equal to 0 similarly a equal to 1 and b equal to 1. So, if a is 0 a bar is 1 and if b is 0 then b bar is 1 and what it says is that in z is 1 either if a bar dot b bar is 1 or a dot b is 1. That means this would be 1 if both are 1 this will be 1 if both are 0 and therefore, z can be written as this. This gives us the rule of converting a truth table into an algebraical expression. You pick out all the ones and if the corresponding value of the variable is 0 put its bar if it is 1 put the variable as it is and take the dot of all those that gives the rule for this row this row is applies only if a is 1 and b is 1 which is uniquely specified by a dot b. Similarly, this row implies that a is 0 and b is 0 which is uniquely specified by a bar dot b bar. So, a bar dot b bar will be true only if a is 0 and b is 0 then which is what defines this row. So, we pick all the rows in which the value is true and define all the numbers by these variables and put it this kind of form is called the sum of products. It is not necessary to also look at 0 because it is a binary system and if we specify all cases in which case it is 1 in all other cases it is assumed that it will be 0. So, therefore, just picking out one will completely specify this function. We could have actually chosen all the zeros as well and this would lead to a different kind of expression which will be a product of sum. This results from the fact that a 1 is a forcing function for sum and 0 is a forcing function for product. So, if we are looking at 0 then we must pick out all the products which have a result 0 and express each term as a sum. If we pick out only the ones then we must express it as a sum and a sum of those conditions must be represented as a dot because we want all those conditions to be satisfied. So, therefore you have these two forms of specifying any logic and these are called canonical forms. These are standard forms of putting down logic. Now, notice that the logic may be put down in some form and that may not be the most concise or the most easy to implement way. In particular, if let us look at something like this, suppose you have x dot y plus z plus y bar dot x. Now, this looks like a proper equation. However, if I open it out what I get is suppose I had an expression like this x dot y plus z plus y bar dot x. Then I can expand it out and that will give me x dot y plus x dot z plus y bar dot x as it was. Now, I can take x common between this term and this term and that gives me x dot y plus x dot y plus y bar plus x dot z. But we know that y dot y bar y plus y bar is always 1 and x dot 1 is just x. So, what we get is x plus x dot z which is nothing but x dot 1 plus z and that simply x because this will become 1. So, in fact, this logic expression could have been simplified to a great extent if we carry out this algebra. Now, every time carrying out this you could do of course always do it by algebraic rules, but every time carrying it out like this is painful. What we want is a graphical expression which will pick out those cases where such things occur. That means the output is true irrespective of whether y is 1 or 0. If we could make a graphical table where y equal to 1 and y equal to 0 are close by then we can see this grouping very easily and this is done by a kind of representation which is called Kano map. So, we have this Kano map. What we want to do is express this expression in such a way that this simplification would have been obvious to us. What we therefore want to do is to write these in an order such that only 1 bit changes at a time. So, for example, I could write it as x and y in this direction and z in this direction. Now, because we want only 1 bit to change at a time they have to be written in a particular order. So, for example, x and y could have the value 0 and 0. They could have the value 0 and 1 in traditional style we often follow it by 1 0, but that would change 2 bits at a time. Therefore, we write it as 1 1 and then 1 0. These are the x and y combinations z could be 0 and 1 and if you now notice the value of all the variables here at a given time in the nearest neighbors only 1 bit is changed. For example, consider these 2 in this case only x remains constant at 0, but y goes from 0 to 1. So, if we have a true value in both of these squares that means it is true whether y is 0 or y is 1 and therefore, it is true whenever z is 0 of course, but if x is 0 that is a sufficient condition to make this function 1. We do not have to bother about y. So, in short the elimination of a logic variable results from the fact that 2 neighboring squares in which the value of that bit has changed that can be eliminated. So, now let us try to form a Carnot map of this function for all the variables all the values which are here. So, now if x y and z are 0 then this evaluates to 0. This is 0. So, it does not matter and this is 0. So, it does not matter. So, the output is actually 0. If x is 0 and y is 1 with z equal to 0 again it does not matter because x is 0 both these terms will become 0. If both x and y are 1 then this term is 1 and this is 0 because y bar is 0. So, if both are 1 then the term is 1. If x is 1 and y is 0 and z is 0 then this is 1 dot 0 plus 0. Therefore, that gives us 1 dot 0 which is 0. Similarly if z is 1 we can work it out for all the values x dot y plus z if the combination is 0 0 1 is 0 dot something. So, it will always be 0 plus of course, y bar dot x. So, whenever x is 0 we can see whenever x is 0 we can see both terms will be 0. So, therefore all the terms with x equal to 0 will be 0. By the way this term when x is 0 and x is 1 and y is 0 this term will give us 1. So, this should have been 1. This term is 0, but plus x dot y bar will become 1. So, this term is 1. Now, x dot y bar being 1 it does not matter what this term is this itself is sufficient to ensure that it is 1. Therefore, we will get a 1 here and when both x and y are 1 you have 1 dot 1 and that also gives us 1. Now, let us look at this graphical representation of this function. We can see that these are all 0's, but these are all grouped as 1. If I take the largest possible combination which is of the size sum 2 to the power n that means either size 2 or 4 and find out what are the properties of this group. So, for example, this I have now accounted for all the 1 in this map. What are the properties of this group? For all the terms in this x is 1 and y can be 1 or 0. Similarly, z can be 0 or 1 and therefore, it does not matter what the values of y and z are for both values of y and for both values of z the function is 1. Therefore, this evaluates to x. So, just by inspection of this we can simplify this function. The rule for that is the following. You first of all write a representation of the truth table in this format in which only 1 bit is changing at a given time. So, for example, if you have 2 bits then you can write it as 0 0 0 1 then 1 1 and 1 0 and then you can club those terms. For example, let us now without looking at the expression consider some arbitrary Kano map and now if let us say that you have 2 terms here and here and everything else is 0. So, what does this group represent? This group occurs only for z equal to 1 it is confined to this row and that row belongs to z equal to 1 and only if y equal to 1 and it does not care whether x is 0 or 1. Therefore, this group essentially is z dot y z must be 1 and y must be 1. So, this group therefore, represents z dot y. So, we can have any arbitrary function and we can express it as a truth table in this format written in this graphical combination and now we can group these numbers and if we pick the largest group then we will eliminate the most term and get the simplest possible expression. Now, notice an interesting property of the Kano map. So, let us look at a Kano map of 4 variables now I have x and y in this direction and p and q in this direction. Now, x and y can acquire values 0 0 0 1 1 1 1 0 these are written in this order. So, that only 1 bit is changing at a time similarly, p and q pair can acquire values 0 0 0 1 1 1 1 0. Now, consider a case in which this is 1 this is 1 this is 1 this is 1 and this is 1. You can easily see the grouping which is this and which is this what would you have written these groupings as because this is group vertically like this and p is changing from 0 to 1 p will drop out and q must be 1. So, the term that it contributes is q on the other hand x and y are both 0 in this case. So, we might be tempted to write the expression as x bar y bar q and similarly for this one we have again for these 2 rows q must be 1 and we do not care for p because p could be 0 or it could be 1. Therefore, these 2 group a grouping of these 2 rows corresponds to just q on the other hand a must be x must be 1 and y must be 0. Therefore, this would be x dot y bar dot q if I add these what I find is that I could have taken y bar q common and I get x plus x bar and therefore, it should just be y bar q. So, what happened why did we not get the optimum expression in the first place and that is because the columns at the end of it are supposed to be adjacent and we did not know that means this column and this column while physically drawn separately are to be considered adjacent. Similarly, this row and this row must be considered adjacent that is because this column and this column has also 1 bit changing namely in this case x changes from 0 to 1, but y remains 0. So, only 1 bit is changing between this column and this column and therefore, we must consider these 2 columns as adjacent by the same reason this row and this row must be considered adjacent because this is 0 0 this is 1 0 there is 1 bit changing from 0 to 1 and why q remains at 0. So, therefore, the combination of this row and this row is just q bar. So, as a result finally, what we should have seen is that not only are these 2 rows to be merged, but these 2 columns are to be merged and in fact, the group is this entire group is 1 because these 2 columns are to be considered adjacent. So, we have 1 big square like this which merges into 1 and what is the property of this group notice that as we go vertically then q must remain 1 this is p q and we do not care what p is for this entire group we do not care what p is because p could be 0 and p could be 1 therefore, we do not care what p is similarly the row column grouping says that x y could be 0 0 or 1 0 that means we do not care what x is, but y must be 0. So, therefore, the property of this group is that y must be 0 and q must be 1 therefore, this is y bar y must be 0 and q must be 1. So, y bar dot q and this gives us the optimum expression. So, in short we should treat extreme rows and columns as adjacent to each other and indeed one very interesting combination is this because these 4 share extreme rows and columns. So, what would these be these represent well this is when this is 0 0 the p q could be 0 0 or 1 0 that means we do not care for p, but q must be 0 similarly this combination of the first and the fourth column says x y can be 0 0 or 1 0 therefore, we do not care for x however, y must be 0 therefore, the combination of these 4 quadrants forming one group would therefore, be y must be 0 and q must be 0. So, that is y bar q bar. So, in short if we write down the truth table in this fashion we can we should try to group the largest possible group of adjacent one and then take care that we treat the first column and the last column as adjacent and the first row and the last row as adjacent and when we club them then we will find that many terms become do not care because they could be 0 or they could be 1, but the output is still 1 and then we can club them all together and come up with optimally simple expressions. So, this technique is called Kano maps by the way it does the final expression does depend the order in which you draw the table and more than one minimal expression might in fact represent the same logical function which is all right. Let us now proceed with a different idea now and up to now we have had logic which is called combinational and the property of this is that the output is mapped uniquely to the combination of input for a different input the output can be different. However, once the inputs are specified at the current time then the output is completely known it does not depend on anything else such logic is combinational logic. However, in real life we often have situation in which the output depends not only on what is the current situation, but also on what has happened before. And that requires memory we must remember what has happened before so how can we implement memory let us work it out in a somewhat ordered way. Let us begin with the NOR gate notice that a 1 on a NOR gate is forcing that means if you put a 1 on this input it does not matter what you put on the other input the output is guaranteed to be 0. Similarly, for a NAND a 0 is a forcing input if either input becomes 0 irrespective of the other the output becomes 1 we are going to make use of this property. Now, suppose we want we had an input it was 0 initially it became 1 and then it became 0 again. Now, at this point any combinational function will have the same value as at this point because the value of the input is the same in this case 0. However, we want a special combination which will remember that this value had become 1 in between that means it should leave a trace of this value having become a 1. So, we want to create an output which will remember that this signal had gone from 0 to 1 and then came back from 1 to 0. So, that we can distinguish this situation from this situation. So, how can we do this well one of the possibilities is that we make a replica of this signal and make sure that the replica stays put and has exactly the same effect as the input has. So, let us develop it step by step. So, let say this is my input A how can I make a replica of A consider this. Now, if this is A this then this is A bar and if this is A bar then this is A. Notice that this is a copy of A, but it is derived from the output. Now, if I could have some circuit in which this copy performs the same function as the original and it is a forcing function then A can go away, but the copy will keep the output in the same state and because the output will remain the same state the copy will continue to persist. So, while A has gone away this copy will persist because it is derived from the output. So, that is the kind of arrangement that we want to make. Now, therefore, I need a gate which will use both the input and the copy of the input. So, I cannot have an inverter here I must modify this logic to a 2 input logic and because we had already seen that this is a forcing input let us convert this to a nor. So, this is A and if A is 1 this will force the output to 0 which will make this 1. So, therefore, this is a copy of A. Now, if A ever became 1 consider this case suppose the output is 0. So, if A here let us take the output from here currently this is the copy which persists and therefore, will have the memory effect. Now, if A becomes 1 at this point then irrespective of what this is doing this output will become 0 if this is 0 then this output will become 1 and if this is 1 that is sufficient condition to keep the output 0 and this output 1. Now, if A goes away nobody will notice it because this copy is performing the same function namely of keeping this point at 0 and this point at 1 as the original signal and it is capable of keeping it in that state without the help of A. So, therefore, when A goes to 0 this guy is 1 and that ensures that this output is 0 and this output is 1 and therefore, the output of this circuit will not change and we have got a memory effect. However, we have a problem once this becomes 1 and this becomes 0 this guy cannot be changed now ever because should this be 1 this is 0 irrespective of what I do here. So, if this is 1 this is 0 this is 0 this ensures that it is 1 and it is a self perpetuating condition and cannot be changed by anybody at all. So, that is not very good that means this circuit will work once and after that it is stuck at that value and will not change its value we cannot change it. So, let us then modify the lower NAND as well and let just redraw this circuit and just to avoid clutter let us do it on a fresh page. So, the point that I was making was that we need to make a replica of the signal and the replica must be forcing. So, rather than using a couple of inverters to make the replica we make a couple of nodes to make this replica and we come up with this cross connected north. Now, initially suppose we call this R and S and call this out and we will later see that this will be a bar of the input right now let me just write it as out bar we will prove it later. Now, let us say that R has that same wave form and we begin with initial conditions that Q is out is 0. Therefore, an out bar is 1 and R as well as S R 0. Let us see whether this is a stable condition or not. If this is 0 and out bar is 1 then this 1 will keep this at 0 and because both of these are 0 this output is 1 this 1 will keep it 0. So, therefore, this is this is stable that means a condition let us just write R S and let me not force this as out and out bar let us call that Q 1 and Q 2. In that case R is 0 S is 0 and if Q 1 was 0 then both S and Q 1 are 0 and therefore, Q 1 this being a north is 1. If Q 2 is 1 that is sufficient to keep Q 1 at 0 and therefore, as long as R and S remain 0 the output will remain in this state of 0 and 1. So, this is a state which sort of keeps itself stable. Now, let us say that R goes to 1 when we are in this state. Now, R goes from 0 to 1 what will happen R going from 0 to 1 will force this output to 0. This is a north and a 1 here is a sufficient condition irrespective of what the other input is doing to force the output to 0. So, this will become 0 and this 0 and this 0 will keep it 1 and this 1 will then keep it at 0. So, essentially what it means is that a 1 at R ensures that Q remains at 0, Q 1 remains at 0 and Q 2 remains at 1. Let us however, now consider a case that initially Q 1 was 1 and Q 2 was 0 and see that is stable. That means our initial state is R 0 S 0, but this time Q 1 is 1 and let us work out what the other things are. If Q 1 is 1 then that ensures that Q 2 is in fact 0. A 1 here is a sufficient condition to ensure that the output goes to 0 this being a north and if this is 0 and R is 0 this is 1. So, therefore this is consistent and can remain in this state for unless we change it it will remain in this state. So, if this is the initial state and now R becomes 1 has this transition. Let us see what happens if R is 1 that is sufficient to ensure that this output becomes 0 and therefore Q 1 has become 0. We assume that S has remained at 0. So, if R becomes 1 that is sufficient to ensure that this is 0 and this is 0 and this is 0 this output becomes 1. Indeed this 1 is now the replica of R and R can now go away, but this 1 will now this copy will make sure that the output remains at 0. So, now we have a stable state even after R has gone away. So, R can now return to 0, but because this Q 1 this Q 2 is 1 Q 1 will remain at 0 and because both these inputs are 0 this output will remain at 1. That means this return transition from 1 to 0 has no effect this circuit remembers the arrival of 1 by making Q 1 equal to 0 and Q 2 equal to 1 because from either starting condition this was one starting condition and this was the other starting condition. From either starting condition it ensures that Q 1 goes to 0 and Q 2 goes to 1 this is called the reset input. It resets Q 1 to 0 and Q 2 will be a complementary state. Let us see the effect of S. So, now consider the scenario and let us redraw the circuit just for working it out from scratch and again we carry out the same analysis. Let us say that the initial state is the same state. That means R and S are 0 and Q 1 and Q 2 are 0 and 1 respectively. However, this time an event occurs on S that means S goes from 0 to 1 and then returns. Let us see what is the effect of that. If S goes to 1 R remains at 0 if S goes to 1 this being a nor it does not care what the other input is. If this is 1 that is sufficient condition to make Q 2 equal to 0. So, R was 0 and S has become 1 that is sufficient condition to make Q 2 equal to 0 and if Q 2 is 0 and R is 0 R is 0 and Q 2 is 0 that means Q 1 now becomes both are 0 therefore, Q 1 will become 1. That means the arrival of a 1 on S has changed the state of Q 1 and Q 2 from 0 and 1 to 1 and 0. What happens when S returns to 0? That means R remains at 0, but S now returns to 0. That means the situation at R and S is the same as we had started from. However, now as S returns to 0 remember Q 1 and Q 2 are 0 and Q 2 are at 1 and 0 now. This is the state of Q 1 and Q 2. If S now returns to 0 however, this is 1 Q 1 is 1 and that is sufficient to keep the output at 0. We do not need S anymore. In fact, we have created a copy of S when it became 1 because this was 1 and Q 1 became 1 and it is this copy which will force the output to 0. We do not care that S has actually returned or not. So, as soon as this becomes 1 it forces Q 2 to 0 Q 1 to 1 and that copy is sufficient to make sure that even if S returns to 0 this output will remain at 1 to 0. So, notice that the initial condition for R and S is the same that means R and S have returned to their original passive state. We have been able to change Q 1 from 0 to 1 and accordingly Q 2 from 1 to 0. Now, you can see that Q 2 is a complement of Q 1 in all these cases. Therefore, we can look at Q 1 as the primary output and the effect of a 1 on S is to force Q 1 to 1 from 0. It has gone from 0 to 1 if S had a transition from 0 to 1 and back. So, it now remembers Q 1 becomes 1 and this is a memory. It remembers that S had become 1 even though it may have returned to 0. Now, we have implemented a memory a circuit whose output is 1 or 0 depending on what had happened in the past. Now, we get a new class of circuits which can produce outputs depending not only on the current input, but also on what happened in the past. So, this input is there then called the set input because it sets Q 1 to 1. Of course, just like a 1 is a forcing input for a nor a 0 is a forcing input for a NAND and we can do exactly the same thing by cross connected NAND gates. But now the passive state of the inputs will be 1 because if this is a 1 the output is determined by this input. If both of these are 1 then the outputs are determined by feedbacks and that is the passive state and the memory will be if either one of them has gone to the forcing state which is 0. That means now the outputs will remember whether one of the inputs had had a transition like this having remained at 1 and had it ever transition to 0. Just to take quickly the output if this becomes 0 this will force this output to 1 a 1 here and a passive 1 here will make this 1 and this 0 both of the 0 will make it 1. Now, if this returns to 1 this 0 is sufficient to keep it at 1. So, it will actually remember. So, that replica of has is sufficient because a 0 has appeared here in response to a 0 here and this replica will do exactly the same thing as the original input had done and therefore, now we do not need the original signal anymore. The original signal may return to its passive state at 1 and now we can combine these storage elements with logic elements to form counters and other such circuits which will remember the effect of this which will remember the effect of this memory. However, this is just the background of what we really want to do later. The point is that all of this logic is fixed. If we want a new circuit then we have to buy new components and connect them separately. Ideally what we would like is to have the connections always the same, but we would like to reconfigure the logic to perform a new function. So, this kind of logic is called reconfigurable logic. That means the same components perform some function earlier and they perform some other function later. So, how do we reconfigure? We can change some connection the basic components remain the same, but we can change some configuration. Let us look at one instance of this and that is to say let us say that I have laid out lots of N channel and P channel transistors once and for all. So, consider a case where I have P channel transistors and they are connected like this. So, suppose I have a template available like this a component available like this. Now, notice that in our CMOS logic one N channel and one P channel transistor was connected to each input. So, this is already done for us one N channel and one P channel transistor are connected to each other. However, how to configure various kinds of logic from this preconfigured block. So, let us look at let us say that this is a template that we will repeat many times and we want we now want to configure it to form different kinds of logic. We could do the following Suppose I connect this point to VDD and connect this point to ground and connect this here and this here. What have I got now? Consider just the left part from VDD and ground. What is the circuit? I have from VDD I have a P channel transistor connected to A and then an N channel transistor going to ground and this is the output. This is nothing but an inverter. Similarly, I have VDD a P channel transistor and an N channel transistor to ground that means I have been able to configure this template into two inverters. Let us consider another configuration where the transistors remain the same, but our interconnections become different. So, let us take the same configuration. This is the original configuration given to us. Suppose I now ground this input connect the center to VDD and short these two inputs. Let us try to recognize what this circuit is. From VDD I have a P channel transistor connected to this node, but I also have another transistor connected to this node and these two are A and B. That means I have a connection in which these two transistors are in fact in parallel. I have VDD a P channel transistor controlled by A and to this terminal. Similarly, I have VDD and a P channel transistor controlled by B going to the same terminal. From that terminal I have a series connection of N channel transistor, one of which is connected to A and the other is connected to B. Now, this is the case where the N channel transistors are in series and the P channel transistors are in parallel. This means that this is N NAND. That means I have been without changing the configuration or the number of transistors, I have been able to implement the function A dot B whole bar. Similarly, I could have done put the P channel in series and the N channel in parallel. Let us see how that would be done. I have the same basic template and this time I connect the ground here and short these two. You can easily see that the two P channel transistors are obviously in series. So, I have two P channel transistors, one connected to A, the other connected to B and these two are in series. We also have two N channel transistors in parallel. That means we have this transistor connected to B going to ground. At the same time from the same node, I have a transistor connected to A going to ground. That means I have put the two N channel transistors in parallel. This is nothing but a norm. So, what it means is that from this template, I can make all the basic gates which I require. I can make NAND, I can make NOR and I can make two inverters. Therefore, if I have got any logic, what I could do is to make a circuit in which I repeat this template in advance. Just keep this template ready and then whenever I want to implement any logic, I would choose from one of these pre-configured interconnections. If I want inverters, then I will use this configuration and I will get two inverters. If I want NANDs, then I will use this configuration which I can store once and for all. This interconnect I can store once and for all and then I will get NAND and if I need NOR, I can use this configuration. So, this interconnect can be these are finite number of combinations and I can store these interconnects once and for all. So, then I can reconfigure this logic, reconfigure this combination to form inverters, NANDs or NORs. I can break down my logic design to inverters, NANDs or NORs and then just implement any logic with a repetitive combination of this kind of a block. So, this is an example of reconfigurable logic. There are many other ways in which reconfigurable logic can be implemented. For example, any logic function, I can pre-compute the values and put it in a memory. Then anytime the input combination is that much, it selects that memory cells and returns the pre-computed value. So, this is called a lookup table way of implementing reconfigurable logic. So, there are many ways of making reconfigurable logic and different companies have made various chips often called CPLDs and we have distributed a board with those capabilities for lab work there. After this introduction to reconfigurable logic, there will be a demo of how to use this card in your lab.