 Hello, and welcome to this presentation of the STM32 Universal Synchronous Asynchronous Receiver Transmitter Interface. It covers the main features of this USART interface, which is widely used for serial communications in embedded systems. The STM32G4 embeds three Universal Synchronous Asynchronous Receiver Transmitter, or USARTs, and two Universal Asynchronous Receiver Transmitter, or USARTs. The USART is a very flexible serial interface that supports Asynchronous USART communication, SPI master and slave modes, Smart Card ISO 7816 communication, IRDA Serial Infrared Communication, LIN mode. It also provides certain features that are useful when implementing modbus communications. The USART implements the same features as the USART, except Support of Synchronous Protocols, SPI, and Smart Card. Applications making use of the USART benefit from the easy and inexpensive connection between devices, which only requires a few pins. In addition, the USART peripheral is functional in low power modes. It comes with transmit and receive FIFOs, and can transmit and receive in stop modes. The USART is a fully programmable serial interface featuring the following configurable parameters, data length, parity, number of stop bits, data order, bound rate generator, and a configurable oversampling mode by 8 or by 16. The USART can operate in FIFO mode, and it comes with two FIFOs, transmit and receive FIFOs. You have the option to use basic RS232 flow control with CTS and RTS signals. The RS485DE signal is also supported. The USART supports a dual clock domain, allowing wake up from stop mode and bound rate programming independent of the peripheral clock. This also allows the peripheral clock to be throttled along with the core clock without disrupting communications. The USART features a multi-processor mode, which allows the USART to remain idle when it's not addressed. In addition to full duplex communication, single wire half-duplex mode is supported. The USART also offers many other features, including auto-bound rate detection, receiver timeout, and supports several modes which will be described later in the presentation. This table also highlights the differences between the three USARTs, the two UARTs, and the LPUART. The UART does not support synchronous mode and smart card mode. The LPUART does not support synchronous mode, smart card mode, IRDA communication, LIN mode, modbus communication. This is the USART block diagram. The USART clock source, or USART CURSEE-K, can be selected from several sources. Peripheral clock, called APB clock, or P clock, SIS clock, high-speed internal 16 MHz oscillator, or HSI-16, low-speed external oscillator, or LSE. The USART clock source is divided by a programmable factor in the USART PSC register in range 1 to 256. TX and RX pins are used for data transmission and reception. NCTS and NRTS pins are used for RS-232 hardware flow control. The driver-enabled pin, or DE, which is available on the same I.O. as NRTS, is used in RS-485 mode. The clock output, or CK, is dual purpose. When the USART is used in synchronous master-slave mode, the clock provided to the slave device is output input on the CK pin. When the USART is used in smart card mode, the clock provided to the card is output on the CK pin. Note that the NSS and NCTS signals share the same pin. NSS is the slave selection input applied to the device in synchronous slave mode. The USART has a flexible clocking scheme. The registers are accessed through the APB bus, and the kernel is clocked with USART CUR clock, pre-scaled or not, which is independent from the APB clock. In order to pass data from one clock domain to the other one, either eight data FIFOs are used or single data buffers. The USART block is an APB slave that can rely on DMA requests to transfer data to or from memory buffers. The functions of the TX and RX pins can be swapped. This allows to work in the case of a cross-wide connection to another UART. The USART receiver implements different user configurable oversampling techniques for data recovery by discriminating between valid incoming data and noise. This allows a trade-off between the maximum communication speed and noise clock inaccuracy immunity. Select oversampling by eight to achieve higher speed up to USART CUR-C-K prez divided by eight, where USART CUR-C-K prez is the USART clock source frequency. In this case, the maximum receiver tolerance to clock deviation is reduced. Select oversampling by sixteen by setting over eight to zero to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to USART CUR-C-K prez divided by sixteen. The maximum bowed rate that can be achieved is twenty-one point twenty-five megaboud when the clock source is at one hundred and seventy megahertz and oversampling by eight is configured. With other clock sources and or higher oversampling ratio, the maximum speed is limited. The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. The USART supports seven, eight or nine bit data lengths. A frame starts with one start bit, where the line is driven low for a one bit period. This signals the start of a frame and is used for synchronization. The start bit is followed by seven, eight or nine data bits. If parity control is enabled, the parity bit is transmitted as the last data bit and is included in the data length count. Finally, a number of stop bits setable to zero, one, one point five or two, where the line is driven high, ends the frame. Data order is programmable with most significant bit first or least significant bit first shifting. The standard frame was described in the previous slide. This slide shows an example of eight bits data frames configured with one stop bit. An idle character is interpreted as an entire frame of one. The number of one will include the number of stop bits. A break character is interpreted on receiving zero for a frame period. At the end of the break frame, two stop bits are inserted. The USART supports full duplex communication where TX and RX lines are respectively connected with the other interfaces RX and TX lines. The USART can be configured to follow a single wire half duplex protocol where the TX and RX lines are internally connected. In this communication mode, only the TX pin is used for both transmission and reception. The TX pin is always released when no data is transmitted. Thus, it acts as a standard IO in idle or reception modes. This means that the IO must be configured so that the TX pin is configured as an alternate function open drain with an external pull up. In RS232 communication, it's possible to control the serial data flow between two devices by using the NCTS input and the NRTS output. These two lines allow the receiver and the transmitter to alert each other of their state. The figure shows how to connect two devices in this mode. The idea is to prevent dropped bytes or conflicts in case of half duplex communication. Both signals are active low. For serial half duplex communication protocols like RS485, the master needs to generate a direction signal to control the transceiver. This signal informs the physical layer if it must act in send or receive mode. In RS485 mode, a control line is used. The driver-enable pin, named DE, is used to activate the external transceiver control. DE shares the pin with NRTS. To simplify communication between multiple processors, the USART supports a multiprocessor mode. In multiprocessor communication, it is desirable that only the intended message recipient should actively receive the message. The device is not being addressed to put into mute mode. The USART can enter or exit from mute mode using one of two methods, idle line detection, address mark detection. Unlike the USART, the USART can also communicate synchronously. It can operate as an SPI in master or slave mode with programmable clock polarity named C-Pole and phase named C-Fay and programmable data order with MSB or LSB first. The clock is output in case of master mode or input in case of slave mode on the C-K pin. No clock pulses are provided during the start and stop bit. When the USART is configured in SPI slave mode, it supports the transmit under-run error and the NSS hardware or software management. Unlike the UART, the USART can be used in smart card mode, based on a half-duplex communication. The clock is output to the smart card on the C-K pin. It supports the T equals zero protocol and provides many features allowing support for T equals one. Both direct and inverse conventions are supported directly by hardware. The USART supports IRDA specifications which is a half-duplex communication protocol. The data from and to the USART is represented in an NRZ non-return to zero format, where the signal value is at the same level through the entire bit period. For IRDA, the required format is RZI return to zero inverted, where a one is signalled by holding the line low and a zero is signalled by a short high pulse. The serial infrared or SIR-transmit encoder modulates the non-return to zero transmit bit stream output from the USART. The SIR received decoder demodulates the return to zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the USART. The USART only supports bit rates up to 115.2 kilobits per second for the SIR NDAQ. In normal mode, the transmitted pulse width is specified as 3 sixteenth of a bit period. The USART receiver is able to detect and automatically configure the bowed rate based on the reception of one character. The received character can be any character starting with a bit at one. In this case, the USART measures the duration of the start bit from falling edge to rising edge, any character starting with a one zero xx pattern. In this case, the USART measures the duration of the start and of the first data bit. The duration is measured from falling edge to falling edge, ensuring better accuracy in the case of slow signal slopes. Zero x7f character frame. In this case, the bowed rate is updated first at the end of the start bit, then at the end of bit six, a zero x55 character frame. In this case, the bowed rate is updated first at the end of the start bit, then at the end of bit zero bit, and finally at the end of bit six. In parallel, another check is performed for each intermediate transition of the rx line. The USART supports a receiver timeout feature. When the USART doesn't receive new data for a programmed amount of time, a receiver timeout event is signalled, and an interrupt is generated, if enabled. The USART receiver timeout counter starts counting. From the end of the first stop bit in case of one and 1.5 stop bit configuration. From the end of the second stop bit, in case of two stop bits configuration. From the beginning of the stop bit, in case of half stop bit configuration. The USART can operate in FIFO mode, which is enabled or disabled by software. It is disabled by default. The USART comes with a transmit FIFO called TXFIFO and a receive FIFO called RXFIFO, each being eight data deep. When the IRDA and LIN modes are used, the FIFO mode is not supported. Provided that the TXFIFO and RXFIFO are clocked by the kernel clock, it is possible to transmit and receive data, even in stop mode. It's possible to configure TXFIFO and RXFIFO thresholds used mainly to avoid underrun or overrun issue while waking up from stop mode. The USART is able to wake up the MCU from stop mode when the USART clock source is the HSI or LSE clock. The sources of wake up can be a specific wake up event which is triggered by either a start bit or an address match or any received data. An RXNE interrupt when FIFO management is disabled or FIFO event interrupts when FIFO management is enabled, receive FIFO full interrupt, transmit FIFO empty interrupt, receive FIFO threshold interrupt, transmit FIFO threshold interrupt. This slide and the next two ones provide the list of interrupt events, detailing their cause and indicating whether these events can be used as wake up requests. Several events can provide an interrupt. The transmit data register empty flag is set when the transmit data register is empty and ready to be written. The transmit complete flag is set when the data transmission is complete and both data and shift registers are empty. The CTS flag is set when the NCTS input toggles. The receive data register not empty flag is set when the receive data register contains data ready to be read. The idle line flag is set when an idle line is detected. The character match flag is set when the received data corresponds to the programmed address. The receiver timeout flag is set when there's no activity on the RX line for a programmed duration. The transmission complete before guard time flag is set after the end of frame transmission and if no NAC has been received from the card. The end of block flag is set when a complete block is received. The wake up from stop mode flag is set when the wake up event is verified. The limb break flag is set when a limb break frame is detected. The transmit FIFO not full flag is set when the transmit FIFO is not full. The transmit FIFO empty flag is set when the transmit FIFO is empty. The transmit FIFO threshold flag is set when programmed threshold is reached. The receive FIFO not empty flag is set when the receive FIFO is not empty. The receive FIFO full flag is set when the the received FIFO is full. The received FIFO threshold flag is set when the programmed threshold is reached. Several errors flags can be generated. The overrun error flag is set when an overrun error occurs. The parity error flag is set when a parity error occurs. The framing error flag is set when a framing error occurs. The noise error flag is set when a noise is detected on the received frame. The auto bowed rate error flag is set when the bowed rate measurement failed. The underrun error flag is set when an underrun error occurs in synchronous slave mode. The DMA requests can be generated when receive buffer not empty or transmit buffer empty flags are set when FIFO management is disabled. The DMA requests can also be generated when the transmit FIFO not full and receive FIFO not empty flags are set when FIFO management is enabled. The USART peripheral is active in run, sleep and low power modes. The USART interrupts cause the device to exit sleep and low power sleep modes. The USART is able to wake up the MCU from stop 0 and stop 1 modes when the USART clock is set to HSI or LSE. USART reception is functional in stop mode and generates a wake-up interrupt on start, address match or received frame event. In standby and shutdown modes the peripheral is in power down and it must be re-initialized after exiting standby or shutdown mode. This is a list of peripherals related to the USART please refer to these trainings for more information if needed. General purpose input or outputs, reset and clock controller, power controller, interrupts controller, direct memory access controller.