 Hello, I am Mr. S. S. Shakapure, assistant professor, department of computer science and engineering, Vulture Institute of Technology, Sulapur. My today's topic about block diagram of DMA controller 8257, my learning outcome at the end of this session to understand concepts of direct memory access controller and how to initiate and DMA cycle and their use in a microprocessor based system. Now what is DMA? DMA stands for direct memory access. It is designed by Intel to transfer data at the fastest rate and it allows devices to transfer the data directly to from memory without any interference of the CPU. So in some in short, we can say here once we got any permission from the processor. So without the interference of the processor we directly can able to transfer our data from memory or to memory. It operates in two modes that is master mode and slave mode how DMA operations are performed. So following is the sequence of operations performed by DMA initially when any device has to send data between the device and the memory. The device has to send DMA request to DMA controller. So it is a DRQ request. The DMA controller sends hold request to the CPU and waits for the CPU to assert the DLA HLDA. So here the controller now sends hold request to the processor and waits to get the acknowledgement from CPU that is called HLDA. Then the processor tries to get all the data bus address bus and control bus. The CPU leaves the control over bus and acknowledges the hold request through HLDA signal. Here processor if once leaves the control over the bus and it acknowledges to hold request that is HLDA signal. Now the CPU is in hold state and the DMA controller has to manage the operation over buses between the CPU, memory and IOD devices. Now here you can able to see the block diagram of it 257. So my internal data bus divides two parts to my 8257. So my right side is have different functional blocks. These functional blocks are nothing but DMA channels and my right side I have the different functional blocks they are control and mode set resistor, read write logic and data bus buffer. Okay. About the block diagram 8257 is a programmable four channel direct memory access controller that is four peripheral devices can request data transfer at any instant. Each channel has two signals one is a request signal and another is a request acknowledge. Okay. It is nothing but DMA request and DMA acknowledgement. The request priorities are decided internally and there are also 8 bit registers one is the mode set register and another is status register. It can operate both in slave and master mode. The functional block diagram consist of different functional blocks, data bus buffer, read write logic, DMA channels, control logic, priority resolver. So one by one now let us check exactly about these functional block. The very first one is a data bus buffer. This is a three state bidirectional 8 bit buffer interface the 8257 to the system data bus. When the 8257 is being programmed by the CPU, 8 bits of data for DMA address register, a terminal count register or the mode set register are received on the data bus. When the CPU reads the DMA address register, terminal count register or status register, the data is sent to the CPU or the functional block diagram. Next consisting read write control logic. In the slave mode when the CPU reads data from or writes data to the 8257, the read write logic accepts the IOR or IOW signals and decodes the least significant first 4 bit address bits and during DMA cycle when 8257 is in the master, the read write logic generates the IOR read and memory write or IOR write and memory read signals which controls the data link with the peripherals that has been granted DMA cycle. The next functional block consists of DMA channels. The 8257 has 4 separate DMA channels each channel with 2 16 bit register, DMA address register and count register and both these register must be initialized before a channel is enabled and the DMA address register is loaded with the address of the first memory location to be accessed and the value loaded into the low order 14 bits of the terminal count register specifies the number of DMA cycles minus 1 before the terminal count output is activated. So please think I have a question for you. In 8257 each of the 4 channel has we have the 4 options, a pair of 2 8 bit registers, a pair of 2 16 bit registers, 1 16 bit register, D1 8 bit registers. Please think on this question. We have discussed already about this question. So your answer is B, the DMA supports 4 channel and each of the channel has a pair of 2 16 bit registers namely DMA address register and our terminal count register. Now my next functional block is control logic block. This block controls the sequence operations during all DMA cycles by generating the appropriate control signals and 16 bit address that specifies the memory relations to be accessed and it contains 2 specific registers and they are mode set register and status register. About the mode set register it is a write only register, it is used to set the operating modes and this register is programmed after initialization of DMA channel. About the mode set register it is a 1 by register have different flags and each different flag have decides different operating mode. About the mode set register the D7 flag bit that is atto load mode if we set AL equals to 1 it is in atto load mode and if we set it is in 0 it represents the rotating mode. The same way about the next flag TCS, TCS equals to 1 it represents stop after terminal count disabling the channel else enable the channel or you can say the start after TC. Next D5 bit if EW equals to 1 it represents extended write mode. If EW equals to 0 it indicates it is in normal mode and the D4 bit that is the RP is equals to 1 it represents rotating priority if RP equals to 0 it represents fixed priority. In the next bit D3 and D2 and D1 and D0 these 4 bits used to represent the flag value 1 to enable DMA channel 3, 2, 1 and 0 respectively and if EN equals to 0 it represents disabling that particular DMA channel 3, 2, 1 and 0 respectively. About the status register it is read only register where you can able to see 5 bits D4, D3, D2, D1, D0 so it tells the status of DMA channels TC status bits are set when TC signals is activated for that channel. Update flag is not affected during read operation and the UPBT is set during update cycle it is cleared after completion of update cycle. Now about the D5 bit UP that is update flag if UP equals to 1 it to 5, 7 executing update cycle if UP equals to 0 it to 5, 7 executing DMA cycle and about the next TC bits. So if TC equals to 1 TC activating channel 3, 2, 1, 0 respectively about the flag values of TC 3, 2, TC 1 and TC 0 if TC equals to 0 TC is not activating channel that is with respect to TC 3, TC 2, TC 1 and TC 0. If we are observing the summary the DMA controllers are normally used in high performance devices where bulk of data need to be transferred from the input to the memory without any interference of the CPU. So these are what my references which I used.