 Hello everyone. Myself Prithviraj Thambe working as an assistant professor in Valgin Institute of Technology in Department of Electron Engineering. Welcome to this session. In this session, we will learn general structure of programmable logic devices. At the end of the session, students can examine the general structure of programmable logic devices. So what is a programmable logic device? So normally we use fixed function logic devices like multiplexers, demultiplexers, flip-flops like devices. So programmable logic devices are programmed by users to perform a variety of logic functions. They can be used to replace hardware fixed function logic gates like I said multiplexers, demultiplexers, etc. They are normally used to build reconfigurable digital circuits. So this reconfigurability allows the designer to readily change the program and use these PLDs without rewiring or replacing the existing components. So this leads to faster implementation. So these are the three types of PLDs. Simple programmable logic devices, complex programmable logic devices and failed programmable gate arrays. So in this session, we will discuss simple programmable logic devices. So SPLD are again categorized like programmable ROMs, programmable logic array, programmable array logic and generic array logic. So let us learn the structure of programmable logic devices. So these PLDs are made up of buffer inverters in the first stage and gate arrays in the second stage or gate arrays in the third stage and again buffer inverter in the last stage. So inputs are applied to the gate arrays through buffers and inverters. So array of AND gates and OR gates which can be programmed to specific functions are normally connected in the matrix fashion which are in the forms of rows and columns with a fusible link at each cross points. And these fuses can be blown to eliminate selected variables from the final output. So normally hardware description languages are used to program these programmable logic devices. So the first stage is the buffer and inverter stage. So inputs are applied to the set of buffers and inverters. So these provides the true values as well as the complemented values of the inputs. Also they provides necessary drive for the AND arrays. So this is the symbol inverter with a bubble and a buffer without bubble. So what is an AND array? So AND arrays are used to generate AND terms or product terms. So from N number of input variables and their complements, multi-input AND gates array produces at max 2 raise to N number of AND or product terms. So here you will see a structure of AND array. So these AND gates are multi-input AND gates with fusible link which can be programmed. So let us calculate the number of AND terms generated with 10 number of input variables and their complements. So with 10 number of input variables and their complements, multi-input AND gate array can produces 1024 number of AND terms. So let us see one example how these AND arrays can be used to generate AND terms. So here this is the four input AND gate having W, X, Y and Z as inputs and these are the fusible links. So if you want to implement X dot Y or to generate this AND term, we need to blow fuse W and fuse Y and we need to keep the fuses X and Z intact. So the output of this AND gate after program is f is equal to X dot Y. Also this is one of the representation to show multi-input AND gate where these rows and columns are having fusible link. So if you blow these links for the given function the symbolic will look like this. Next third stage is the OR stage OR arrays. So the product terms or AND terms generated from the AND array are failed to the OR array which are used to realize set of M numbers of outputs in the SOP form that is sum of product form. And these outputs lines are again made available for the final usage through inverter or buffer stage sometimes. So let us see one example. If you want to generate f is equal to W plus Y where these W, X, Y and Z are the AND terms generated from the AND arrays. So to generate W plus Y we need to blow fuse of X and Z input so that you will get the output of this OR gate as f is equal to W plus Y where W, X, Y and Z individually represents AND terms. Here is again one of the symbol used to represent multi-input AND gate having rows and columns and after the programming for the above function this multi-input OR gate will look like this. So these are the few advantages of using programmable logic devices over fixed logic ICs. References. Thank you.