 Hello and welcome to this presentation of the STM32L5 power controller. The STM32L5's power management functions and all low power modes are also covered in this presentation. STM32L5 devices feature a flexible power control, which increases flexibility in power mode management and further reduces the overall application consumption. This slide details the consumption in the various power modes for the STM32L5-62. Run mode can support a system clock running at up to 110 MHz with only 11.21 mA. The consumption is even lower when frequency and voltage are decreased. 7 mA in range 1 at 80 MHz and 1.87 mA in range 2 at 26 MHz. STM32L5 devices support 8 main low power modes. Low power run, sleep, low power sleep, stop 0, stop 1, stop 2, standby and shutdown modes. Each mode can be configured in many ways, providing several additional sub modes. In addition, STM32L5 devices support a battery backup domain called VBAT. The high flexibility in power management provides both high performance with a core mark score equal to 4.02 MHz, together with an outstanding power efficiency. The STM32L5 has several key features related to power management. Several low power modes down to 17 nanoamps while it is still possible to wake up the MCU with an event on an I.O. For only 668 nanoamps, 64 kilobytes of SRAM2 can be retained assuming a 1.8 volt VDD power supply. A large number of peripherals can wake up from the various low power modes. Dynamic consumption is down to 62 microamps per MHz when the internal step-down converter is used. A battery backup domain called VBAT includes the RTC and the backup registers. Several power supplies are independent, enabling the reduction of the MCU power consumption while some peripherals are supplied at higher voltages. Thanks to the large number of power modes, STM32L5 devices offer high flexibility to minimize the power consumption and adjust it depending on the active peripherals, required performance and required wake-up sources. STM32L5 devices have several independent power supplies which can be set at different voltages or tied together. The main power supply is VDD, supplying almost all I.Os except those part of the VBAT domain and port G pads 15 down to 2. VDD also supplies the flash memory, the reset block, temperature sensor and all internal clock sources. In addition, it supplies the standby circuitry which includes the wake-up logic and independent watchdog. The built-in switched mode power supply or SMPS step-down converter is a power efficient DC-DC nonlinear switching regulator that improves low power performance when the VDD voltage is high enough. The SMPS step-down converter automatically enters into bypass mode when the VDD voltage falls below a VDD minimum value following the selected voltage range and switches back to the selected operating mode when VDD rises above the minimum value. Only STM32L5-52XXXP and STM32L5-62XXXP support SMPS. The other STM32L5 microcontrollers only rely on integrated regulators or external SMPS power supplies. V-core supplies most of the digital peripherals, SRAMs and flash memory controller. VDDA voltage supplies the analog peripherals. The VREF plus pin provides the reference voltage to the analog to digital and to digital to analog converters. It is also the output of the internal voltage reference buffer when enabled. The USB transceiver and port G pins 15 down to 2 also have their own independent power domains powered by VDDUSB and VDDIO2 respectively. A backup battery can be connected to the VBAT pin to supply the backup domain. This slide explains the pinout of switched mode power supply or SMPS power supply. VDDSMPS is provided externally through VDDSMPS supply pin and shall be connected to the same supply as VDD. VLXSMPS is the switched SMPS step down converter output. V15SMPS are the power supplies for the system regulator. It is provided externally through the SMPS step down converter VLXSMPS output. The SMPS power supply pins are only available on a specific package with SMPS step down converter option. When it is not present, the main regulator is connected to VDD. The main power supply VDD ensures full feature operation in all power modes from 1.71 up to 3.6V, enabling it to be supplied by an external 1.8V regulator. Device functionality is guaranteed down to 1.6V, the minimum voltage after which a power down reset is generated. Other independent supplies are provided to enable peripherals to operate at different voltages. VDDA is the external analog power supply for analog to digital converters. Digital to analog converters, voltage reference buffer, operational amplifiers and comparators. When the analog to digital converters or comparators are used, the VDDA voltage must be greater than 1.62V. When the digital to analog converters or operational amplifiers are used, VDDA must be greater than 1.80V. When the voltage reference buffer is used, VDDA must be greater than 2.4V. VDDUSB must be in the range 3.0 to 3.6V. VDDUSB power supply may not be present as a dedicated pin, but internally bonded to VDD. For such devices, VDD has to respect the VDDUSB supply range when the USB controller is used. VDDIO2 must be in the range 1.08 to 3.6V. VDDSMPS is the external power supply for the SMPS step-down converter. A backup domain is supplied by VBAT, which must be greater than 1.55V. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator, and the TAMP block containing the 128-byte backup registers. VBAT is internally bonded to VDD for small packages without dedicated pin. VDD12 is the external power supply bypassing the internal regulator when connected to an external SMPS. The ADC and DAC voltage references can be provided either by an external supply voltage or by the internal reference buffer. This improves the performance of the converters by providing an isolated and independent reference voltage. The VREF plus pin and thus the internal voltage reference is not available on certain packages. In those packages, the VREF plus pin is double bonded with VDDA and the internal voltage buffer must be kept disabled. The voltage reference can be provided through the VDDA pin in those packages. Two embedded linear voltage regulators supply all the digital circuitries except for the standby circuitry and the backup domain. The regulator output voltage providing VCOR can be programmed by software to three different values, depending on the performance and the power consumption requirements. This is called dynamic voltage scaling. Depending on the application mode, VCOR is provided either by the main voltage regulator for run, sleep, and stop-zero modes, or by the low-power regulator for low-power run, low-power sleep, stop-one, and stop-two modes. The regulators are off in standby and shutdown mode. When SRAM 2 content is preserved in standby mode, the low-power regulator remains on and provides the SRAM 2 supply. The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals according to the application performance and power consumption needs. Here are the supported voltage and frequency pairs. Range 0, voltage is 1.28 volt and frequency up to 110 MHz. Range 1, voltage is 1.2 volt and frequency up to 80 MHz. Range 2, voltage is 1.0 volt and frequency up to 26 MHz. The SMPS step-down converter is used to step down the VDD supply. When the SMPS step-down converter is enabled, it can be configured in high-power mode or HPM, low-power mode or LPM, bypass mode. HPM achieves a high efficiency at high current loads. SMPS high-power mode is used in all ranges 0, 1 and 2. It is the default selected mode after poor reset. LPM achieves a high efficiency at low current load. When enabled, the voltage scaling must not be modified. This mode shall be only selected in range 2 and when power consumption does not exceed 30 mA. When the bypass mode is enabled, the SMPS step-down converter is switched off and it is possible to change the voltage scaling. This mode can be forced by software by setting the SMPS by P bit in PWR-CR4 register. In range 0 and range 1, the SMPS bypass mode is selected automatically when VDD drops below 2.0.5 volts. There is no automatic SMPS bypass in range 2. The bypass mode can be enabled or disabled on the fly at any time by the application software. During stop 1, stop 2, standby and shutdown modes, the SMPS step-down converter is switched to open mode. When exiting from low power modes except shutdown mode, the SMPS step-down converter is set by hardware to the mode selected prior to the low power mode selection. After poor reset, the SMPS step-down converter is in high power mode. The power reset bore and pour resets all registers except those in the backup domain powered by VBAT which contain the RTC and TAMP blocks and the external low speed oscillator LSE. When exiting standby mode, all registers powered by the main regulator are reset. When exiting shutdown mode, a power reset is generated. Five bore levels can be selected via the option byte. During power on, the bore keeps the device under reset until the supply voltage VDD reaches the specific VBOR-X threshold. When VDD drops below the selected threshold, a device reset is generated. When VDD is above the VBOR-X upper limit, the device reset is released and the system can start. POR and PDR are always on except in shutdown mode. Five bore levels can be selected through option bytes. When VDD goes beyond the VBOR rising edge threshold value, the reset is negated. When VDD goes below the VBOR falling edge threshold value, the reset is asserted. A power voltage detector or PVD can generate an interrupt when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby and shutdown modes. The threshold is selected by software among seven possible values. In addition, comparisons can be done between VREF-INT and the PVD-IN external pin. The VDD-A power supply can be independent from VDD and can be monitored with two peripheral voltage monitors or PVM. VDD-IO2 and VDD-USB can also be monitored by dedicated PVMs. Each PVM output is connected to an EXT-I line and can generate an interrupt if enabled through the EXTI registers. This is a new feature compared to STM32L4 microcontrollers. The STM32L5 also supports two new features to enhance the power supply supervision. Temperature threshold monitoring, upper VDD threshold monitoring. Whenever these monitors detect an abnormal condition, they can generate an internal tamper event. The STM32L5 offers a new feature compared to STM32L4. The SRAM2 can be entirely or partially retained in standby mode. Either 64 kilobyte or the upper 4 kilobyte can be preserved. From run mode, it is possible to access all low power modes except low power sleep mode. In order to enter low power sleep mode, it is first required to enter low power run mode and execute a wait for interrupt or wait for event instruction while the regulator is the low power regulator. Similarly, when exiting low power sleep mode, the STM32L5 transits via low power run mode. When the device is in low power run mode, it is possible to transition to all low power modes except sleep, stop 0, and stop 2 modes. Stop 0 and stop 2 modes can be entered from run mode. If the device enters stop 1 mode from low power run mode, it will exit in low power run mode. If the device enters standby or shutdown, it will exit in run mode. Each peripheral clock can be configured to be on or off in run and low power run modes. By default, all peripherals clocks are off except the flash interface clock. The SRAM clock is always on in run mode. When running from SRAM in run or low power run modes, the flash memory can be put in power down mode and the flash clock can be switched off. The flash memory must not be accessed when it is switched off. Consequently, interrupt vectors must be mapped in SRAM using the Cortex-M33 vector table offset register. The current consumption in run or low power run modes depends on several parameters. First, the executed binary code. That means the program itself plus the compiler impact. Then, it depends on the program location in the memory, the device software configuration, the IO pin loading and switching rate, and the temperature. The consumption also depends on whether the code is executed from flash memory or from SRAM. Energy efficiency is better when the flash prefetch and the instruction cache are enabled. Executing from flash consumes more than executing from SRAM because the flash memory belongs to the VDD power domain while the SRAM belongs to the V-Core power domain. In run mode, the CPU is clocked and program code can be executed from flash or SRAM memory. In range 0, the system clock frequency is up to 110 MHz. All peripherals can be activated in range 0. In STM32L5-52XX and STM32L5-62XX, only the main regulator is active. In STM32L5-52XXP and STM32L5-62XXXP, both the main regulator and the SMPS are active. In range 0, when the internal flash memory is not needed, it can be powered down. In run mode, the voltage scaling range 1 is the medium performance range, enabling a system clock frequency from 26 MHz to 80 MHz. As in range 0 mode, the internal flash memory can be powered down. All peripherals can be activated. All clocks can be enabled. In range 2, the system clock is up to 26 MHz. All peripherals can be activated except the USB device and random number generator. All clocks can be enabled. In low power run mode, the CPU is clocked and program code can be executed from flash or SRAM. Additionally, the flash can be completely unpowered to save power. The system clock is limited to 2 MHz. The main regulator is switched off and supply to digital blocks is provided by the low power regulator. In low power mode, all peripherals except the USB device and random number generator can be active. Sleep and low power sleep modes enable all peripherals to be used and features the fastest wake up time. In these modes, the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep and low power sleep modes. These modes are entered by executing the assembly instruction wait for interrupt or WFI or wait for event or WFE. When executed in low power run mode, the device enters a low power sleep mode. Depending on the sleep on exit bit configuration in the Cortex M33 system control register, the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupt subroutine. This last configuration saves time and consumption by avoiding the need to pop and push the stack when exiting the low power mode. However, all computations must be done in Cortex M33 handler mode because the thread mode is no longer used. In sleep mode, the CPU clocks are off. In range 0, the system clock is up to 110 MHz. In range 1, it is up to 80 MHz. And in range 2, it is up to 26 MHz. By default, the SRAM clocks are enabled. They can be individually gated off during sleep mode. All peripherals can be activated in range 0 and 1. In STM32L5 52XX and STM32L5 62XX, only the main regulator is active. In STM32L5 52XXXP and STM32L5 62XXXP, both the main regulator and the SMPS are active. Clock gating is supported for SRAM 1 and SRAM 2 when sleep mode is active. In low power sleep mode, the CPU clock is off and the logic is supplied by the low power regulator. The system clock is up to 2 MHz. Flash memory can be configured in power down and can be gated off. SRAMs can be gated off. All peripherals can be activated except the USB, OTG and random number generator. STM32L5 devices feature three stop modes, stop 0, 1 and 2, which are the lowest power modes with full retention and wake-up time of only a few microseconds to run mode. The contents of SRAM and all peripherals registers are preserved in stop modes. All high-speed clocks are stopped. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake up from stop mode. System clock on wake-up is the internal high-speed oscillator at 16 MHz or MSI, up to 48 MHz. Stop 1 is similar to stop 0, with the main regulator switched off. In stop 2, only LPU-ART, LP-TIMERS 1 and 3, I2C3 and comparators peripherals remain active. The voltage regulator is configured in main regulator mode. All clocks in the V-core domain are stopped. The PLL and the HSE, HSI 16, HSI 48, MSI oscillators are disabled. The RTC clocked by the internal or external low-speed oscillator can remain active. The brown-out reset is always enabled. Most of the peripheral clocks are gated off. Several peripherals can be functional in stop 0 mode. Power voltage detector, peripheral voltage monitor, digital-to-analog converters, operational amplifiers, comparators, VREF buff, independent watchdog, low-power timer, I2C, UART, and low-power UART. The events from all IOs can wake up from stop 0 mode, as well as the interrupt generated by the active peripherals. The I2C-UART or LPU-ART can switch the HSI 16 on during the stop mode in order to recognize their wake-up condition and switch off the HSI 16 after receiving the frame if it is not a wake-up frame. In this case, the HSI 16 clock is propagated only to the peripheral requesting it. The system clock when exiting from stop 0, stop 1, or stop 2 mode can be either MSI up to 48 MHz or HSI 16, depending on the software configuration. In STM32L5-52XX and STM32L5-62XX, only the main regulator is active. In STM32L5-52XXXP and STM32L5-62XXXP, both the main regulator and the SMPS are active. Stop 1 mode is very similar to stop 0, except that the power figures are much lower as the main regulator is stopped and replaced by the low-power regulator. In stop 2 mode, most of the V-core domain is put in a lower leakage mode. LPU-ART reception is functional in stop 2 mode and generates a wake-up interrupt on start, address match, or received frame event. I2C3 address detection is functional in stop mode and generates a wake-up interrupt in the case of an address match. During stop 2, standby and shutdown modes, it is possible to set the bore and PVD in ultra-low power mode to further reduce the power consumption. The standby mode is the lowest power mode in which the contents of SRAM-2 can be entirely or partially retained. The automatic switch from VDD to VBAT is supported and the IOS level can be configured by independent pull-up and pull-down circuitry. By default, the voltage regulators are in power down mode and the contents of SRAM and peripheral registers are lost. The 128-byte backup registers are always retained. The brown-out reset is always on to ensure a safe reset regardless of the VDD slope. Each IO can be configured with or without a pull-up or pull-down which is applied and released thanks to the APC control bit. This controls the input state of external components, even during standby mode. Five wake-up pins are available to wake up the device from standby mode. The polarity of each of the five wake-up pins is configurable. The wake-up clock is MSI from 1 to 8 MHz. In standby mode with SRAM-2 retention, the main regulator is powered down and the low power regulator supplies the SRAM-2 to preserve its content. The RTC clocked by the internal or external low-speed oscillator may remain active. The brown-out reset is always enabled. The independent watchdog can also be enabled in standby mode. Reset, brown-out reset, RTC and tamper detection. Independent watchdog, LSE clock security and any event on the five wake-up pins can cause the microcontroller to exit standby mode. IOs can be configured with internal pull-up, pull-down or floating in standby mode. The IOs with wake-up from standby or shutdown capability are PA0, PC13, PE6, PA2, PC5. In standby mode without SRAM-2 retention, both main and low power regulators are powered down. Wake-up events and available peripherals as well as wake-up sources are the same as in standby mode with SRAM. The shutdown mode is the lowest power mode of the STM32L5 with only 17 nanoamps at 1.8V. This mode is similar to standby mode but without any power monitoring. The power down reset is disabled and the switch to VBAT is not supported in shutdown mode. Hence the product state is not guaranteed in case the power supply is lowered below 1.6V. The LSI is not available and consequently the independent watchdog is also not available. A power reset is generated when the device exits shutdown mode. All registers are reset except those in the backup domain and a reset signal is generated on the pad. The 128-byte backup registers are retained in shutdown mode. The wake-up sources are the five wake-up pins and the RTC events including tampers. When exiting shutdown mode the wake-up clock is MSI at 4 MHz. In shutdown mode the main regulator and the low power regulator are powered down. The RTC clocked by the external low-speed oscillator can remain active. The brownout reset is deactivated. Only the external low-speed clock can be enabled. The wake-up events are the RTC and tamper events, the reset and the five wake-up pins. IOS can be configured with internal pull-up, pull-down or floating in shutdown mode but the configuration is lost when exiting the shutdown mode. Here you can see the summary of all the STM32L5 power modes. The backup domain keeps the RTC fully functional and preserves the backup registers if the VDD supply is down thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low-speed external oscillator at 32.768 kHz. Three tamper pins are functional in VBAT mode and will erase the 128-byte backup registers also included in the VBAT domain in the case of an intrusion detection. The backup domain also contains the RTC clock control logic. If VDD drops below a certain threshold the backup domain power supply automatically switches to VBAT. When VDD is back to normal the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the backup battery level. When VDD is present the battery connected to VBAT can be charged from the VDD supply. In VBAT mode the main regulator and the low power regulator are powered down. The RTC and tamper clocked by the external low-speed oscillator can remain active. Only the external low-speed clock can be enabled. The only powered block is the backup domain that includes RTC and tampers and the return to normal execution happens once VDD supply is provided. The VBAT consumption without RTC is typically around 3.4 nanoamps at 1.8 volt. The battery charging feature enables the charging of a supercapacitor connected to VBAT pin through the internal resistor when VDD supply is present. The charging is enabled by software and is done either through a 5 kilo ohm or 1.5 kilo ohm resistor depending on the software. Battery charging is automatically disabled in VBAT mode. The VBE bit field of the PWR-CR4 register enables battery charging. The VBRS bit field of the PWR-CR4 register selects the resistance value. During the startup phase if VDD is established in less than TRS-T tempo and VDD is greater than VBAT plus 0.6 volt a current may be injected into VBAT through an internal diode connected between VDD and the power switch. If the power supply or battery connected to the VBAT pin cannot support this current injection it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. Three bits are available in the flash option bytes to prohibit a given low power mode. When cleared a reset is generated instead of entering the related low power modes. The microcontroller integrates special means allowing the user to debug software in low power modes. Three bits are available in the debug control register in order to allow debugging in stop, standby and shutdown modes. When the related bit is set the regulator is kept on in standby and shutdown modes the HCLK and FCLK clocks remain on to keep the debugger active. This maintains the connection with the debugger during the low power modes and continues debugging after wake up. Remember to clear these bits when the MCU is not under debug because the consumption is higher in all low power modes when these bits are set due to the fact they force the clocks and the regulators to remain enabled. The PWR is a trust zone aware module. When the trust zone security is activated by the TZEN option bit in the flash opt R register some PWR register fields can be secured against non-secure access. The PWR trust zone security secures the following features through the security configuration register PWR sec CFGR low power mode wake up pins voltage detection and monitoring and VBAT mode. Other PWR configuration bits are secure when the system clock selection is secure in RCC. The voltage scaling or VOS configuration is secure but GPIO is configured as secure. Its corresponding bit for pull-up or pull-down configuration in standby mode is secure. The RTC is secure. The backup domain write protection DBP bit in PWR CR1 register is secure. The UCPD is secure. The UCPDDB DIS and the UCPD standby bits are secure in the PWR CR3 register. A non-secure write access to PWR sec CFGR register is write ignored and generates an illegal access event. The PWR registers can be read and written by privileged and unprivileged access depending on privbit and PWR priv CFGR register. When the privbit is reset all PWR registers could be read and written by both privileged or unprivileged access. When the privbit is set all PWR registers could be read and written by privileged access only except PWR SR1, PWR SR2 and PWR sec CFGR registers. Unprivileged access to a privileged register is read as zero write ignore. In addition to this training you can refer to the following presentations. Reset and clock control. Real-time clock. Tamper. STM32CubeMX focusing on the description of the power consumption calculator.