 Hello and welcome to this presentation of the STM32G4 Digital 2 Analog Converter. This block is used to convert digital signals to analog voltages which can interface with the external world and also with on-chip peripherals such as comparators and operational amplifiers. The STM32G4 Digital 2 Analog Converters converts 8 or 12-bit digital data to an analog voltage. Each DAC module has two converters that can work synchronously or asynchronously. A low-power sample and hold mode is also integrated. The DAC can interface with external potentiometers or BIA circuitry. It can also create voice and arbitrary signals. The Digital 2 Analog Converter inside the STM32G4 microcontrollers offers simple Digital 2 Analog Conversion in an 8 or 12-bit mode. The DAC outputs can have a low impedance buffer to drive external loads. Its sample and hold mode can reduce the power consumption significantly. The two converters within the same DAC can be synchronized with each other. The input data can be transferred by DMA which offloads the CPU. It also integrates small logic to generate noise, triangle and sawtooth waveforms. The DAC output data is updated by a complex triggering system based on software request, timers, HRTIM and EXTI. Vref Plus is used as a positive voltage reference. An input reference pin, Vref Plus, shared with other analog peripherals is available for better resolution. An internal reference voltage buffer can generate the reference voltage on the same pad. Output buffer's voltage offset is calibrated. This calibration is performed at the factory, loaded after reset. The user calibration can be done when the operating conditions differ from nominal factory calibration conditions and in particular when VDD, VDDA, voltage, temperature, Vref Plus values change and can be done at any point during application by software. Here you can see the simplified block diagram of the Digital 2 Analog Converter. This DAC block is supplied by VDDA and uses Vref Plus as a voltage reference. The Digital 2 Analog Converter is an AHB slave that supports DMA requests to fill the data hold register. Either of the DAC out X signals can be disconnected from the corresponding output pin which can be used as an ordinary GPIO. DAC out X signals can use an internal pin to connect to on-chip peripherals such as comparators and op amps. DAC output channels are buffered or non-buffered. Sample and hold block use, LSI or LSE clock source and are operational in stop mode for static conversions. The content of the data hold registers is transferred to the corresponding data output register when a trigger condition is detected. This includes software triggers. Then the content of the data output register is transferred to the converter. The output buffer has mechanism to calibrate the voltage offset. The STM32G4 implements four DAC units. DAC1, 3, 4 support two channels while DAC2 supports only one channel. DAC1 and DAC2 can be output to GPIOs while DAC3 and DAC4 only have internal channels that can be connected to comp and op amp units. Consequently, DAC3 and DAC4 do not implement output buffers. The utilization of output buffers is optional for DAC1 and DAC2. DAC1 and DAC2, maximum speed is one mega-sample per second while DAC3 and DAC4, maximum speed is 15 mega-sample per second. The DAC OutX can use an internal pin connection to on-chip peripherals such as comparator and operational amplifier. Regarding DAC1 and DAC2, the corresponding DAC OutX GPIO can be used for another purpose. Connecting the internal DAC output to a comp-in-m input defines the reference voltage of the comparator. Connecting the internal DAC output to an op-amp v-in-p input can be used to bias the op-amp DC point or amplify the analog voltage. It is also a way to get internal DAC channels to pin, which can be useful for DAC3 and DAC4. The DAC can support different input formats. In 8-bit mode, it is a right-aligned 8-bit data format. It also accepts the unsigned and signed data format. In dual-channel mode, it is an 8-bit plus 8-bit data format in order to provide input data for two DACs. In 12-bits plus 12-bits, either a right or left aligned mode can be used for input data. Data held in these registers are transferred to the related converters, either synchronously for instance for stereo audio or asynchronously. This means that the two channels can operate independently. DAC output conversion is started by writing to the data hold register using software. Seven different timer outputs, seven different HR TIM outputs, and an external I.O. or software can trigger a DAC conversion. When a software trigger is used, the content of the data hold register is transferred to the corresponding data output register after one AHB clock cycle. When a trigger occurs in trigger mode, the content of the data hold register is transferred to the corresponding data output register after three, five, or seven AHB clock cycles, depending on the AHB clock frequency. The sample and hold feature maintains the DAC output voltage while not actively driving continuously. It relies on an internal or external capacitor that will hold the voltage level at the end of the sample period. Then the DAC output can be set in high impedance. Of course, the capacitor will discharge over time. That is why a refresh period has been defined. Upon expiration of the refresh period, the DAC output will be actively driven again to recharge the capacitor. The digital to analog converter can work intermittently, charge the external or internal capacitor, and be powered down while the output voltage is kept on the hold capacitor. After the refresh period, the DAC is powered back on again and recharges the hold capacitor. When the DAC is configured in sample and hold mode, it is able to generate its converted output voltage and active circuitry can be turned off. In this mode, the DAC core and all corresponding logic and registers are driven by the LSI clock or LSE clock in addition to the DACH clock, allowing the usage of the DAC channels in deep low power modes such as stop mode. The logic in charge of scheduling refreshes only requires the LSI or LSE clock. In doing so, the DAC is only active during very low-duty cycles, sample and refresh, resulting in very low power consumption. The duty cycle program is very flexible and autonomous. The capacitor can be external or internal. When it is external, the buffer can be used and the DAC's output can also be routed to internal components, such as embedded comparators. When it is internal, an embedded capacitor is used and the DAC's output is routed only to internal components. The charging time depends on the capacitor value. The timings for the three phases above are in units of LSI or LSE clock cycles. The DAC digital interface integrates three special signal generators, noise, triangle and sawtooth. The linear feedback shift register can create the noise signal for the DAC input. Each trigger updates the DAC output data by an LFSR block. The up-down counter with a programmable count value can create triangle wave data, which can update the DAC output data. The data can also be updated by a trigger signal. The DAC can generate a sawtooth waveform. Specific register settings for the initial value, increment value and direction control are required. The sawtooth counter starts from STRST data. Each increment trigger then increments or decrements ST, INC data value. The increment trigger and reset trigger must be selected through the STRST, INC, trig cell and the STRST, trig cell bit fields. This feature is useful to create the threshold voltage for the comparator to control the motor current. The increment value is defined by the STRST, INC, data bits in the DAC STRX register. The DAC output is used from 12 MSB of those counter value. When the counter reaches 0X0 or 0XFFFF, the value is saturated. The sawtooth direction is defined by STRDIAR bit in the DAC STRX register. The DAC can also issue DMA requests from the trigger signal. Once a trigger is detected, the data hold register value is then transferred to the data output register. Then the DMA request is generated to obtain the new data for the data hold register. As the update of the output data register is initiated directly by the trigger signal, the DAC output signal will not have jitter so that it can create a stable sampling time signal output, making it easy to filter out the sampling frequency. The DAC supports a double data DMA capability to reduce the bus activity. The DAC DMA request is generated every two external triggers, except for software triggers so that two samples are transferred in the same 32-bit AHB transaction. In DMA double mode, DMA requests can only handle one DAC channel. To use two channel outputs in DMA double mode, each DMA channel has to be configured separately. To transfer data from memory, a DMA request can be generated. The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgment of the first external trigger is received, then no new request is issued and an underrun flag is set that causes a maskable interrupt request. The digital 2 analog converter is active in the following low-power modes, run and sleep. In stop 0 and stop 1 modes, it remains active when sample and hold mode is selected. In standby and shutdown modes, the DAC is powered down and it must be reinitialized afterwards. The following table shows some performance parameters for the digital 2 analog converter. The DAC can work between 1.71 and 3.6 volts. When DAC output buffer is on or DAC outpin is connected, the minimum VDDA voltage value is 1.8 volts. 10-bit monotonosity is guaranteed. When operating at 1 mega-sample per second, power consumption is 185 microamps when the buffer is enabled and 155 microamps when the buffer is disabled. By using sample and hold mode, the current consumption can be drastically reduced. Depending on the condition and the hold capacitor characteristics, less than 1 microamp's current consumption is possible for this mode. The DAC buffered output has a setting time of 1.6 microseconds with 50 picofarad load. The DAC can handle a sampling rate of 1 mega-sample per second or 15 mega-samples per second. This is a list of peripherals related to the DAC. Please refer to these peripheral trainings for more information if needed. Application notes dedicated to DAC topics are also available.