 Hello and welcome to this presentation of the STM32WB Power Controller. Power management functions and all power modes will also be covered in this presentation. STM32WB devices feature Flex Power Control, which increases flexibility in power mode management and further reduces the overall application consumption. Run mode can support a system clock running at up to 64 MHz with only 117 microamps per MHz. STM32WB devices support 8 main low power modes. Low power run, sleep, low power sleep, stop zero, stop one, stop two, standby with RAM retention, standby and shutdown modes. Each mode can be configured in many ways, providing several additional subnodes. Note that for RF operation, the system cannot go below standby with RAM retention mode, as a minimum set of contexts needs to be maintained. In addition, STM32WB devices support a battery backup domain called VBAT. The high flexibility in power management provides both high performance with a core mark score equal to 215, together with outstanding power efficiency demonstrated by the ULP bench score equal to 175. The STM32WB has several key features related to power management. Several low power modes down to 30 nanoamps while it is still possible to wake up the MCU with an event on an I.O. For only 3200 nanoamps, 32 kilobytes of SRAM can be retained. A large number of peripherals can wake up from the various low power modes. Dynamic consumption is down to 77 microamps per MHz, executing from flash memory. A battery backup domain called VBAT including the RTC and certain backup registers. Several power supplies are independent, allowing you to reduce MCU power consumption while some peripherals are supplied at higher voltages. Thanks to the large number of power modes, STM32WB devices offer high flexibility to minimize the power consumption and adjust it depending on active peripherals, required performance and needed wake up sources. STM32WB devices have several independent power supplies, which can be set at different voltages or tied together. The main power supply is VDD, supplying all IOs, the reset block, temperature sensor and all internal clock sources. In addition, it supplies the standby circuitry which includes the wake up logic and independent watchdog as well as the radio. VDD is monitored by the BORS circuitry. VDD SMPS supplies the switch mode power supply step down converter. Its output VFBS MPS supplies the CPU with most of the digital peripherals and the SRAMs. The flash memory is supplied by both VFBS MBS and VDD. STM32WB features several independent supplies for peripherals. VDDA for the analog peripherals, VDDUSB for the USB transceiver and VDDRF for the radio. VLCD for LCD drivers can be generated internally or come from an external supply. The internal reference voltage used by the analog block can be output on the VREF plus pin to supply external circuitry for the application. A backup battery can be connected to the VBAT pin to supply the backup domain. The SMPS supplies the digital core and radio LDOs. The SMPS supports switching on the fly. When the VDD supply drops below 2.1 volts, it automatically switches to bypass mode. The SMPS operating mode on and off will follow the device modes. To remove any noise from the SMPS during ADC conversions, software may switch the SMPS mode on the fly. The STM32WB supply configuration is to be selected by hardware. For the best power performance, use the SMPS configuration. For the lowest cost, the LDO configuration can be used. The main power supply VDD ensures full-featured operation in all power modes from 1.71 up to 3.6 volts, allowing it to be supplied by an external 1.8 volt plus or minus 5% regulator. Device functionality is guaranteed down to 1.61 volts, the minimum voltage after which a brownout reset is generated. RF operation is allowed in the full voltage range from 1.71 to 3.6 volts. Other independent supplies are provided to allow peripherals to operate at a different voltage. The VDD SMPS is connected to the same supply as VDD. The analog power supply VDDA can be connected to any voltage other than VDD. When the analog to digital converters or comparators are used, the VDDA voltage must be greater than 1.624 volts. When the voltage reference buffer is used, VDDA must be greater than 2.4 volts. The LCD voltage can be generated internally or provided externally. The USB power supply VDDUSB can be connected to any voltage other than VDD. When the USB is used, VDDUSB must be greater than 3 volts. Note that three IOs of port A, 13 to 11, are supplied by VDDUSB independently from VDD. A backup domain is supplied by VBAT, which must be greater than 1.55 volts. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator, and the 80-byte backup registers. The power supply supervisor allows dynamic power supply management. STM32WB devices embed power management on main VDD, analog VDDA, VBAT supply input, switch mode power supply, VFBS MPS, and USB interface VDDUSB supply lines. The main VDD supervision allows reset management and voltage detection via the power voltage detector, or PVD, when the VDD crosses the selected threshold. The PVD can be enabled in all modes except standby modes. Seven thresholds can be selected by software. The ground out level can be used to provide switching on the fly of the SMPS when VDD drops below the threshold level. On the analog VDDA supply, a supervision circuit selected via PVM detects when VDDA crosses a threshold. The PVM can be enabled in all modes except standby modes. On the VBAT supply, a supervision circuit selected via PVM detects when VBAT crosses a threshold. On the SMPS VFBS MPS supply, a supervision circuit will reset the core when the supply is too low, less than 1.4 volts. On the USB interface VDDUSB supply, ADC performs measurements to verify that the USB interface supply is present. The USB supply measurement can only be enabled in run mode. The power supply supervisor guarantees a safe and ultra low power reset management. STM32WB devices embed an ultra low power brownout reset which is always enabled in all power modes except shutdown mode. The BOR ensures reset generation as soon as the MCU drops below the selected threshold, regardless of the VDD slope. Five thresholds from 1.7 to 2.95 volts are selected by option byte programmed in flash memory. A power voltage detector can generate and interrupt when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby and shutdown modes. Seven thresholds can be selected by software. In addition, an external pin can be used to compare voltages. The BOR consumption with the 1.7 volt threshold is included in the datasheet. STM32L4 MCU embeds four peripheral voltage monitors to detect if the independent supply is present or not. These comparators have wake up from stop mode capability. The PVM1 compares the VDDUSB voltage with the 1.22 volts threshold. The PVM3 compares the VDDA voltage with the 1.65 volt threshold, intended for the comparators and analog to digital converters. The PVM2 and PVM4 are reserved. To guarantee any of the supply sequences on the application, power isolation has been implemented and is active by default. It is the role of software to enable the needed supplies by removing the power isolation. The ADC and DAC voltage references can be provided either by an external supply voltage or by the internal reference buffer. This allows improvement of converter's performance by providing an isolated and independent reference voltage. The VREF plus pin, and thus the internal voltage reference, is not available on the 48 pin package. In this package, the VREF plus is double bonded with VDDA, and the internal voltage buffer must be kept disabled. The voltage reference can be provided through the VDDA pin in this package. The application software can decide to place the SMPS in bypass mode when performing ADC conversion to reduce noise. The battery charging feature allows charging of a supercap connected to a VBAT pin through an internal resistor when VDD supply is present. The charging is enabled by software and is done either through a 5 kilo ohm or 1.5 kilo ohm resistor depending on software. Battery charging is automatically disabled in VBAT mode. The STM32WB system contains three subsystems. The CPU Cortex-M4, the CPU2 Cortex-M0 plus, and the radio subsystem. Each of the three subsystems can operate independently, being in one of its operating modes, C run, C sleep, or C stop. Peripherals will only be clocked when the associated subsystem is in C run mode or C sleep when enabled in sleep mode. The system resources such as RCC, PWR, AIEC, and SRAM2 connected on the shared bus will always be clocked when the system is in run mode. The other peripherals on the shared bus may be enabled to operate with CPU1 and or CPU2. The SRAM1 and QSPI peripherals on the CPU1 bus matrix can only be associated with the CPU1 processor. The other CPU1 bus matrix peripherals may be enabled to operate with CPU1 and or CPU2. The radio system bus matrix can only be associated with the CPU2 processor. The radio system BLE peripheral may operate when both CPUs are in C sleep and C stop mode. In this case, only the system resources on the shared bus are clocked. Each CPU can decide independently which low power mode to use. Stop 0, stop 1, stop 2, standby, or shutdown. Each CPU can decide which IT source or RTC, RF, CPU2 only, GPIO signal will wake it up. When both CPUs enter WFI or WFE, the hardware mechanism executes the compatible request. It selects the highest low power mode compatible with the requirements for both CPUs. One CPU can wake up without the need to wake up the other one if not required. When the STM32WB wakes up from stop X modes in accordance with the interruption source, only the CPU registered for this IT source is restarted. The other one stays in WFI or WFE with its clock stopped. When the STM32WB wakes up from standby modes in accordance with the source, only the CPU registered for this source is restarted. The other one stays under reset mode. Run mode, run range 1, run range 2 and low power run and frequency selection changes are centralized on one of the CPUs to avoid conflicting configurations. This includes selection of the system clocks as well as LP enabled and voltage range and flash memory configurations. Each radio subsystem operates autonomously and will enter and exit low power modes on its own. The radio low power timer is the wake up source for the radio subsystem. When both CPUs and the radio subsystem are in C stop mode, the system will enter the low power mode as selected by the CPUs. According to the requirements of the CPU1, CPU2 and RF systems, the PWR hardware mechanism manages how the STM32WB reaches a given state. That is to say, when CPU1 allows standby mode and CPU2 allows only stop to mode, the system enters stop to mode. Note that only the CPUs can place the system in LP run or LP sleep modes. The radio does not support shutdown mode and must be disabled prior to entering shutdown mode. Power management allows control of the device power supply based on system operating mode. The system operating mode depends on the individual CPUs and radio operating modes. The system is in run mode whenever one of the three subsystems is in C run or C sleep mode. The system enters stop or standby modes when all three subsystems are in C stop mode. In system run mode, the device power supply can be scaled according to the required performance. Up to 64 MHz in range 1, 16 MHz in range 2, and only up to 2 MHz in low power run mode. A CPU enters the C stop mode when executing a wait for interrupt or WFI, or wait for event or WFE with a deep sleep bit set. The system state also depends on the operating modes of the other CPU and the radio system. The CPU1 bus matrix clock is only stopped when the other CPU has no allocated peripherals on the CPU on clock domain, or the other CPU is also in C stop mode. The system may only enter stop or standby mode when both the other CPU and the radio system are in C stop mode. The system only enters standby mode when allowed by both CPUs. When a CPU wakes up from its C stop mode, it has to know from which mode the domains and system have woken up. For this, the CPU has a few dedicated flag bits, SBF D1, SBF D2, SBF, and stop F. These bits inform the CPU about the state of the system and which parts, clock, peripherals may need to be re-initialized. These CX SBT or standby and CX stop F or stop flags have to be tested by the CPU software when waking up from stop or standby modes. They enable the CPU1 application to selectively reprogram its context, RAM, peripherals, and clocks. This figure gives the complete overview of the power modes in relation to the CPUs and radio operating modes. Whenever a subsystem is in C run or C sleep mode, the system is in run mode. Low power stop, standby, and shutdown modes are only entered when all three subsystems are in C stop mode. The low power mode is selected by the low power mode select or LPMS bits. Each CPU has its own low power mode select bits and the system enters the highest consuming low power mode selected. From stop and standby modes, each subsystem can be awakened independently by its own enabled wake-up sources. From shutdown mode and reset, only the CPU1 Cortex-M4 is awakened. It is up to the Cortex-M4 application software to wake up the CPU1 Cortex-M0 Plus and the radio subsystem. Each peripheral clock can be configured to be on or off in run and low power run modes. By default, all peripheral clocks are off except the flash interface clock. The SRAM1 and SRAM2 clocks are always on in run mode. When running from SRAM1 or SRAM2 in low power run modes, the flash memory can be put in power down mode thanks to software and the flash clock can be switched off. The flash memory must not be accessed when it is switched off. Consequently, interrupts must be mapped in SRAM using the Cortex-M4 vector table offset register. Here is a summary of the PWR control related interrupts. Radioactivity flags and interrupts are available to the Cortex-M4 and may be used to control the radio's real-time operation. For example, to prevent flash memory operations from being executed during the radio's critical phase. The run mode thanks to voltage scaling and the low power run modes offer flexibility between required performance and consumption. In run mode range 1, the system clock is limited to 64 MHz and the internal and external oscillators and the PLL can be used. In run mode range 2, the system clock is limited to 16 MHz and the internal and external oscillators as well as the PLL can be used but must be limited to 16 MHz. In low power run mode, the system clock must be limited to 2 MHz. Sleep and low power sleep modes allow all peripherals to be used and feature the fastest wake-up time. In these modes, the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep and low power sleep modes. These modes are entered by executing the assembler instruction, wait for interrupt or wait for event. When executed in low power run mode, the device enters low power sleep mode. Depending on the sleep on exit bit configuration in the Cortex-M4 system control register, the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupt subroutine. This last configuration allows you to save time and consumption by saving the need to pop and push the stack. Batch acquisition mode is an optimized mode for transferring data. Only the needed communication peripheral plus 1 DMA plus SRAM 1 or SRAM 2 are configured with clock enable in sleep mode. Flash memory is put in power down mode and the flash memory clock is gated off during sleep mode. Then it can enter either sleep or low power sleep mode. Note that the I2C clock can be at 16 MHz even in low power sleep mode, allowing support for 1 MHz fast mode plus. The use art and LPU art clocks can also be based on the high speed internal oscillator. Typical applications are sensor hubs. STM32WB devices feature 3 stop modes. Stop 0, Stop 1 and Stop 2, which are the lowest power modes with full retention and fast wake up time to run mode at maximum 48 MHz. The contents of SRAMs and all peripherals registers are preserved in all stop modes. All high speed clocks are stopped except the ones used as kernel clock for peripherals capable of operating in stop modes. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake up from stop mode. System clock on wake up can be the internal high speed and multi-speed oscillators up to 48 MHz with only a 1 microsecond wake up time from SRAM or 5 microseconds from flash memory. Add plus 10 microseconds when SMPS is used. Stop 2 consumption is lower than stop 1 and 0 but supports less active wake up peripherals. When comparing stop modes, stop 0 mode has the highest consumption as it keeps the main regulator on. Stop 1 mode consumption is higher than stop 2 mode consumption but the wake up time is shorter and the number of active peripherals is higher. It is possible to wake up from stop 0 or 1 mode with the USB resume from suspend event or with attached detection but it is not supported in stop 2 mode. The I2C address recognition is functional in both stop modes and can generate a wake up event in case of an address match. Only one I2C is supported in stop 2 versus two I2C's in other stop modes. The UART byte reception is functional in both stop modes and can generate a wake up event in case of start detection or byte reception or address match event. Only the low power UART is supported in stop 2 mode. In other stop modes, all UARTs and the low power UART can generate a wake up event. When clocked by the internal or external low speed oscillator or when clocked by an external pin, the low power timer can wake up the MCU with all its events. In stop 0 or 1 mode, both low power timers are supported whereas only LP-TIM-1 is supported in stop 2 mode. To allow the CPU-1 to re-initialize the clock system when exiting from stop modes, the stop hold function holds the CPU-2 until the CPU-1 has re-initialized the system. To ensure this, a wake up from stop mode interrupt holds the CPU-2 and wakes up the CPU-1 with a wake up hold interrupt. Once the CPU-1 has re-initialized the system, it releases the CPU-2 hold. The standby mode is the lowest power mode in which 32 kilobytes of SRAM-2 can be retained. The automatic switch from VDD to VBAT is supported and the IOS level can be configured by independent pull-up and pull-down circuitry. By default, the voltage regulators are in power-down mode and the SRAMs and the peripherals registers are lost. The 80-byte backup registers are always retained. The ultra-low power brownout reset is always on to ensure a safe reset regardless of the VDD slope. Each IO can be configured with or without a pull-up or pull-down which is applied and released thanks to the APC control bit. This allows control of the input state of external components even during standby mode. The radio IP can wake up the CPU-2. Five wake-up pins are available to wake up both CPUs from standby mode. The polarity of each of the five wake-up pins is configurable. The wake-up clock is HSI with a frequency of 16 MHz. The shutdown mode is the lowest power mode of the STM32WB with only 30 nanoamps at 1.8 volts. This mode is similar to standby mode but without any power monitoring. The brownout reset is disabled and the switch to VBAT is not supported in shutdown mode. The LSI is not available and consequently the independent watchdog is also not available. A brownout reset is generated when the device exits shutdown mode. All registers are reset except those in the backup domain and a reset signal is generated on the pad. The 80-byte backup registers are retained in shutdown mode. The wake-up sources are the five wake-up pins and the RTC. When exiting shutdown mode, the wake-up clock is MSI at 4 MHz. The backup domain allows you to keep the RTC functional and to preserve the backup registers in case the VDD supply is down thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low-speed external oscillator at 32.768 kHz. Three tamper pins are functional in VBAT mode and will erase the 128-byte backup registers also included in the VBAT domain in case of intrusion detection. The backup domain also contains the RTC clock control logic. In case VDD drops below a certain threshold, the backup domain power supply automatically switches to VBAT. When VDD is back to normal, the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the backup battery level. When VDD is present, the battery connected to VBAT can be charged from the VDD supply. Here you can see the summary of all the STM32WB power modes. Three bits are available in the flash option bytes to prohibit a given low power mode. When cleared, an option bit configures reset generation when entering shutdown mode. Another bit configures reset generation when entering standby mode and the last bit configures reset generation when entering stop one or stop two modes. One bit is used to configure the behavior of the BORHX threshold either as a reset as in the STM32L4 family or to automatically switch the SMPS into bypass mode. Note that switching back to SMPS mode when VDD increases depends on the application. Three bits are also available in the debug control register for debugging in sleep, stop, standby and shutdown modes. When the related bit is set, the regulator is kept on in standby and shutdown modes and the HCLK and FCLK clocks remain on to keep the debugger active. This maintains the connection with the debugger during the low power modes and continues debugging after wake up. Remember to clear these bits when the MCU is not under debug because the consumption is higher in all low power modes when these bits are set due to the fact they force the clocks and the regulators to remain enabled. In addition to this training, you can refer to the reset and clock control and interrupts trainings as well as those for all the peripherals with wake up from stop capability.