 Hello, and welcome to this presentation of the STM32 Quad SPI Memory Interface. It covers the features of this interface, which is widely used for connecting external memories to the microcontroller. The Quad SPI Memory Interface, integrated inside STM32F7 microcontrollers, provides a communication interface, allowing the microcontroller to communicate with external SPI and Quad SPI memories. The Quad SPI Memory Interface supports the connection of one or two external memories. This means that data can be transferred over a four or eight-bit data bus in between the memory and the microcontroller. It gives the user flexibility to choose between the number of pins required for connection, six for a single and ten for a double connection, and the performance of the data transfer, four bits for a single or eight bits for a double connection. The Quad SPI Memory Interface offers three operating modes. It is optimized for communication with external memories with support for dual flash mode, allowing access to eight bits in a single reading cycle. It also supports both single and dual data rate operation. The Quad SPI Memory Interface operates in three different modes. Indirect mode, where it behaves as a classical SPI interface, and all operations are performed through registers. Status polling mode, where the flash status registers are read periodically with interrupt generation. And memory mapped mode, where the external memory is seen as an internal memory for read operations. The Quad SPI Memory Interface offers high flexibility in frame format configuration. This flexibility allows it to address any serial flash memory. Users can enable or disable each of the five phases and configure the length of each phase as well as the number of lines used for each phase. The Quad SPI Memory Interface used in indirect operating mode behaves like a classical SPI interface. Transferred data goes through the data register with FIFO. Data exchanges are driven by software or by the DMA controller. Using related interrupt flags in the Quad SPI status registers. Each command is launched by writing the instruction, address, or data depending on the instruction context. A specific mode has been implemented in the Quad SPI interface to autonomously pull the status registers in the external flash memory. The Quad SPI interface can also be configured to periodically read a register in the external flash memory. The returned data can be masked to select the bits to be evaluated. The selected bits are compared with their required values stored in the match register. The result of the comparison can be treated in two ways. In ANDED mode, if all the selected bits are matching, an interrupt is generated. In ORD mode, if one of the selected bits is matching, an interrupt is generated. When a match occurs, the Quad SPI interface can stop automatically. The Quad SPI memory interface also has a memory mapped mode. The main application benefit introduced by this mode is the simple integration of an external memory extension thanks to there being no difference between the read accesses of internal or externally connected memories except for the number of wait states. This mode is only suitable for read operations and the external flash memory is seen as an internal one with wait states included to compensate for the lower speed of the external memory. The maximum size supported by this mode is limited to 256 megabytes. The prefetch buffer supports execution in place. Therefore, code can be executed directly from the external memory without having to download it into the internal RAM. This mode also supports SIOO mode or send instruction only once supported by certain flash memories which allows the controller to send an instruction only once and to remove the instruction phase for following accesses. Delayed data sampling allows users to compensate for the delay of the signals due to constraints on the PCB layout optimization. It allows applications to shift the data sampling time by an additional one-half clock cycle when operating in SDR mode. In DDR mode, the output data can be shifted by a one-half system clock cycle to relax hold constraints. An additional fine-grain delay can be added to the timing of the sampling clock by enabling the delay block dedicated to Quad SPI. The Quad SPI memory interface has five interrupt sources. Timeout, status match when the masked received data matches the corresponding bits in the match register in automatic polling mode, FIFO threshold, transfer complete and transfer error. DMA requests can be generated in indirect mode when the FIFO threshold is reached. The Quad SPI memory interface is active in run and sleep modes. A Quad SPI interrupt can cause the device to exit sleep mode. In stop mode, the Quad SPI memory interface is frozen and its register's content is kept. In standby mode, the Quad SPI is powered down and it must be re-initialized afterwards. The Quad SPI interface of the STM32 MP1 microprocessors is one of the supported boot sources. It can be used in a dual Quad configuration where one port is hooked on a serial NOR flash memory for the initial steps of the boot sequence and the second port is connected to a serial NAND flash memory which embeds the Linux kernel and the file system and hence can be used as a mass storage by the application. Because of the high speed supported by the interface and the very low pin count such setup offers highly optimized system integration and cost efficient solution. You can refer to the training slides related to the RCC, interrupts, DMA and GPIOs for additional information. The Quad SPI interface is fully compatible with the one available on the STM32 L4 and STM32 F7 series allowing a straightforward reuse of applications developed on these devices when the interface is managed by the ARM Cortex-M4 core.