 Hello, and welcome to this presentation of the STM32 Universal Synchronous Asynchronous Receiver Transmitter Interface. It covers the main features of this USART interface, which is widely used for serial communications in embedded systems. The USART is a very flexible serial interface that supports asynchronous UART communication, SPI or Serial Peripheral Interface Master Mode, and LIN or Local Interconnect Network Mode. It can also interface with ISO, IEC 7816 smart cards, and IRDA devices. It also provides certain features that are useful when implementing modbus communications. Applications making use of the USART benefit from the easy and inexpensive communication between devices, which only requires a few pins. The USART is a fully programmable serial interface featuring the following configurable parameters. Data length, parity, number of stop bits, data order, baud rate generator, and configurable oversampling mode by 8 or by 16. You also have the option to use basic RS232 flow control with CTS or clear to send and RTS or request to send signals. The RS485DE or Driver Enable Signal is also supported. The USART supports a dual clock domain allowing baud rate programming independent of the peripheral clock or PCLK. This also allows the peripheral clock to be throttled along with the core clock without disrupting communications. The USART features a multi-processor mode which allows the USART to remain idle when it is not addressed. In addition to full duplex communication, single wire half duplex mode is also supported. The USART also offers many other features including auto baud rate detection, receiver timeout, and supports several modes which will be described later in the presentation. This is the USART block diagram. The USART clock or FCK can be selected from several sources. System clock, peripheral clock or APB clock, the high-speed internal 16 MHz RC oscillator, or the low-speed external 32.768 kHz crystal oscillator. TX and RX pins are used for data transmission and reception. N-CTS and NRTS pins are used for RS-232 hardware flow control. The driver-enable or DE pin, which is available in the same IO as NRTS, is used in RS-485 mode. The clock output or SCLK pin is dual purpose. When the USART is used in synchronous master mode, the clock provided to the slave device is output on the SCLK pin. When the USART is used in smart card mode, the clock provided to the card is output on the SCLK pin. The USART has a flexible clocking scheme. Its clock source can be selected in the RCC, and can be either the PCLK or peripheral clock, which is the default clock source, or the HSI, LSE, or system clock. The registers are accessed through the APB bus. The kernel is clocked with FCK, which is independent from the APB clock. The USART receiver implements different user-configurable oversampling techniques for data recovery by discriminating between valid incoming data and noise. This allows a trade-off between the maximum communication speed and noise clock inaccuracy immunity. Select oversampling by 8 to achieve higher speed, up to FCK 8. Where FCK is the USART clock source frequency. In this case, the maximum receiver tolerance to clock deviation is reduced. Select oversampling by 16. Over 8 equals 0 to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to FCK 16. The maximum BOD rate that can be reached is 27 Mb, when the clock source is at 216 MHz, and oversampling by 8 is configured. With other clock sources and or a higher oversampling ratio, the maximum speed is limited. The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. The USART supports 7, 8, or 9-bit data lengths. A frame starts with one bit, where the line is driven low for one bit period. This signals the start of a frame and is used for synchronization. The start bit is followed by 7, 8, or 9 data bits. If parity control is enabled, the parity bit is transmitted as the last data bit and is included in the data length count. Finally, a number of stop bits, 0, 1, 1.5, or 2, where the line is driven high, end the frame. The standard frame was described in the previous slide. This slide shows an example of 8-bit data frames configured with one stop bit. An idle character is interpreted as an entire frame of ones. The number of ones will include the number of stop bits. A break character is interpreted on receiving zeros for a frame period. At the end of the break frame, two stop bits are inserted. The USART supports full duplex communication, where TX and RX lines are respectively connected with the other interfaces, RX and TX lines. The USART can be configured to follow a single wire half-duplex protocol, where the TX and RX lines are internally connected. In this communication mode, only the TX pin is used for both transmission and reception. The TX pin is always released when no data is transmitted. Thus, it acts as a standard I-O in idle or reception modes. This means that the I-O must be configured so that the TX pin is configured as an alternate function open drain with an external pull-up. In RS-232 communication, it is possible to control the serial data flow between two devices by using the NCTS input and NRTS output. These two lines allow the receiver and transmitter to alert each other of their state. The following figure shows how to connect two devices in this mode. The idea is to prevent dropped bytes or conflicts in case of half-duplex communication. Both signals are active low. For serial half-duplex communication protocols like RS-485, the master needs to generate a direction signal to control the transceiver or physical layer. This signal informs the physical layer if it must act in send or TX or receive or RX mode. In RS-485 mode, a control line is used. The driver-enabled pin is used to activate the external transceiver control. DE shares the pin with NRTS. To simplify communication between multiple processors, the USART supports a multi-processor mode. In multi-processor communication, it is desirable that only the intended message recipient should actively receive the message. The devices not being addressed are put into mute mode. The USART can enter or exit from mute mode using one of two methods, idle line detection and address mark detection. The USART can also communicate synchronously. It can operate as an SPI in master mode with programmable clock polarity or CPOL and phase, CPHA. The clock is output on the SCLK pin. No clock pulses are provided during the start and stop bits. The USART can be used in smart card mode based on a half-duplex communication. The clock is output to the smart card on the SCLK pin. It supports the T equals zero protocol and provides many features allowing support for T equals one. Both direct and inverse conventions are supported directly by hardware. The USART supports IRDA specifications, which is a half-duplex communication protocol. The data from and to the USART is represented in an NRZ or non-return to zero format, where the signal value is at the same level through the entire bit period. For IRDA, the required format is RZI, return to zero inverted, where a one is signaled by holding the line low and a zero is signaled by a short high pulse. The SIR transmit encoder modulates the non-return to zero or NRZ transmit bit stream output from the USART. The SIR received encoder demodulates the return to zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the USART. The USART only supports bit rates up to 115.2 kilobits per second for the SIR end deck. In normal mode, the transmitted pulse width is specified as 3 sixteenths of a bit period. The USART receiver is able to detect and automatically configure the BOD rate based on the reception of any one of the following characters. The received character can be any character starting with a bit at one. In this case, the USART measures the duration of the start bit from falling edge to rising edge. Any character starting with a 10xx pattern. In this case, the USART measures the duration of the start and of the first data bit. The duration is measured from falling edge to falling edge, ensuring better accuracy in the case of slow signal slopes. 0x7f character frame. In this case, the BOD rate is updated first at the end of the start bit, then at the end of bit 6. Or a 0x55 character frame. In this case, the BOD rate is updated first at the end of the start bit, then at the end of bit 0, and finally at the end of bit 6. In parallel, another check is performed for each intermediate transition of the RX line. The USART supports a receiver timeout feature. When the USART doesn't receive new data for a programmed amount of time, a receiver timeout event is signaled and an interrupt is generated if enabled. The USART receiver timeout counter starts counting from the end of the first stop bit in case of 1 and 1.5 stop bit configuration. From the end of the second stop bit in the case of 2 stop bit configuration. And from the beginning of the stop bit in case of 0.5 stop bit configuration. Several events can provide an interrupt. The transmit data register empty flag is set when the transmit data register is empty and ready to be written. The transmit complete flag is set when the data transmission is complete and both data and shift registers are empty. The CTS flag is set when the end CTS input toggles. The receive data register not empty flag is set when the receive data register contains data ready to be read. The idle line flag is set when an idle line is detected. The character match flag is set when the receive data corresponds to the programmed address. The receiver timeout flag is set when there is no activity on the RX line for a programmed duration. The end of block flag is set when a complete block is received. The lin break flag is set when a lin break frame is detected. And the DMA request can be generated when receive buffer not empty or transmit buffer empty flags are set. Several errors can be generated. The overrun error flag is set when an overrun error occurs. The parity error flag is set when a parity error occurs. The framing error flag is set when a framing error occurs. The noise error flag is set when a noise is detected on the received frame. The auto-bod rate error flag is set when the bod rate measurement failed. The use art peripheral is active in run and sleep modes. The use art interrupts cause the device to exit sleep mode. In stop mode, the device is not able to perform any communication. In standby mode, the peripheral is powered down and it must be reinitialized after exiting standby mode. The STM32F7 devices embed eight use art instances. Use art 1, 2, 3, and 6 have a full set of features. Instances 4, 5, 7, and 8 do not support synchronous and smart card modes. This is a list of peripherals related to the use art. Please refer to these trainings for more information if needed. General purpose input outputs, reset and clock controller, power controller, interrupts controller, and direct memory access controller.