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Published on Oct 19, 2015
When it comes to high speed design, the name of the game is understanding and controlling impedance…
At first glance, you may wonder why ICD put together software that seems to address 2 nearly unrelated areas. The stack up planner addresses the layers. The PDN planner addresses the use of capacitors. What gives?
When we really look at high speed design, we are dealing with the issue of the effect of impedance, both on the traces and on the power provided to the board. The trace impedances are heavily influenced by the layer stack up.
On the power planes, we also deal with impedances. Any noise that makes its way onto the Power Distribution Network (PDN) (a.k.a the power planes) needs to be given a low impedance path to the ground plane, regardless of the frequencies of the noises. Thus the need to determine which values of capacitors are needed, what kind, and how many. The PDN Planner provides over 6500 capacitors in the library. More will be added as they become available. The user can add capacitors to the library as well.
The ICD stackup planner provides accurate impedance information through its built-in field solver. By using the information in the stack up planner, the PDN planner can, in turn, provide accurate information for all noise frequencies of concern. With the ICD stack up planner, the user has access to a library of over 20,000 materials (core, prepreg, and solder mask) up to 100 GHz.