 So, welcome to this lecture on advanced digital system design in the course digital system design with PLDs and FPGAs, in the last lecture we have looked at how to go about designing a complex system like a CPU. We have taken an example of an 8 bit microprocessor, we have said that it cannot be designed in a flat way in one shot, it has to be partitioned into the functional blocks which requires domain knowledge and we have to decide on the interface between this block. Then at the next level I mean at that level top level we have to decide the function timing all that, at the next level we will handle each block separately and try to design and go to the third level and when we are kind of we end up with the known blocks like registers multiplexers and counters, then we can stop you know that the neat way of designing. In the industry we call it RTL design, the same it is same what I am talking about. So, we have looked at the example of the CPU we have seen the level 0 block diagram level 1 partition and then for the level 2 we have picked up 2 blocks, one was the register CPU register which is fairly simple. Then we have taken a program counter and designed it in detail and we have also discussed the division of the data path and the controller to bring clarity. So, that is what we have covered in the last lecture and today we are going to look at the behaviour of the controller and we will try to from that behaviour from that idea we will try to kind of come out with the structure for the controller and look at the properties and check what a whether a generic architecture which fits for all cases whether we can come out with such a thing. You know from this we are working out little bit backwards from an example to the basic normally in a textbook the other way is done and which is sometime difficult to kind of understand at the beginning because we learn something formally the structure and you try kind of later on apply or sometime the textbook does not show the serious application it only deals with very simple cases and then it does not bring clarity that is why I am kind of going from an example and kind of working backwards and that brings clarity so that is the idea. So, before turning to today's part on the controller we will have a brief look at the last lectures part then we will move on to today's part. So, let us move on to the slides of the last lecture and so we have looked at an 8 bit microprocessor but the thing was that it has 8 bit ALU data bus 16 instruction 64 address space 64 kb address space which means 16 bit program counter and stack pointer the controller is hard wired on microcoder no separate IO space and so on okay. So, and we said that we have to partition this in the blocks with interfaces we have to do a top down design at each level we have to handle the functional timing and the electrical aspects of it and so we have looked at the top level which is CPU with clock reset interrupt as input read bar write bar address as output and data as a kind of bidirectional pin and we said this is a kind of we have decided now you have to decide on the functionality we said this is there is no kind of pipelining. So, it fetches then decodes execute then it goes and fetch it so it makes it multiple clock cycle CPU for one instruction to execute it takes multiple clock cycle it is not very current design you know the current nobody design like that the CPU can be designed for a single clock cycle operation in most cases. So, but we are just trying to kind of grasp the basics so we stick with it and when it comes to the timing spec and of course you have to decide what are the instruction which are supported what is the instruction format and so on. But we will not get into that kind of detail and our idea is in the process of you know design how the design process goes on and this you can refer to some book good reference book some books on microprocessor or you can computer architecture there is a good book by Hennessy and Patterson on computer architecture two volumes are there both deals with the CPU design in detail and here the clock reset interrupt as some basic timing the clock may have some duty cycle the frequency the reset as some timing interrupt will have you have to decide whether it is a level triggered edge triggered or both and what is the timing pulse width and so on. And one important timing detail is the bus cycle how this bus is kind of behaves whether it is synchronous or synchronous how many clock cycles it takes and so on. So, and these are the and the electrical spec because these are to kind of support lot of load and this should have enough sourcing and syncing of the current and we have seen the second level of partition level one wherein there is an internal data bus, instruction register, decoder, temporary register, ALU, set of registers, program counter and stack pointer. Everything is connected to a single bus in the current high performance CPUs it may have multiple buses so that and all the high performance CPUs will have multiple buses that means the registers can feed the ALU, ALU can feedback the register. And while that is going on instructions can come on to the instruction register and so on okay or an instruction fee 4 or a queue. So, so many things can go in parallel and that will be synchronized and so on. And we said there is a difference one is a data path where the data moves or the computation happens and there is a controller which sequence all the operation okay. So, this partition is very good because when you functionally partition it you do not have to worry about the sequencing of operation. You can concentrate on the functionality concentrate on the interface and the timing details can be worked out later you know like in what sequence these condo signal come that can be decided later. And the controller job is to give the sequence operation give the condo signal latch signal enable signal and select a max path to enable data into a particular path and so on. So, that is a job of the controller and we said in a synchronous case you need only one controller if everything is synchronous. But if there are kind of two concurrent activities which is not synchronous to each other then you can controller to handle two concurrent activities which are not synchronous okay. And but in any case in a very complex scenario it is very difficult to manage with a single controller for modularity ease of designing and debugging and testing and all that it will be ideal some time you have multiple controllers handling the multiple parts and a top level controller coordinating with the bottom level controller. So, as in a top down approach you can even imagine you could have the second level partition some of the blocks together having you know separate controller and so on that can be thought of one can think of a hierarchy of controller. So, there is a top level controller which is you know coordinating the second level controllers and so on. So, that is a data path and controller and we have picked up an example of a register and we have designed it seen the design in detail. So, the idea of register is that it should be connected output should be connected to the data bus when it is enabled the data should come. Similarly, when the latch signal from the controller comes and the clock comes the data get latched and we have seen a kind of circuit for that say this is a possible circuit 8 flip flops clock is common and input and output is connected together through a tri state gate to the same data bus. And the clock and the latch signal is ended together so that when the latch signal comes only then the clock comes. So, at this level we know all the components flip flops and gate and registers the design is over ok. And that can be coded in a VHDL or verilog things like that but as the node says there is a little timing issue with it because we are ending it with not proper there could be multiple pulses here and we will see that later you know that issue can be handled later. So, there is another possibility which avoids it that means you do not do anything with the clock path clock goes continuously and that is problematic because every clock the data gets latched so we have to take care of that. So, the idea is to put a 2 to 1 MUX and when the latch signal comes the input goes directly when it is 0 it is recirculated ok that is a basic idea. And the next thing we have looked at was a program counter which has various operation the data when a jump or a call comes the address has to be latched in you know byte by byte when there is a call the return address is stored back again 16 bit register byte by byte it has stored back and then the latch signal. So, there are 2 8 bits registers inside which are separate I mean this has to be handled properly there are different input path one is from the data one is an increment path one is a reset address one is interrupt address. So, that is this input select output select is when the both address need to be transferred to the data bus you have to select byte by byte. So, that is the address output select then they enable for the output to be connected to the data bus and that drives the address bus and we have seen a possible design. So, you have 2 8 bit registers which has latched same latch and we have a temporary register to transfer the least significant byte because the address come least significant byte first and the most significant byte. So, first it is transferred which has a latch signal separate from the controller then when the MSV comes this particular green path is selected and both together this least significant byte and the most significant byte coming on the data bus is latch simultaneously on here. So, the latch signal is common for both and when it is need to be incremented it is incremented this way and this red and blue path is selected and is latch packed. When the reset comes this address is loaded parallely interrupt comes that is loaded and when the program counter output need to go to the data bus this particular MUX operates with the enable and this is the address bus being driven by the program counter. So, it basically means 3 8 bit registers 2 4 to 1 8 bit MUX 2 I mean 1 2 to 1 8 bit MUX 8 tri-state gate and 1 16 bit 2 to 1 MUX the design is over this can be easily coded ok. So, that is how we design and we said so, essentially it has to be top down design any complex system and you should have the domain knowledge and you should at each level you have to look at the functionality timing electrical characteristics may be power dissipation where it is critical. Nowadays everything most devices are mobile or which can be kind of transported and that needs a battery and which is better if the power dissipation is controlled. And there are many devices now sensors which is kind of installed in one place which is which is supposed to work over long years. So, the low power dissipation is very important. So, let us come to today's part today's part we are going to look at the controller this part what is the behavior of it what is the structure of it may be possible an introduction about how to go about designing it you know that is our focus today. So, for the sake of illustration let us take an instruction ok. Because basically a CPU is executing instruction and depending on the instruction these control signals are generated ok. So, now I am going to take one instruction ok. So, but that can be extended to similar instruction and other instruction. So, I am only kind of discussing a part of the game, but that is enough to capture the idea. So, let us take an instruction like add A and B ok. That means we are essentially adding the content of the register A and the content of the register B and putting the result back to the content of A. So, it is a kind of two operand instruction like the indel assembly language instruction or the machine language instruction where when you say add A B it is nothing but A plus B is loaded to A ok. So, let us see what happens when such an instruction is executed. So, it is simple you move the content of A to the temporary register then move the content of B to this temporary register 2. Then you give select the ALU operation that you say that it is add operation ok. You can imagine there are multiple arithmetic and logic units doing computation which is all parallel which is MUX through a MUX and you can think of this as selecting the path in the MUX ok. This is a select line of the MUX which is choosing and the connecting the output of the appropriate block to the output of the ALU ok. And this enabled is a tri-state gate because only one device can drive the bus. So, that has to be enabled when the result is. So, you give the operation selection then you enable it then register A is loaded with that result ok. So, that is a kind of macro step of adding A and B. But let us look at little more detail because our idea is the controller has to generate appropriate condo signal. So, we have clarity in terms of the condo signal ok. So, the first operation is moving the content of A to the temporary register 1 ok. So, what we need to do is that we have to enable the register A output. So, you give A1 to register Ae which is register A enable then the data comes on the data bus ok. And that goes to all inputs all the register input goes. But then the controller has to give a pulse to the TR1L which is a temporary register 1 latch signal. And it has to be in synchronous with the clock very important then the clock edge comes and the data gets latched ok. Unless it is not synchronous it is not going to happen. So, when it is 1 when it is high the active clock edge should come ok that should be taken care. And then you disable it ok. So, that is the game. Now I can tell you a very simple idea. So, what we should do is that we give a pulse to RAe and we can give the same pulse to the TR1L assume that it is synchronous with the clock. Then the A value is enabled because it is a pulse and it comes here and the clock edge comes it gets latched and the pulse goes to 0 it is disabled ok. Similarly, you move the register B content into the temporary register 2 enable A give the same pulse to the latch signal clock comes it gets latched and when the pulse goes 0 this is cut off ok. Now specify the add operation and that can be some bits from the instruction directly there is may not be kind of decoding is not required you can kind of maybe you can kind of you know encode if you need in another fashion. But may not be required same pattern can be given here from the opcode and that can select the operation or there is a kind of a further encoder which encodes into some less number of bits which can come here and select this operation. And this is enabled after a clock period after a wait and this is enabled and that same signal is given to the register a latch same signal means the controller will generate at the same time another signal of the same timing. And so it is enabled and on the active clock edge that is latched and when the pulse goes 0 that is disabled and the add operation is done you know. So A to TR1 B to TR2 add operation enable and the result back to A. So enable is given a pulse latch is given a pulse upon the clock it is moved it is disabled. Register B E is given a pulse TR2 L is given a pulse and upon the clock it gets latched here and that is disabled. And this is given a selection this is enabled same pulse is similar pulse is coming at the latch signal and the data comes here it gets latched and it gets disabled automatically. So that is a kind of sequence. So I have written that here in detail move A to TR1 move B to TR2 ALU operation wait and ALU output register A okay. So now what I am showing is I am showing a possible timing waveform which will achieve this. So assume there is a clock you know going like that which is a say assume a square wave clock. Now this is the timing okay these are two separate output instead of you know drawing it separately I am showing it together. I mean this is separate output coming from the controller this is not the same signal do not assume that it is same signal it is two separate signal with the same pulse okay. So A enable and TR1 L gets similar pulses like it comes with the delay with respect to the active clock edge like that. So at this point the data is A is enabled data is flowing on the data bus. So it has enough time before the active clock edge comes. So if you go back to this like when you enable something it takes some time for the tri-state gate to get enabled and propagated and set up at the input of the register then only the clock can latch it. So that is taken care of by this kind of timing. So we are enabling it here at this point data start flowing and it will be ready at the input and when the clock comes data get latched and the output is disabled okay. Similarly the B is enabled at this point and in the temporary register 2 it is latched and B is disabled. And I am not specifying the early operation but that can be taken from the opcode with an encoding if needed. And this is ALU is enabled and the ALU is enabled and that data is coming here and gets latched to the A and it is disabled okay. So this symbol scheme achieve this operation instruction add A, B okay. Now the question is of course you know there are other instructions and one has to maybe if say you can imagine say add BC add AB everything is same. So all that can be easily captured by this behaviour maybe subtract again things are same only thing is that the subtract operation is different. So the controller which is designed the part of the controller which does this can be generalized to do many other things okay. So that is the basic idea but for you it might look little convoluted that I am kind of orchestrating a scheme very clearly I am pushing the edge little bit to the right hand side so that you know the clock edge comes here. But you will see that what we practically come out with will match this at this point you take it I mean you may think it is a kind of manipulation but it will turn out to be true correctly like the structure will mimic this behaviour okay and also you should know that we are kind of going to have everything in terms of integral number of the clock cycle okay. So the basic unit of control is a clock period okay nothing less than that. So we will have a pulse of at least one clock period not half clock period. So everything will be decided per clock cycle that should be kept in mind. Now the question is that can the controller be a combination circuit okay because we have studied combinational circuit and sequential circuit. So we know that for a combinational circuit if given an input say n input it can produce an m output but it cannot definitely produce given an n input to a combinational circuit it cannot produce a pulse like this you know every clock like for 3 clock periods. So this controller cannot be a combinational circuit it has to be a sequential circuit okay. It is like given an input it generates a sequence of pulses okay. In this case it looks very neat one pulse then the second pulse and third pulse and so on. So the question is that what type of sequential circuit can generate such a pulse okay. Like the answer is that unfortunately we have studied only the counter now synchronous counter. So I want to straight away ask can we have a synchronous counter generating this kind of pulses you know that is the question we are asking can we use a counter to generate timing pulses. A mode 3 counter like we have a counter which is designed like this you know you have a state flip flops which is decoded with the input to generate the next count. Can we have a counter generating a mode 3 counter generating this kind of pulses okay. So like this thing and we know that a mode 3 counter will count 0 1 and 2 and it has 2 bits okay. But what we require is separate outputs okay. Now so why not we decode this particular pulse from that 00 count okay and we decode this 2 pulses from 01 and we decode this 10 I mean these output from the count 10. So that is the basic idea. So we take a counter and what we do is that we do not need 00, 01, 10 we need some outputs. So what we do is that we put a combinant circuit here and we generate the output as a decode of the state here okay. So when it is 00 we will generate 2 outputs 01, another 2 outputs 10, another 2 outputs okay. Now we have to design this output logic this is called output logic which the input is a present state and the output is the various outputs we need. So we can write the truth table for the output logic in this case. So we have input which is present state in this case 2 bit Q1, Q0 and there are 6 outputs okay. I said for convenience I have shown these as together but it has to be separate because luckily in this case these are similar pulses. But if you are adding B to C then the TR1 latch and the B will have the same kind of pulses. So it has to be separate. So we know that in 00 at least for this case these 2 as 1 in 01 this register B enable and the TR2 as 1 and in the 10 ALE enable and the register A latch as 1 okay. Now it is very simple for each output you pick up 1 form the minterms in terms of Q1, Q0 optimize it come out with the equation. So like for an example we take this register A enable that you will get as a function of Q1 and Q0 which is a present state similarly you can work out for all other 5 outputs. So we can say output is a function of the present state you know. So the output is decoded from the present state and then we say output is a function of the present state okay. So that is how we generate this timing process it is complex because we are only considering now one instruction we have to kind of combine all similar instruction and there may be this mode 3 business may not work it may have to count in a very complex way making branches and so on depending on the various inputs. So you can imagine these are various instruction various group of instruction these inputs and depending on that it will make lot of transition and each transition is decoded each state is decoded to produce the output by this output logic. So from a counter we have graduated to a next level having another logic at the output which is decoding the present state and producing the various outputs okay. Now you see I have the before coming to this part this kind of delay now that this enable and the latch is delayed by some time with respect to active clock head looked artificial. But now you look at the diagram we are putting a logic here. So the clock comes and this present state will change after TCQ time delay. Now the output will come after the clock head after TCQ and output logic okay. So when you implement when you use such a structure to generate this kind of outputs then you can see that there is a delay with respect to the active clock head which is nothing but TCQ plus T output logic. So everything will be delayed and which is required unless it is delayed this edge cannot you know latch the data. So it is very important that there is such a delay and that is automatically achieved by this particular structure okay. Now the next question is that we have come out with a structure which is an extension of a synchronous counter. We have added an output logic to the synchronous counter the next question we ask is fine it can do add A plus B can it do everything what we require. You know can we generate whatever timing signals required say example let us forget about particular instruction let us pose a question that okay. Now the register A enable and TR1L has a different pulse shape or a timing. So at the first clock period it is high then it is 0 then in the third clock period it is high. Similarly for the second set it is high for consecutive 2 clock cycle which is second clock cycle and third clock cycle. Let us forget about what instruction it implements I am only pausing a hypothetical question you can form any kind of pulses okay. The question is that can we generate whatever timing signals required. So if you look at this particular structure we can say very definitely yes okay because we are decoding the present state. So it is not necessary that you have to decode like a pulse 1 in the first clock you know clock cycle 00 like you can say let us make this decode this particular signal as having 1 in the 00 and 1 in 010. So then that is done. So it is very simple that yes it is possible A register A enable is nothing but Q1 bar Q0 the 00 or say Q1 Q0 bar that is 1 0 okay this is 00, 01, 10. Similarly when you come here it is nothing but 01 and 10. So you get equation for that register A enable in that case is Q1 bar Q0 bar Q1 Q0 bar which will be kind of you know you simplify to Q0 bar okay. Similarly register B enable if you look at this it is Q1 exclusive or Q0 bar. So what I want to convey is that this particular structure is very generic you know whatever may be the timing requirement in terms of clock period this structure can generate it you know you do not have to worry saying that the instruction is different or it is a very complex thing it is something to do with the program counter the call has come. So the current address has to be pushed to the stack new address need to be stored how this can be how this is possible and all that okay. So maybe the diagram I have shown requires some modification for little bit modification probably I do not know maybe some shadow registers are required but whatever it is it can be done from a controller perspective number of it requires to generate different type of pulses and this structure is able to generate it. So what it comes to is that when you talk about a controller this structure or this architecture is very generic it can be used for as used as any controller like you have a multiplier you need a controller and then this can be used only thing is that depending on the application this next state logic will change because depending on the input and application this transition will change and at each state the output a number of outputs and the timing of output will change so this logic will change. So depending on the problem depending on the timing this next state logic will change output logic will change number of flip flops will change the transition will change but we can say this is the architecture of a controller. General architecture of a controller only thing we have to decide for a particular problem is this how many bits are required what is the next state logic what is the output logic okay. So that is the conclusion. So this is called a finite state machine because this machine goes through the finite number of states it transit through the finite number of states in a complex way it is not that it likes a counter it can take branching decision it comes to a state then depending on an input it can go branch to a one particular state or branch to another state another set of states and so on okay. So the transition can be complex unlike in a counter so that is it it is very generic the next question is that is a counter need to be ordered is a state in need to be ordered that means we said for add instruction we said it count 0 0 0 1 and 1 0 does it have to be ordered can we count 3 0 and 1 or a 3 0 and 2 yes it does not matter it can transit the state does not matter because we are worried about the output and given some set of inputs we need a sequence of output and we do not care too much about how this counter part keep track of the state as long as it is distinct state for each step then we can decode accordingly. So it is not very important how the state particular numerical value of the state okay need not be very ordered it can be arbitrary so that problem is called state assignment okay. So we care only about inputs and output state can be assigned with useful values and that could be of some use okay. Maybe question is that if you assign the states in a particular order maybe this logic get minimized or this particular logic get minimized okay. So the state transition the numerical values are of no consequence we can decode we can change the decoding of two table of next level logic and two table of output logic to reflect the state you are assigning the designer is assigning and as I said it can be assigned to reap some benefit out of that assignment like having the minimal area for the logic and so on okay or to solve some timing problem okay. And so what is what it means to design and as I said this is called a finite state machine or FSM okay. So that is the expansion of this finite state machine. So basically it means that you have some inputs depending on the inputs the transition happens state transition happens because in an add a b instruction we have three states which is transited and each state generate some output. So this is the specification okay this is the algorithm and we while designing at the end of it we design this next state logic and output logic. So the what it means to design an FSM is that you have a specification of the input the state transition and the output or the sequence and then from there you come and design the next state table and output table okay. So that is the basic what it means to design a finite state machine. So the basic finite state machine or controller is nothing but a finite state machine idea is that there is a counter part which go through various states it is a material whether it goes through in a particular sequence and states are decoded to generate various pulses to control the data path okay. Maybe this control signal will select the MUX give a clock signal to a latch will enable clock to a register, increment a counter and so on okay that is what these output signals are used for okay. They do the sequencing operation of the data path like as I said enabling something in the register, incrementing a counter, selecting a multiplexer path and so on of course these are the important thing we do with the sequencing pulses okay. So let us come back to the slide so here we look at this particular architecture and you see here the output is generated as a decode of the present state okay. Now in some cases it is convenient we will see that later what is the advantage of doing that or when we can do that. Sometime it is convenient to generate the output not only as a decode of present state but as a function of both present state and input. So you can imagine this input is coming here and you decode the output as a function of present state and the input okay. So it may happen that some outputs are decoded from the present state, some outputs are decoded from the present state and the inputs okay. Now when you decode an output from the present state it is called Moore machine or Moore output this is after the mathematician Moore and when you decode an output as a function of present state and input then it is called Milley machine okay. So we have two types of output one is a Milley output when output is decoded from the present state and input a Moore output when the output is decoded from the present state only. So we can modify that earlier architecture or structure that where the output logic gets not only the present state but also the inputs okay. So we say here when you say the decoding the next state logic decode the next state as a function of present state and inputs and the output logic when generate some outputs as a function of present state which are called Moore outputs and the output logic decode some output as a function of present state and inputs which is called Milley outputs okay. Now I should mention that most of the textbooks you have studied in the undergraduate program talks about a Milley machine and a Moore machine okay. It is kind of very kind of simplistic view many a times you would have noticed that the finite state machine you have kind of seen example is just with many a times one input and one output okay. In such a case it is very easy to call the Milley machine because there is only one output which is Milley output or one output which is Moore output. So you can call a Moore machine and a Milley machine but in practical cases the controller or state machine has lot of inputs lot of outputs. So you cannot call kind of you know Milley machine and Moore machine because even if there is one output which is Milley then you will end up calling that the Milley machine that could confuse the design. So let us keep this kind of distinction. Now one thing to notice is that now you look at this next state logic it the input to the next state logic is the present state and the input and it decodes the next state okay. Now if you look at the output logic the input way there is a present state and the inputs and it decodes output okay. Now why do not we like if you look at the inputs are same. So why do not we combine this together in a block and we call it logic the output of the logic is next state and the outputs okay. So we get a two block view which is nothing but we are combining the next state logic and output logic. The logic looks at the input and the present state it decodes the next state and is also decode output. So it is a very useful view because for when we analyse the timing when we do the VHDL coding this kind of three block view and the two block view is useful because when we analyse maybe while doing the timing analysis this is easier to look because it is much simpler it captures all the kind of data various paths together and when you VHDL code maybe you will code this separate and this separate but there could be advantage in coding the logic together in a various ways. So these two views are very useful please keep this in mind and these two views and as I said any finite state machine the architecture is same only the logic differs depending on the application depending on the input output timing the logic changes and the number of flip-flop change transition change the architecture essentially remains same okay. So that is the description of the two block. Now let us look at the timing issue of the state machine the finite state machine we will use the two block view because it is a much more kind of concise. So one important thing to look is that there are now two paths from a register output through the next state logic to the register other register or the same register we cannot say like if there are three flip-flops three I mean three inputs three output then there could be nine three into three nine distinct path maximum okay. But very important thing to notice is that there is another path from the through the flip-flop through the output logic to the output okay. So when we consider the maximum clock frequency if you consider only the clock to clock it is not useful because the clock comes then it propagates here propagates here and the setup time is met say we say tcq plus t next state logic ts should be kind of less than the clock period or the clock period should be greater than this. But suppose if the tcq plus t output logic is even greater than that the transition will happen correctly but the output would not appear at the output. So what I say is that we will say the clock period the minimum clock period should be maximum of the tcq plus t next state logic plus t setup time comma or tcq plus t output logic because output has to appear at the output okay. And normally in most cases if it is kind of close together we can imagine that this is kind of larger than this quantity. But one issue is there we do not know where this output is going suppose if this output is going through a combinational logic and going to another register as part of the control then in that case we have to analyse the path from this particular register through this output logic through the combinational logic to the destination register okay. So since I do not have any a priori information about that I have written that but in real life there could be term like t logic plus t setup time of the destination register may be coming here that you should not forget okay. So the slack is the margin we give and the whole time violation is that the tcq min plus the mean t next state logic min should be greater than the whole value okay. So that the like when the clock comes because of the clock the data at this point changes but that should change only after the whole time as I said it is with respect to same clock edge okay. So that is the essence of it now. So that is basically the timing so when we maybe the controller design we can take in the next lecture so or maybe we can look at this. So the question is that when you implement a control algorithm basically what we have is an input output timing diagram okay and from there we have to kind of decide depending on the input what are the transition okay and in each transition what are the outputs required okay. So normally you have a verbal description and a timing diagram from there we have to with respect to input we have to come out with various state sequences and output at each sequence and at that point there are a lot of possibility is not that there are only unique kind of way of solving a control problem. So there could be different ways you can solve it something could be optimal. So essentially what I am saying is that it is very difficult to go in one step from a waveform to a next stage logic and output logic. So we need to play with it and we need to design that refine that algorithm and you know that in software before writing the code we have an algorithm then we use the flow chart and all that. So when we try to think of control algorithm it is good if we can play with the graphical it is graphically so that we can capture the basic idea. So similar to the flow chart we do something called a state diagram in designing this state machine that helps us to kind of visualize the control algorithm refine it remove the redundancies and group them and all that you know that is a thinking process with graphic symbols capturing basically it should specify what are the inputs with respect to input what are the transition to the state and in each state what are the output this particular diagram should capture that we will see in the next class and it is called the state diagram or sometime it is called ASM chart algorithmic state machine whatever you call that is basically the idea of designing a control algorithm and that part we will handle it in the next lecture. So today what we have looked at basically is one quick run basically we have looked at an instruction called add AB and we have seen what are the essential macro steps involved in executing that and we have seen what is a corresponding waveform for that of the signals for that particular operation. And we have laid out a possible waveform and we kind of worked out how this pulses can be generated and we said it cannot be generated out of a combinational circuit we need a sequential circuit and in this case we said that it can be generated out of a mode 3 counter by decoding the out the present state and putting an output logic to decode it. The next question and that can be you know kind of implemented by writing the truth table and that is the truth table we have seen and you can kind of get a function output as a function of the present state. Then we the next question we have asked and we have seen that this particular delay comes naturally because of the tcq and the t output logic and then we asked whether this is enough to generate all kinds of timing signals is it a generic architecture. So we put some arbitrary waveform and we said yes it is fine because that output logic can be changed the truth table can be changed to generate any kind of waveform in terms of the clock period does not matter. In this case the answer was yes and we have seen that answer we have seen that decoding and we also said that there is no necessity that the state transition goes through a particular neat sequence it can be any arbitrary sequence as long as we properly decode it. So there is no need to worry about how it counts this is a counterpart but that can be made use in minimizing the area of logic and so on. And essentially what we have is an input output waveform so we come out with state transition and output ultimately from that we generate this next state table and output table. And we have captured the finite state machine as a counter going through various states with an output logic to decode to generate the output logic. And we said that sometime it is convenient to decode the output as a function of present state and input then it is called mille output if it is a decode of present state it is called a moore output. And we also said there is another convenient way of looking at is combining these two blocks together because both get the same input. So that is shown here where the logic generate the next state and output. And the last thing we have looked at is the timing issue which is similar to a counter but additional path is an output. So that is captured in the clock period definitely it comes for I mean that has to be analyzed because this output can go through another combinational circuit and reach a register in that case this has to be modified. So which looks similar to the counter because after all the counter is a finite state machine. So counter is also a specific example of a finite state machine where output is not decoded. So now though for illustrating I said I kind of work from the counter to the state machine okay. Don't think that the state machine is a counter but it is other way you know state machine is more generate we can say a synchronous counter is a finite state machine is a specific case of a finite state machine not the other way just for grasping it you know from kind of evolving it from the counter is convenient that is why I have discussed this way but don't say that the finite state machine is a counter a counter is a finite state machine other way. So please now it is a very important topic once you grasp this basic architecture the timing you can master the design this is very many a times very much lacking in textbooks because textbooks to show some practical cases it takes lot of pages and pages it is very difficult to kind of describe in textbook that is why people don't handle it. So please revise this go through the reference book understand it well we can continue in the next class with the designing. So I wish you all the best and thank you.