 Welcome to the presentation of the STM32H7 DMA Request Multiplexer, or DMA Mux. It covers the main features of this module. The DMA Mux Request Multiplexer allows routing a DMA request line between the STM32H7's peripherals and its DMA controllers. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line unconditionally or synchronously with events from its DMA Mux synchronization inputs. The DMA Mux may also be used as a DMA request generator from programmable events on its input trigger signals. DMA Mux main features. Up to 16-channel programmable DMA request line multiplexer output. Up to 8-channel DMA request generator. Up to 107 DMA request lines and synchronous operating mode. Per DMA request generator channel, DMA request trigger input selector, DMA request counter, and event overrun flag for selected DMA request trigger input. Per DMA request line multiplexer channel output, up to 107 input DMA request lines from peripherals, one DMA request line output, synchronization input selector, DMA request counter, event overrun flag for selected synchronization inputs, and one event output for DMA request chaining. The DMA Mux request multiplexer enables a routing DMA request line between the STM32H7's peripherals and its DMA controllers. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line unconditionally or synchronously with events from its DMA Mux synchronization inputs. The DMA Mux may also be used as a DMA request generator from programmable events on its input trigger signals. The assignment of DMA Mux request multiplexer inputs to the DMA request lines from peripherals and to the DMA Mux request generator outputs, the assignment of DMA Mux request multiplexer outputs to DMA controller channels, and the assignment of DMA Mux synchronizations and trigger inputs to internal and external signals depend on the STM32H7's implementation, referred to the STM32H7 reference manual. The DMA Mux request multiplexer enables routing a DMA request line between a peripheral and a DMA channel in unconditionally operating mode. When the multiplex is set, it ensures the actual routing of DMA request acknowledged control signals. The connection of one peripheral request to the multiplexer channel's output is selected through the programmed request ID in the DMA REQ ID field of the channel control register, or DMA Mux CXCR. For each peripheral request line an ID is assigned. DMA REQ ID equals 0X00 corresponds to no DMA request line selected. After configuring the DMA Mux channel, the DMA controller channel to which it is routed can then be configured. It is not allowed to configure two different DMA Mux channels to select the same DMA request source. Each DMA request line multiplexer can individually be set to synchronous operating mode by setting the Synchronization Enable, or SE, bit in its corresponding Multiplexer Channel Control Register, or DMA Mux CXCR. The DMA request router has multiple synchronization inputs. The synchronization inputs are connected in parallel to all multiplexer channels. When a multiplexer channel is in synchronous operating mode, the effective connection of the selected input DMA request line to the multiplexer channel's output is conditioned with events on the selected synchronization input and on a built-in DMA request counter. Upon the synchronization event, the selected DMA request line is connected to the multiplexer channel's output. From this point on, each served DMA request, transition one to zero on the selected DMA request line, decrements the DMA request counter. In its underrun, the DMA request counter is automatically loaded with the value in the NBREQ field of the control register and the DMA request line is disconnected from the multiplexer channel's output. Thus, the number of DMA requests transferred to the multiplexer channel's output following a synchronization event is the value of the NBREQ field plus one. When the DMA Mux channel is configured in synchronous mode, its behavior is as follows. The request multiplexer input, or DMA request from the peripheral, can become active, but it will not be forwarded on the DMA Mux request multiplexer output until the synchronization signal is received. When the sync event is received, the request multiplexer connects its input and output, and all the peripheral requests will be forwarded. Each DMA request forwarded will decrement the request multiplexer counter or user-programmed value. When the counter reaches zero, the connection between the DMA controller and the peripheral is cut, waiting for a new synchronization event. For each underrun of the counter, the request multiplexer line can generate an optional event to synchronize with a second DMA Mux line. The same event can be used in some low-power scenarios to switch the system back to stop mode without CPU intervention. Synchronization mode can be used to automatically synchronize data transfers with a timer, for example, or to trigger the transfers on a peripheral event. A synchronization event or edge is detected if the state following the edge remains stable for longer than two AHB clock periods. After writing to the DMA Mux CXCR control register, synchronization events are masked during three HCLK cycles. When enabled, the multiplexer channel generates an event or a pulse when its DMA request counter is automatically reloaded with the value of the corresponding NBREQ field. The event generator is enabled by setting the EGE bit in the control register of the corresponding multiplexer channel. When the DMAX channel is in event generation mode, it generates an event or a pulse when its DMA request counter is automatically reloaded. The request counter is decremented with the execution of a DMA request. The DMA Mux channel event output can be used as a synchronization event or trigger for another channel. On its output, the DMA request generator produces DMA requests following trigger events on DMA request trigger inputs. The DMA request generator has multiple channels. DMA request trigger inputs are connected in parallel to all channels. The outputs of DMA generator channels go to inputs of the DMA request line multiplexer. Each DMA request generator channel or generator channel further in this section has an enable bit. The DMA request trigger input for generator channel X is selected through the SIG ID field of the corresponding generator channel's control register. Trigger events on a DMA request trigger input can be rising edge, falling edge, or either edge. The active edge is selected through the POL field of the corresponding generator channel's control register. When the DMA Mux is used in the DMA request generator mode, it allows performance of DMA transfers on events that are different from a peripheral DMA request such as external interrupt event, comparators output, RTC wake up, and other events refer to the STM32H7 reference manual. A programmable DMA request counter enables the configuration of the number of requests to generate on a single trigger. Upon the trigger event, the corresponding generator channel starts generating DMA requests on its output. Each served DMA request, transition 1 to 0, decrements a built-in DMA request counter. At its underrun, the DMA request counter is automatically loaded with the value in the GNBREQ field of the corresponding generator channel's control register and the generator channel stops generating DMA requests. Thus the number of DMA requests generated after the trigger event is the value in the GNBREQ field plus 1. A trigger event or edge is detected if the state following the edge remains stable for longer than two AHB clock periods. After writing to the DMAMuxRGXCR control register, trigger events are masked during three HCLK cycles. If a new DMA request trigger event occurs while the DMA request counter's value is lower than the GNBREQ field value, the trigger event overrun flag OFX is set in the status register DMAMuxRGSR of the corresponding generator channel. The overrun flag OFX is reset by setting the associated clear bit COFX in the DMAXRGCFR register of the corresponding DMA request line multiplexer channel. Setting the DMA request trigger overrun flag generates an interrupt if the DMA request trigger event's overrun interrupt enable bit OIE is set in the control register of the corresponding generator channel. The STM32H7XX integrates two instances of the DMA request router, DMAMux1 for DMA1 and DMA2 in the D2 domain and DMAMux2 for BDMA in the D3 domain. This is an example for DMAMux inputs. For a detailed list of DMAMux inputs, synchronization events and request generator triggers, please refer to the STM32H7XX reference manual. An interrupt can be generated for a synchronization event overrun in each DMA request line multiplexer channel or a trigger event overrun in each DMA request generator channel. In both cases, per channel individual interrupt enable bits are available. Please refer to these trainings linked to this peripheral for more information. STM32H7 DMA controller or DMA and STM32H7 basic DMA controller or BDMA.