 In the notes that you will get, there is actually a very detailed tutorial in which I have taken essentially one or two circuits which produce glitches and then we just go step by step by step saying this is what the computer will do and then it will become clear to you if you just go through that that this is how the simulation proceed so that the concurrency and the time, they become quite clear to you. Now, the way the simulation proceed is that it proceed so unfortunately we do not have time and I will leave you leave for you to do the tutorials on your own time. So, the way the simulation proceed is the following the first step is the syntax checking grammar checking. So, you have described something and just like a C compiler or anything you will you check for the syntax that everything is according to the correct syntax. The second thing is elaboration the circuits are described in a compact way. For example, there might have been a 1 kilobyte memory. Now, you are not going to describe every bit of the memory right each is a hardware, but you will have some repetition grammar saying take this 1 bit memory and expand it 10,000 times or whatever, but when you do the simulation each bit is different and must be separately stimulated right. So, therefore, the circuit has to be elaborated has to be expanded out to its actual value. You might have described a circuit behaviorally for example, you might have said that a counter is a d flip flop with q bar return to d and then you may have 4 of them. Now, each one receives a different signal you have described the behavior of the counter only once that these are the properties of a d flip flop, but because of this interconnection each one of those d flip flops has a different behavior depending on what it is connected. So, while the description has it only once in reality it has to be repeated 4 times and such expanding out is done at the time of elaboration. However, at the time of elaboration a very important data structure is developed. This data structure is called the sensitivity data structure that means any piece of hardware is sensitive to some input that means its output has to be recalculated when that input changes. Now, in general combinational logic the output is sensitive to all its input, but that is not always so. Indeed you are all familiar with transparent latches. A transparent latch is such this is a transparent latch. It looks just like a d flip flop, but its property is that when clock is high q is equal to d if d changes q will change. That means it is transparent. So, any change in d will be reflected in a change in q this is a transparent latch. A flip flop on the other hand is exactly the same except that if the clock is 0 or 1 q remains fixed it does not change when d changes. Only when q clock has a transition then the value of d is read and assigned to q. That is the standard flip flop. The transparent latch simply says that when the clock is high q is a copy of d, when the clock is low the q retains its old value. Now, both of them look very similar. How will you describe them differently in a hardware description language? The behavioral description seems to be that when the clock goes to 1 then q equal to d. What is the difference between the latch and the flip flop then? 1 is no, no, but in this description see the value is assigned only once and it is assigned when the q goes from 0 to 1. Correct. q will not change, d can change. So, the only difference between them their behavior is the same. Their sensitivities are different. The latch is sensitive to clock as well as d. If either changes the output has to be recomputed whereas the flip flop is sensitive only to clock. If d changes q need not be recomputed. Only when the clock has a positive transition a new value of q has to be computed. This is the only difference in this way. So, therefore a circuit need not be sensitive to all its input. So, when we describe a circuit the sensitivities are inferred and these sensitivities are then made into a data structure and then you say that if there is a signal you make a list of all the circuits who are sensitive to you. Now, should the value of this signal change you wake up all the pieces of hardware who are sensitive to this signal. So, essentially it is a reverse mapping. When you describe some hardware you said this hardware is sensitive to this signal. So, then you put hardware u 1 sensitive to this u 2 sensitive to this u 3 sensitive to this. Now, you do a reverse sorting of this. You say this signal and u 1, u 13 and u 15 are sensitive to it. Signal b u 4 and u 10 are sensitive to it. So, you do a reverse sorting and this is done at the time of 11. Once this is done then the third step is simulation and in the simulation you have a loop. There is first step which is called signal update. That means all those transactions that at this time make the signal equal to this. So, at the current time if the time of some waiting is up then you update that signal at this time. So, first you do signal update you do not compute the effect of the signal update. Simply update all the signals which are waiting to be updated. So, all signals are updated first. Then evaluate which signal change and that is called an event. Because of this update it might be possible that a signal was updated but it did not change at all. For example, you might say make q equal to 0 at 30 microsecond. When the time became 30 microsecond you assigned 0 to q but it turns out that the old value of q was also 0. In that case no change has occurred but if the old value of q was different then you will say that q has had an event. So, all updates will not result in event only when a value changes it will result in an event. So, you check whether an event has occurred. First do the updating of all and keep track of which signals have had an event. And the next is called selected or selective simulation and what you do is a nested loop for each event for each component sensitive to this event. Resimulate the circuit. So, more than one event may have occurred. So, you take an event then you go to your data structure. Who cares about this event? So, you will say circuit A and circuit B care about this signal. So, then you wake up A and say look this node just now became 1. What do you think of your output? So, that guy says what is the current time? So, you say current time is 30 microsecond. So, that guy will say please make my output equal to this at 30 microsecond plus delta. You wake up the second circuit and then that guy will say oh this signal change. What is the current time? So, you say current time is 30 microsecond. So, he says make my output equal to this at 31 microsecond. Each resimulation will then result in a set of transactions. No output will be made at that time. These transactions will be entered into a time ordered queue. So, you retain a time ordered queue in which there is a request that at this time please do this at this time please do this at this time please do this. This is ordered according to time. You finish insert. So, these when you do resimulation the output will be recomputed and that output will not be updated immediately. That output will be inserted in this according to the time at different places in this queue. And when you have done that all then you will see what is the top entry in this. And then advance the time variable to that. And now again do this whole thing repeatedly till all events have been taken care of. So, this is how simulation actually proceed. I have very little time and madam Dathe is going to fill me because this is not the part that you are going to use. This is something which has to be always at the back of your head when you use simulation. However, now let us look at a particular kind of description which has only structural description. There is no behavioral description in that. So, in structural description what do we do? I am taking VHDL as an example now because now we are doing practical thing. Each component is described as a two part object. The first part is the external look. So, you look at each object from outside and from inside. So, when you look at it from outside what do you see? You see its pin diagram and you know what circuits to connect to its pin. That is called an entity. So, to take an example let us say entity d flip flop. So, I will say entity d f f is and then I must specify its port. So, I will say port and then I will have a comma separated list of all the inputs all the outputs and that bit type. So, for example, I will say port d and clock followed by a colon and there are two properties which are to be specified. What kind of signal and what is its direction? So, I will say for example, d and clock are inputs and they are of the type bit and this whole construct can be repeated in a list separated by semicolon. So, for example, I might say semicolon and then q, q bar are out and bit. This describes the ports of this. Notice that I could have also said d in bit, clock in bit. I need not group all signals of the same direction. I can describe them individually or as a group. If I describe them as a group of signals then they will must be comma separated and this entire construct is separated by semicolon and the list and its properties are separated by colon. The whole thing is inside bracket and this whole thing ends with a semicolon. So, you have described the spin diagram in short and then you say end entity d l. Now, in the old VHDL there was a whole lot of dancing that you had to do. You had to convert this entity into a component and then you had to instantiate that component in order to use it in a circuit. Modern VHDL allows you to instantiate d flip flop directly or any entities directly. So, maybe I do not I am not sure, but in your lab perhaps you will use that side. So, now the entity is over. You must describe the look from inside. So, when you look at a component from inside you are describing how does it work. So, you say architecture give this architecture some name. So, say my first you could give any name. Now, you have to specify an architecture of which entity you are specifying. So, you say architecture my first of DFF is and now you can specify between begin and end the working of this part. Now, this part you can be either behavioral or it could be structural. So, if it is structural then you will instantiate component. So, you might say to give you an example u 1. So, u 1 is a component name. Now, you have to say what kind of component it is. So, modern this thing can instantiate either components or entities. The old one never allowed you to instantiate entities. So, in this one if you are using entity then you might say entity this is by the way optional DFF and then you say port map. Port map is equivalent to soldering a wire. So, the entity told you what is it spin diagram. So, it has a pin called D a pin called clock and so on. Now, you are connecting these pins to some signal which is equivalent to soldering a wire. So, you are soldering a particular wire to the D pin soldering a particular wire to the clock pin and so on that is called port map. So, you are simply saying port map and may be your circuit may have some interconnection. Let us take some example that this is D clock Q Q bar and let us say we are we have a divide by 2. So, we take connect Q bar to D and then you might have some other signal and then this might be your output and the clock could be generated from let us say an end of enable and external clock. So, now I will have this entity called a circuit big circuit. It is a it is enable external clock and D will be its port signal like before and this call call it x or something will be its output and now you will instantiate this AND gate and you will have to use this as some internal signal called A right. So, you will have to declare in this begin and end. So, for example you will say entity big circuit is port D clock enable in bit. You might directly say Q out bit and entity big circuit. So, you declare the now bigger circuit using that smaller piece. Assume that just like D flip flop you have described the AND gate also alright. So, then what you will say is architecture some name of big circuit is and then begin now first of all you must declare all the local variables. So, A is a local variable that is not known from the port and that is the only circuit in this particular one which is local alright. So, then you will say A notice that internal signals there is no direction do not have to give them as in or out. So, you say A is a signal of type bit. So, after begin you will say signal A bit. The Q bar was part of this it is a port signal. So, yeah internally of course, if you are taking it I am assuming that Q and Q bar are going output. So, then in that case you should give Q bar here. We are not doing any processing on Q bar right oh you are connecting it to D yeah alright and then you assign this signal A and let us say that this is called B. Then you must instantiate the AND gate. So, you say U 1 is of type AND the modern version of VHDL will require you to declare that you are directly instantiating an entity. So, you will say and U 1 entity AND and then port map and now you map the signals of this to this. So, you will say port map enable external clock and A then you will port map this. So, wherever the clock occurred you will put A and you will port map Q bar to B as well as D to B which will short Q bar to Q bar to D alright and then take the output. So, in short every internal wire will carry a signal you must declare the signal and the type it could be a bus it could be an 8 bit bus right. So, in that case you will declare it as an array, but otherwise signal there are some IEEE type signals etcetera do not have time to go through that, but this structural description essentially involve the following you first must have in your library all the entities that you are using. So, either you must have described it or it must come from a separate library. So, you must have all the entities that you have and then you must declare an architecture declare all the signal. So, here for example, A and B will have to be declared of type B. So, signal A and B will have to be declared as. No, no, no it is inside the architecture which will yeah yeah yeah all the declarations come before begin and then you instantiate all the components and then end. This is a purely structural description it simply says what is connected to what and how using what, but you might actually have mixed. For example, you might say this is the interconnect and then this signal you might have some signal here which you would say D is equal to A or X depending on some C. So, you say if C equal to 1 then D equal to X else D equal to A. So, that is behavioral the rest is structural. So, you can mix both kinds and then apply an input to this whole thing and test it out. Now, one last point before my time runs out is that the design description is not everything you have to then test the circuit that it is working like you do. So, that is called a test bench. So, you have a test bench in which the circuit you just designed the whole circuit that you designed is one component and this describes how you will test it. So, you will apply some inputs to it using sources and you will observe some outputs and compare them to some standard output and generally produce a result either an error if it does not agree etcetera. So, for example, if the timing is wrong then you will say over this period the to did not agree. This whole circuit is called a test bench. What is the remarkable thing about a test bench? It is also another circuit after all. So, why should we worry about test bench as a separate kind of thing? It just uses the circuit that you designed as a component and applies all sorts of test circuits to it, test signals to it and looks at its output and behaviorally sees if the outputs are equal to expected values or not. But, there is one remarkable property of this test bench. No, that is the function of it, but there is a particular remarkable property of a test bench. No, it has an entity. No, no, port map you will require, you you are placing all these components. So, port map you will require correct, its port list is empty. That means anything that you want is part of this big circuit. There are no essentially this bench has a circuit that I have designed and all the test devices and nothing is coming out of this bench. Anything that I want for testing it is all already inside. There are no external input or output to this circuit. So, that is the mark of a test bench. It has an empty port list. So, you will have entity test bench is port just closed without anything and entity test bench. So, a test bench is something which is self-sufficient. It has the circuit that you want to test and let us say that we have just designed an ATT file. So, the first description is completely behavioral right specifications have been given to us. So, it is a completely behavioral and I have a test bench which generates various instructions according to the timing of its bus and it gives various instructions and some test program needs to run on this ATT file right. So, it is a complicated test bench and this test bench will then run through, but the anything that I need for testing this ATT file is part of this circuit and including applying inputs and testing output. Therefore, this test bench is self-sufficient and port will be 0. Next when I go from fully behavioral to let us say now first block level decomposition. Now, all I can do is just plug out the old architecture and put in the new architecture and even this new architecture should have exactly the same output. If it does not that means I have fouled up somewhere and I can catch myself right at that point. If that works then I take out the ALU and replace the ALU by gate again plug in the whole thing again it should give me the same result and so on. This way I catch my errors as soon as they occur and do not let them propagate a long way. So, therefore, a test bench is a very useful circuit and almost any circuit that you design must be designed with a test bench to ensure that it is indeed its behavior is indeed what was specified to be the behavior. I think that is all the time that we have for right now. Madam, you will require only structural description from them. No, no. So, all I have done is what is under the bonnet of a simulator the idea of delta times and so on, but also entity architecture and so on and behave in instantiation of components. So, that I have done, but I have not done any processes and if then else and case and so on. So, the rest means the instantiation of components and declaration of signals I have done, but we have not had time to do behavior. Sir, just one question. Why we are not able to simulate transistor labor circuits and synthesize them using VHDL? Not VHDL is not capable of simulating and synthesizing transistor level circuits. So, that is because the model that is not actually correct. The point is what is the library that you are using. So, in case of VHDL the model for a it is considered useless to go down to a transistor level. It is assumed that your library will always have a digital circuit and which will then go down. However, this is wrong to say that you cannot synthesize transistor level. If you have model for a transistor as a switch, then you can synthesize down to a transistor. The only point is that unlike verilog the model for the transistor is not a part of the language, it is part of a library. So, if you have a library which describes the transistor there is no problem. But in verilog also we are able to simulate not synthesize. No, of course you synthesize synthesizer is not part of the language, but in a verilog system of course, meaning maybe you should show it should be sure we must show it to you that synthesis. There is no difference verilog and VHDL are only syntactically different. Synthesis means can it be downloaded to FPGA? Sure using verilog of course. Transistor level design. Of course there is no difference between VHDL these are two different it is like two programming languages, Fortran and C. So, both can be used for both. No, but the transistor level in one case is part of the language that is what I am saying. So, NMOS is a component understood by the language. In the other case there is no inbuilt component. Any component that you use has to come from a library and if you have a library then VHDL will also. So, books are saying that FPGA programming for transistor level is not possible. This has nothing to do with programming language, which FPGA gives you a transistor? Suppose sir I am designing a transistor level, suppose I am designing a NAND gate. So, are we talking of FPGA or are we talking of ASIC? No sir, I am designing a circuit NAND gate circuit for simulation purpose and I use verilog for design. Simulation part is quite easy and it can be done. Now, second part is, am I able to synthesize it and download to the FPGA? Again we are back to FPGA. If you are using FPGA then you can use VHDL, verilog, X system, verilog whatever you want. A transistor is not available to you. In an FPGA you have only LUTs and so on, those components available. The transistor is not visible to you. So, it is not a function of the programming language. It is a function of the architecture of the FPGA that a transistor is not available. So, if a language did allow you to synthesize right down to the transistor level, it will do you no good at all because you cannot address a single transistor in an FPGA. You cannot use a transistor in an FPGA. Because you wanted a single transistor, you cannot get that transistor in an FPGA. But presently we have those mixed type FPGAs or FPAA, field programmable analog arrays which include transistors also. Correct. So, that is not an FPGA, the C of gate design. Sure, but then you can use that using both VHDL and verilog. So, now we should be able to simulate a synthesized transistors. You will if you have a library which does that, then there is no problem. In general, synthesizing down to transistors is no use because nobody has that kind of design time in which will be synthesized down to this thing. In fact, the effort is going towards other modern design for example, even counters. In fact, some designs use microprocessors as a black box. The modern FPGAs for example, come with for example, the Xilin series comes with four FPGAs as components. So, the idea is that you stop designing as soon as you hit a component which is available in your library. You never ever have to go down to a single transistor. But it is not a property of the, it is not a property of the language. It is a, it is a property of the design style. The language verilog is very MOS specific. So, many MOS structures become part of the language itself. VHDL is a generic language and any technology that you wish must be brought in as, as, as a, as a library of component. So, for example, VHDL even refuses to look as a bit collection and will not convert it to an integer. It does not know which bit is most significant. It refuses to assign a most significant bit at least significant sense to a collection of bits. To hit a collection of bits is the collection of bits. Verilog makes many more assumptions. So, for example, it makes the assumption that the left most, left most bit is in fact the most significant bit. It allows you to assign from a, assign from different width buses, one to the other and so on. So, essentially verilog is a very loose language. Therefore, it is a very convenient language. You have to do very little. On the other hand, your chances of making mistakes are very high. VHDL is a very formal language. You have to do a lot of work, but on the other hand, you are sure. That is the difference. But otherwise, at heart, both are simulation languages which follow the thing that I described right in the beginning. When we write a VHDL code after functional simulation, we are going for the timing simulation. So, whatever the delay introduce in the timing simulation, what kind of delay it is? That comes, that is generally inertia and that comes from the library of part. So, essentially what happens is, first you want to see that the circuit that you are proposing works properly. At that time, you do not want to bother about delay. So, that is the zero delay model and then you will have the timing delay. So, there are various delay models. Then, there is the constant gate delay model in which you assume that every gate has the same delay. But it is not zero because there are some things which might be missed out if everybody has zero delay. For example, all glitches will vanish because they will have zero width. So, next you might want to do constant gate delay model in which every delay has a fixed gate, one gate delay or two gate delays. So, all delays are measured in individual multiples of a gate delay. Then, you have the timing model in which what happens is that suppose you are using a Zyling safety gate. It actually computes the delay of that component based on where it is laid out, how long a wire has been used and so on. And there is an idea of back plugging of those values. So, what happens is that you describe the circuit and then the timing delay simulator adds an after clause with the actual delay extracted from the circuit depending on the actual layer. And now, the simulation that you get is exact according to the time. And then there is a pre-layout and post-layout timing simulation. So, in the pre-layout timing simulation, the wiring delays are not taken into account. In the post-layout, not only are the component delays taken into account, but the wiring because now you know the wire length. So, the wiring delays are also taken into account. So, is it possible to minimize that delay that we are getting in the timing simulation? You can. There are various synthesis switches that you have. There are switches which will minimize complexity. There are switches which will minimize delay. So, you have to trade off one against the other. For example, suppose you want to minimize the time, then it might allocate close by gates and certain gates may become unreachable because of that. So, you may waste a lot of hardware resource, but you will get a very fast circuit. On the other end, you may want to minimize complexity. In that case, it will use every resource even though it has to use a tortuous wiring to reach that gate so that all your complexity is minimized. In that case, you will get a very large circuit, but it will be slow. So, these things are there given as switches at the time of synthesis. If you wish, you can have the finished program in more than a week. Yeah. Yeah. So, we have we have both submitted. If you are interested in a comparison, you can do that. But which is actually a small component and that is why I did only the structural part.