 మారఒ trás బ్యాంటడి ధానిలం Hello everyone Okay so during the last the last session lastön ఏరిత్దానారితట్టో lastizations జానిని to how to code, how to two important ones బర Audience Arting Now, in this section బర traveler RG పదానిని సంలి Now, this section మిషిufficient�్తాసనన İn సాయిట్లిమాఎ సదిసందిమ్లూస్యి రకిని బ్య్స్ మంన్ర్లి న్లిమార్తి ఈందాల్ర్లు సందిమ్ర్లేలి పానికె ప్నకి పిబ్కి. న్లారేసది న� we will be looking into this, the design we will be looking at the three commands and I will elaborate on these five and during the whole unit of synthesis I will keep following this flow chart. Now let us look at assuming you have RTL type strategy what you could do with them. So the first important command is it translates HDL into intermediate format. Let us not worry about what that intermediate format is it is something intermediate design combined. This command is recommended for reading RTL. This is very very important when you want to read RTL when you want to read the law this is the command you should use first step. So any command any command you can get help in the design compiler by using this. Analyze my sense will tell you what are options are available. If you do a man analyze I may say analyze it will give much more details about each and every option. So I would recommend like whenever it is the first time you are using any command I would recommend using these two options. So analyze my sense will give you a quick summary of what are options are there and man analyze will tell you in detail what it is it is a lot more details than the number of options. So its options are minus library name, minus word library name. So these two are just to specify what library you would use to store the intermediate output of the after reading the RTL. This is in conjunction with the defined design list of what you call earlier. These are anyway you could so a parenthesis here parenthesis here means that this is an optional argument. So minus library, library name, minus word library name they are both optional arguments. Since this command is common for VLOG and VSD that is why you have to So but once you start coding in VLOG most probably you will not need these two options if you design the kind that you designed correctly. You will only need this one minus format format string this will tell design compiler what format it is. So for reading a VLOG you would say analyze minus format VLOG. Again you can read about these options minus update, minus read update and all that because these are not used frequently these are used for some advanced cases some special cases you could read about them. Then this is a very special case again minus defined macro name. So you go to go back to VLOG you can have parameter you can have macros behind obviously this is only for VLOG and so VLOG has give this macro. So many times code and attain code will have this statement. So you could define those macros. So let us say I want to I want to set the constant I say that let us say I have an option in my design to set a particular register to either 0 or 1 based on two use cases. So I can say I can define a macro as if there is let us say if there is 0 then I will assign register to 0 otherwise I will assign register to 1. So you by defining that if you do not define anything it will go to the else bar. So it will define it it will specify the register it will assign constant point to the printer. Using this minus defined macro you could say minus defined 0 and correspondingly design compiler will pass that and it will assign the register value to be 0. This is very similar to the V-poster character of C. So once so analyze what analyze actually does is it enables you to define macro while reading a very long or VSDL column. Obviously for VSDL the macro is not the macro is not the topic there. So if analyze is complete and it can also tell what our syntax error to your RTL file sentence. So once you pass analyze it means that at least your code is syntactically corrected. Then what follows is second command is elaborate. It is a second step of SGA translation elaborate will actually build the gtec data. So after you have read in the file using analyze elaborate will map it will start the mapping or rather translation of your code into gtec. It will start mapping it into gtec. What it does is that SGA parameter is funded in your parameter command in the law the all parameters will be expanded. It will infer register the matches we saw in last picture how does design compiler infer register the matches it will actually infer that and it will link the design what linking design if you have a PLN or memory and that memory is part of your should be a part of the link library it will now map it will now link the design elaboration view the design should be completely linked each and every component should be mapped if it is not able to link the design it will never work. So it is of course architecture selection architecture selection is VSDL specific whatever it is a part of it is the law specific it is so analyze elaborate both these commands combined together are recommended for reading hardware into design again you could do elaborate minus n again it has not so many options it is VSDL specific it is law specific again there are you could read about the options here most important thing is design name we will see a bit more about date block later in the film the design name will be top limit of the design now in the last lecture we saw in the design of an accumulator the accumulator contains an adder a marks in the register block so the top level module which is the accumulator module will be given here now because as a top level module so you only give so you analyze all the accurate files but elaborate only from the top you should be very very clear about this concept that elaboration defines if elaboration should be done on the level at which you want to perform the elaboration the design name here will be the module link of the top level once you start working yourself in time compiler or once you see few examples we have example videos later on you can it will be very clear now there is one more command called v file now v file is used on RTL v file performs analysis and elaboration in the in one step this is exclusive this command is exclusive this should not be used along with either you use analyte elaboration or you use v file or a particular design you only use one either analyte elaboration or read form but read file does not perform any parameter passing or architecting it has limited some selecting compared to analyte elaboration it is recommended for reading map why do you want to read map net list now let us say you are doing a big design it is in a net list form it is a very common occurrence that if you are procuring from outside from some other team from some other company they might give you in a net list form they do not want to due to see the code the code is proprietary so if they will give you the net list they will give you the data you read file you specify if it is very long or ddc or dbm so on again you put to read about all these options in design compiler in detail however you can use this to read the RTL also if your RTL is simple enough it does not have it supports matroname reading if your RTL does not have parameterized design you can go and read about parameterized design if your design does not have parameterized design then you can actually use this read file or reading RTL also or let us say all your code is you are just compiling one module you are just synthesizing and testing only one module so you could reuse read file that your needs to do a separate analysis now let us look at one of the most popular g-tech sequential cell it is called sqgen or section so whenever sqgen compiler read the design it use this sqgen module to represent an inferred flip flop or a latch so whenever it encounters an all this block and sees and reduces that is there a latch or a flip flop it will map that logic onto a g-tech sequential element please note that this is a g-tech element it is not a technology it is not a standard standard cell it is a generic cell as you can see that this generic cell contains clock, data in clear and enable are asynchronous pins enable in asynchronous set this is asynchronous reset next state reset these are synchronous pins synchronous, cobalt synchronous pins so as you can see by the pin names itself you can actually represent either a flip flop or a latch or a cobalt flip flop number of sequential element just by some tweaking of the some you could set some constants and you can represent any sequential flop using a section let us take a flip flop example this is the code of a d flip flop with asynchronous reset how do i know it is an asynchronous reset because reset is a sequential pin as we discussed in the last lecture now design compiler as soon as it reads this code as soon as it elaborates please note elaborate is the command that will force a g-tech mapping so as soon as it elaborates it will map now q is now analyzes and sees that q is the output of the flop so now it will connect q it will instantiate a section, it will connect the q here it will connect the clock, clear is asynchronous reset data goes to next state, so next state is apparently data ok and rest all synchronous is synchronous clear and set asynchronous set they are all set to 0 synchronous enable is set to 1 to enable the function of this so usually in most of the cases you do not need to be concerned about the functionality of schedule because it will be what you are concerned about first thing is i will go into this and second please note in this state synthesis has not been done, you are still reading the design so once the design is read once it inputs flip-flops and mappings the design compiler will simply map flip-flops and mappings to accept them there are a lot many number of g-tech files also so there are g-tech or g-tech and g-tech and so it will map all that so the first step in this list we go back and try to remember is translation, translation and mapping so translation means reading of the RTL mapping means mapping the RTL into g-tech so this is one example where it will map the sequential logic into segment so let us look at very very important thing very very important the sort of reports which is called inference reports let us first look at the inference reports for registers now hgm compiler provides inference reports that will describe each input flip-flop or not so each of the all these sequential blocks will get mapped so design compiler after at the time of elaboration you say elaborate the top level design it will start throwing out reports the enabling or disabling of generation of inference reports can be chemistry on and off by using the sdn in reporting the sdn in prefix here represents that this sdn in or sdn in variables are used by the sdn compiler part of the sdn compiler so sdn compiler is actually the engine that reads in the level off so sdn in reporting level variables controls the enabling or disabling of these elaboration the tools by default if these are enabled these reports are very very useful during the analysis of the design so what do you do you read in the article and wherever you expected a latch or a flip-flop you look at this report so it will say for example for this as soon as it reads this module this module it knows two is a sequential element so it will add a suffix here it will add underscore reg to the name it should add the register so it will say register name is pure it will tell that the type is it deducted a latch if it inferred a latch the level here would be latch it tells what is the width it is one in this case it tells whether it is bus so width is one it is sort of bus mv tells it is multibit let me read for now these are very important these tell you that whether it has inferred an asynchronous reset asynchronous set, synchronous reset or synchronous set now this inference report is not consistent with the code here so now this code here tells it is an asynchronous reset so there should be a yes yeah so asynchronous reset has a yes multibit is no AR is yes that means synopsis design compiler has correctly identified that you intend to have a asynchronous reset here so for every register during the start of your coding process when you start synthesis first synthesis you should carefully look at all the the complete inference report for each and every register what about the combination logic let us say for example the combination logic is not correct and we saw few mistakes in the previous sector where few small mistakes could mean inference of a latch so if you see a latch here and you did not mean it then you can see then you can you can search for latch in this report you can press for the latch in this report elaboration report and correct all such cases usually the most common mistake is not specifying every case in the case I have it results in a latch you could grab for latch in this report elaboration report and correct all now let us see how there is an effective coding get rid of the unwanted register the sequential elements are not easily optimized off it is not like combination logic sequential elements represent timing sequence and design compiler in most of the cases when it sees a sequential element from the all this block in the ultimate code it will mark them to flip blocks and those flip blocks it does not know if they should be optimized off on our side they represent the timing sequence and they represent the way you post the RTL you have to make sure that your RTL should contain sequential element only when it is desired it is the beauty of the designer to make sure that if you have unwanted sequential elements obviously your area will be moved let us look at this case in this column you have always a positive slot you have a reset so now this is a question is this a synchronous reset or asynchronous reset answer is the synchronous reset it is not part of the sensitivity it is a synchronous reset count goes to 0 if it resets state if it does not get reset count implements there are 3 outputs here and bits or bits door bits and or and zore all get these values and gets and of all bits or gets zore of now when it reads zore in this particular always door if that starts here and ends here it sees it sees down and it sees off now you see correspondingly you see the impedance report like this orbits so it will append underscore edge orbits range count range orbits and width range inductive they have width block it is a positive block it specifies the width here one of them that is count range is a bus it did not although you expected that reset would be a synchronous reset it did not it does not have a y for the synchronous reset it does not have a y here so it is not deducing that it is not inferring that it is not inferring the synchronous reset I will tell you how to parent it how to make sure that you tell design compiler that it is a synchronous reset because it will affect the implementation and the way the net list is implemented let us leave it let us hold the partner we will see the it is not necessary how to encounter that but the important thing is that do you actually want and bits or bits and orbits So, you should carefully look at this code and decide in most in, but just looking taking a first look and just delving it a bit deeper into this, we can say that and bits, orbits and orbits are combinational operations on on the count and most probably it is not needed that they be represented by a system, how do we connect this code like this. Again we go back to the basics, first thing we have to separate combinational people. So, here is how we do that, we separated this equation part and the combinational part is another orders of. Now, when it when it see this all this job, design some pilot will assume obviously it will know that these are combinational outputs, it will impact only counter as we expect, not and bits or bits and drop. So, this is the way we have to be very very clear while coding what is sequential, what is combinational and code according to that. First very important and basically separate the all this blocks for combinational people, very very important. This will make sure that you are not having number of liftoffs are not more than what they should be. In the particular case of unloaded registers, so HGN compiler will not automatically keep unloaded registers or unloaded with blocks or larger in a design. These as we start itself HGN compiler knows these are not necessary and they are removed even before the designers complete the optimization. So, they are removed in the first class of optimization, what are unloaded registers, what are entrances of HGN example. So, a module few, who you have three inputs of critical speech, i n 1, i n 2, i n 3, your input clock or put out your two registers somewhere in front to your buyer save. Always at college clock, sequential element there is no reset here, someone gets i n 1 to sign in 2, come to get i n 1 to sign in 2 to sign in 3, but now the output here, the out there is only one output, out gets the someone's compliment, save gets someone or something, but is save an output, is save feeding to any output, no. There is only one output out and out get someone, what about some two, some two is it no way affecting any output, although you have a buyer, but this buyer does not go anywhere, you assign save to something, but the save is not going to the module module also. So, now HGN compiler knows, DC knows that save is not new and some two that is usually the great save is also not used, although some two is register flip flop, it is a valid flip flop, but the output of this flip flop goes to a buyer and that buyer is hanging, that buyer is not connecting to anything. So, the combination logic of save is not save and the register this flip flop some two is not save, both of these are optimized off. So, what you get is registers corresponding to someone, that is it. Again you have to very careful while coding, that if you are not using some two, do not even put it there, it will be completed. Otherwise if you intended to use some two, then you should make sure that these registers go to some output or drive some two, otherwise they will be optimized off. However, however in the initial design phase, let us say I coded this, I intended to use some two, but for a later period. So, and you want to still want to see what is the area impact. You want to analyze what is the area impact, but you do not know where some two will go for now. You can tell DC to keep the unnoticed registers. So, here is one more example, here is one more variable called hdl in preserve sequential, that tells DC which says to preserve. So, to preserve unloaded untrimmed flip flop and latches may be technically we said hdl in preserve sequential to all, to preserve only flip flop. So, if you said this to all, DC will preserve everything all registers, all and latches. If you said this to ff it will preserve only flip flop, it will preserve only latch, to preserve all unloaded sequential cells, including unloaded sequential cells that are used only as loop variables. Please ignore this for now, we do not need to go deal with this now, the loop variables loop variables are part of for a, for loop variables. And so, a loop variable in a in a software concept a loop variable is nothing, but the loop variable comes, but in case of since it is in case of hardware, a loop variable simply means that this hardware will be either repeated depending on the depending on the kind of logic you write or there will be some counter. So, not necessary it is not necessary that the loop variable will itself be a flop. If the if the for example, if the hardware is repeated, let us say you have a loop of file and it means that corresponding hardware should be repeated five times, there will not really flip flop that will represent the counter file. So, if you said this variable to all plus loop, it will start saving the loop variables also. Please you should be very careful in using this variable, because by default this variable is not set it has to instead of the default value means that it will not keep unloaded a distance, if you choose to enable it to all or SS to latch you should be prepared to see a real thing. So, this will be very careful while using this variable. Now, so we saw register inference, we saw few inference support, inference support of this type is the name five and so on, but there are some limitations on register inference that means I have already said very low, complete that low is not synthesized with only a subset is, we should be careful while writing RTF percentage and these are the limitations that tell us that in what all cases a system file will have problems in inferring a flip flop or a latch. So, whenever the model asynchronous behavior using a flop, the tool does not support more than one independent flop and asynchronous behavior is more if the all is block is clearly signal multiple independent is block support. We will see few examples of this later, it cannot infer flip flop and latch is being taken out, it assumes a flip flop in a latch it assumes will always have two states either 0 or 1, not ready. If you have a special library cell that has this case, you should instantiate it, it will never never in for even if you have a flip flop it is dead output in your standard cell library it will never use it, you should if you assign the value to be dead in your always loss it will error, it will error out, it is it cannot infer flip flop by direction thing, the flip flop then should be the input or output not enough. Again whatever special case, whatever cases are written here, if it is not supported and you have a cell that implements that, you should instantiate it swiftly, it cannot infer flip flop multiple flop input, again you should have flip flop with only one flop, that means you are always at the rate for which it should have only one flop, it cannot infer multiple clutches again it does not infer register bands, register files and a thing but small memory, so it will not infer let us say you have a small memory as you unknowingly you specified a register file as part of a target target has to be designed compiler will never infer that, inferring means it will never automatically pick up some hardware to replace your RTA, inferring means that, how do you encounter this? You do not code an RTA part manually to instantiate that part for example, you have a register file you want to use it, you instantiate a register file, you do not rely on design compiler to infer that thing so although we can instantiate flip flop by direction thing, design compiler will ignore that, it will be done as blackout, that means it does not know the functionality, so if you use an if statement to infer deep flip flop this is very important, the if statement must have corrected top level of the always flop like this if you have some statement here and you want DC to infer this is a if you think you have reset flip flop it will not do it, because the first statement is the only statement so very important coding guidelines whenever you want to write the code for an asynchronous set of reset flip flop, first slide should be always a reset always set, hence part you write your rest of the code but first slide should always tell DC what is the reset for something, you should very very clear about it so this tells you that you cannot arbitrarily code RTA you have a sort of a set of guidelines which you should follow to make sure that design compiler does the correct thing also correct we talk about finite state machines again there are set of rules about finite state machines the set of rules it must never be assigned a value other than defined state values finite state machine cannot have latches it must always have flip flops the FFM register all these register rules must never be module code function for the pass code the state register that is we have specifically talking about this register it cannot be a port of any module or function or task it can only use the operands like equal to or not equal to that is the comparisons and not any other expressions since the states will always be compared only compared, there will be any data operation or not there can be only one FFM design we have also have multiple FFM we need to have separate modules all codes are initial design so again bioreaction support is not supported in combination feedback rules are not supported although combination logic does not depend on state method in accurately presented FFM will only should have only module and optional sentimentals are FFM this is again a variable which tells a DC whether or not to automatically let us look at one example you have 4 states set 0 hold 0, set 1 hold 1 so states are represented by good way of coding so this is one hot coding that means that only one bit will be one time and so 4 states are represented like this lsv 1 hold 0 will have bit 1 1 set 1 will have bit 2 1 hold 1 will have the lsv 1 so 4 states for one hot encoding you need 4 bits so you by using parameter you define all these states current state is my current state is nothing but the state register so the first all this block is the sequential block this is the sequential block which tells DC that this part here is the state register very simple way this is a signal this is an a signal a cc current state gets next state if it is not cc and then in a separate combinational block which forms the combinational part of the FFM you write the operation that will take place based on the state based on the current state so current state you write so current state if it is something if it set 0 based on this you follow this diagram and you start coding if you have an input dependency you have you write it here like this if and hence and so on and make sure that all the cases are covered all the states are covered now in this case if you if you set the variable this variable FFM model is running to true this this statistic does not is not matching with the code but you could ask it will define it will tell you what the states are it will give you the parametric code here it will tell you how many number of states are there so you can match this inference code with your code and make sure that you write them by an understand what you wanted it to understand and we also see that this efficient follows each and every two messages this try to mark it one to one you can use this code as a help to code whatever FFM you want so first you should have a skate diagram and then you can code like this now let us look at a very important concept of sdl compiler sdl compiler so sdl what is a sdl it is these are special commands that will affect the action of sdl compiler and design compiler these commands are ignored by any other tool so they look like commands but there are special commands they begin with slash slash synopsis or slash slash synopsis there is one more notation but we will use this slash slash synopsis notation in all our examples so they carry special value for design compiler it will change if a dc reads those statements it will help you in some cases these are dangerous in other cases it will sdl compiler will report a syntax error it will use that as an option on a regular command we will see now let us look at the few most famous syntax directive when to use them when to avoid them so a thing such as now we saw that there is a rule that if we want to code sdl whatever the first statement should be it is very important now in most of the cases the tool will so as I mentioned before sdl set or reset cannot be will only be implemented only if you have a corresponding standard sdl the case is where sdl only then you could map it so in most of the cases if you have a sdl reset and you have correct coding done then you do not need to use sdl but in some cases if you see that even if you write the correct code I am not sure what that case might be but if you see that this is another old variable you will have not seen people using it a lot so you should try first sdl sdl sdl if it does not work you can write the comment like this sdl sdl sdl sdl sdl sdl sdl sdl sdl use in the statement and you say you see that this is the AC signal use this only on single grid signal or AC compiler will see it and then it will check whether on the on we check have you assigned any constant to register if you have done it it will try to look in standard cell that is if you indeed have an AC server set of a set clock and then it will man thus we have a signals we have a signal sync set. Now this is important this is used to infer at each flip clock with a signal set reset when we compile a design the section inferred by agile compiler when we map to a flip clock in the logic library with signal set in the pin or or if you will have it does not contain a flip clock with a signal set reset then design the compiler will use a regular DT clock and build the synchronous set reset logic in front of a decision. The choice depends on what method will provide a better option and we can do that. It is important to use the directive to label because it tells the thing that signal should be kept as close to register as possible during the now first first assume that you have a flop in your standard cell library that has a regular to register and you want to use it then you simply tend to see that ok by using sync set reset that yes I have I want to use this flop and this is my particular reset pin resetting unit this is the best case scenario. If you do not have a flop corresponding flop in your design now this you cannot map it so it will build a combinational logic. Now this directive tells we see that my reset pin is very important it should be kept as close to register as possible otherwise what may happen that this reset pin will be a lower priority signal it will go then might be a number of stages between this reset signal and your flop and correspondingly you might face problems in container simulation. This is not an easy example to tell right now at the level we are starting to learn to do it but as you go on you find that this is a problem in your design where you have complex synchronous system. So, if your reset synchronous set is being generated by some complex logic then and you want to keep that reset close to the flip flop then you use it. Let us see one example yeah again inference support is the way to go here you you read in the design you elaborate and you look at the inference support. If it tells that asynchronous set is yes your job is done. So, first my recommendation do not use this for a proper guideline that is first line should be hit set or reset. If you see that your corresponding option is set to y your job is done if you still see n here you can use this use the statement synopsis same set reset here the signal is set is set use set to 1 and and verify with respect to the inference with with the inference support is correct you can go there is one more inference box many times we have lot of case statements and we want a tool to implement this using a much not the combination logic not not have a thing whatever kind of combination logic this might increase the area or or decrease or decrease the performance but many times you would want that for there are many reasons why would you want that let us say your functionality is not final and you know that you might need to pay something in the next later then amongst type of structure amongst the type of structure is needed to understand as opposed to an ideal structure amongst kind of structure amongst the type of structure has many times it has better timing but more area so if you want a design compiler you want to make sure that it uses multiplication logic in your in your it picks up the next logic in your argument to multiplexer in your logic that is you need to use the first set is you can use the synopsis internal mask here then you can see your gtech weather so corresponding to sequential block you have much of block here it looks like this you are selecting this your beta you are output so if you you must use simple variables that control expression for example if we use not input a but the negative of input a it will not infer a much soft so whenever it infers a much soft we use it for much when it infers a much soft you can be assured that it will use the much kind of structure form and it is a library to implement a much speed in most of the cases unless and it will be timing more area than that so as a first as you start coding I will not recommend you to use this always from the last 3 from we saw 3 directive we saw 18 set we said I will not recommend that you use this if you do proper coding in a library has a corresponding set you are you are good you can use the set we said for complex synchronous types of input so these are any special cases again again the first thing you code you code without using the directive look at the inference reports see that whatever you expected is there if not then you can actually study about these directives and start using them so I am just that is why I am mentioning only the famous ones again with informa I will not recommend it to you guys unless and until that is very much necessary now comes the full case so the two things here full case and parallel place are the most popular and most misuse comparable you should be very very careful first thing you should not use it but why are we cutting this we are studying this because in case you get an RTA code and somebody has used it we should know what it means we should know what kind of dangers it is and we should know how to solve those problems so full case prevents SGA type browser from generating logic to test any value that is not covered by the case branches and create implicit defaults now let us see you have a set of case block and all the cases are not mentioned and there is no default what does that mean it means that you see that assume that in the cases that you have not specified you want to preserve the value of the output and correspondingly equal in for a latch you obviously do not know this so what is the reality this first way out is to correct your poop use the default statement make sure that all your case have this all your case is complete complete you mention all the cases but many times it is not possible many times the designer will assume that or will know that the input case we want to code will never come so it is not coded so then to prevent a latch you can use this you can say it is an obstacle case in front of the case statement case case statement and DC will now not infer a latch we will see few examples parallel case will tell DC if you do not use a parallel case and you have such a condition that more than one case can be true then it will make a priority kind of input it will make a priority logic DC will make priority logic to make sure that this prevents as in compiler from building additional logic to ensure that first preference of a few branch so there are more than one branches that are evaluated to prove and it will make sure that the first preference of the two branch is executed with more than one branch or two at a time this will be an extra logic this will be extra priority logic you want to prevent that that is why you can see that okay boss all these cases are exclusive that means at one point only one of them is true so please do not add any extra logic any extra practice of these will not do that now let's see the inferences DC will tell you as corresponding to each case branch each case in your design each case statement in your design DC will produce an inference report similar to the system similar to steps logs for example C67 line number it is M by line number and 5 number it tells me here that line C67 of some kind has a case statement and it is automatically filled in automatically that means that we haven't specified any that the final direction we haven't specified full case value but by designing a cell this case block has all the cases covered and only one case is true at one time this is by design so it tells auto and auto it is automatically this is the best case scenario what if you forgot to hold a case now here it is telling me that at 9108 the case block is not filled that means all the cases are not covered but it is done for the other case it will tell that okay boss it is full if it is not filled full and not even parallel it will say no and no the first two cases here tell us that some binary direction is not used now I have started using the parallel direction so this tells me that at 959 the case block it is full yes it is full but you have used a parallel case direction user means that you are telling DC as a user that please this as family case if you write full case it will say user slash user now this table tells us that what happens when the case analysis description is full and parallel no additional logic is related so you should achieve for this or a case blocks if you do not want priority logic if you do not want latch you should achieve for the first thing by design your code should be full and parallel too if it is full but not parallel then priority input logic will be there it is generate logic will show that branch is with first if it is parallel but not full that is a created if it is neither parallel not full then it is generate priority input logic and it will also create parallel please understand this table very very carefully spend some time over it try to see try to go in cases and see where you might miss and it does not become a full or does not become a parallel so on next is an example here so this is the case statement select is of 2 bit maximum it can have 4 so all 4 cases are coded so this is by default full and obviously by default parallel why because only one of them this can be true at one time cell can be 0 0 0 0 1 0 1 at one time all the cases are specified and one can happen at one time so it is parallel and full full you do not need any compiler like this second case select is 2 bit you can have 4 cases here but only 2 are coded so it is unknown what happens when cell equals 0 1 and 1 0 in this case there is some binary generate logic to test for any value that is not covered and create a default branch keyword is implicit it will assume it will assume a default branch and try to it will try to make sure that why here remain unchanged that is why it will use latches what you can do to correct this state use a default branch use a default branch or you know that in one of some cases the designer knows that cell cannot take value of 0 1 and 1 0 ever select an input here what if designer knows that cell will never take 0 1 1 0 and he is a bit lazy he does not write default here but writes a full case here you can do that now by telling in office DC that it is full case here it will assume it is full and it will not infer latches this is the case here here you see that an office full case is used here for the first case case is ion in it is stupid again only 3 are written second and third 4 cases report is not there in the first case statement condition ion is equal to 3 is not covered however designer knows that it is a full case here so no latches both final case and full case are used here which is again kind of a 1 1 input in designer knows that so current state is a reported signal it has 16 states only 4 states are coded here so only 4 states are coded here and this is 1 1 reported so designer knows here that only 1 bit will be more at a time and all other cases are embedded they will not even come this is a statement like that so instead of writing on the 15 cases here he writes what are the valid cases and tells the see that it is full and final code that means DC will not have any priority including it will not have any latches so this is you will see in my experience I have seen not a party like this because in this case the designer has he knows very well that these cases are embedded they will never occur and so his simulation test cases also do not have these cases so he is never facing the problem of simulation synthesis but again he wanted to know that designer should know what we do if you are not confident if there is even 1% chance that these cases can occur then please make sure that by design your case block should be for a thousand and there should not be any need to use the full case of talent so a word of caution a final word of caution although the full case directive although both full case and report clauses prevent flash inference they have the same meaning the full case directive asserts that all input values have been specified in both report clauses this is for the case where you do not have default and you are using full case you are telling the see that assume assume that all are covered but the default clause explicitly specify the output for any undefined input form now what is the difference in terms of the hardware generated in terms of hardware generated in the first case let us say let us say we take a case here now here let us say I write default out is equal to B now in this case let us say there is some hardware generated compare it with the case where default is not specified now if default is not specified it is not possible to give DC will assume the value of output such a value of output we will assume some value just 0 or 1 or 2 or 3 whatever such that the area is minimal so it is like a part of my optimization but let us see we specify default here until and fix the value of output it might increase the area bit why because now this value is not don't give it is some other value so the optimization default here is better when compared to a non-toad case as you all know so this is the difference now what can we do we do not want to use the full case yet we want the hardware to be optimal in such cases use the default clause with an output value of it so we specify in this case we say default out is equal to X this tells that this tells DC that okay was this is full by design it will take auto image and now we have to use the don't give it frame optimization if we use full case directive the gate level simulation might not match the rpm why because let us say there is a case which occurs which is which you did not specify case block and the second case actually occurs then it will not match the hardware simulation whenever the case expression evaluates from an specified input value so this is the problem if you use the default case simulation mismatch can only occur if you specify don't give a condition and the case expression so in the any first case when you use full case and the simulation mismatch occurs it is difficult to develop and since you set the output value with X it is easier to develop so it is always preferable to use the default class and not use anything I will summarize this lecture this is the last slide so we saw we saw how to read the RTL what commands we use so for reading RTL I would recommend you can use read files or read the netlist so you will use analyze library then we saw we saw the example of inference report for register this is very very important to study to take some time and study the elaboration report that comes out after you read the article we saw how to separate population and people always want to make sure that number of registers is minimal we saw the coding style for represent there is one very good example you can follow this for your second coding then we saw very important concept of compiler synthesis direction we saw few famous synthesis directive again the recommendation is first code without synthesis direction only use synthesis direction when your coding style is not able to solve the problem because usage of synthesis direction when synthesis direction is not time is a tool it might cause simulation to be useful and simulation is not desirable condition it is difficult to develop you have to again review RTL code thank you