 So, for the recording I will make the PPT only share good afternoon friends welcome to the third session of on-date. This course in the session now we will be covering the reset and register the portion of the topic. So, the following are the sub topics that we would be covering in this presentation. What I would like to do in the initial first few sessions is that now you understand the basic memory interface and then the basic architectural features. So, that when we get into the assembly instruction level details you have all the background knowledge what is needed especially from the ARM architecture perspective as well as running general about the processor architecture. So, you are well acute and prepared to understand the assembly instruction and understand deeper details about how it is implemented and how they are used in different scenarios. So, in the session we are going to cover what not a normal class that ARM uses on what is a processor core and what is a CPU core and then we will talk about some of the P interface signals that comes out of the ARM processor core. Then how the memory is interface with the processor core and different bus cycles that ARM supports then the register set and different operational mode that ARM supports that. And let us touch upon the reset behavior there also because that is where the processor starts executing your instructions and once we understand this then we are ready to get into deeper about instructions ok let us carry on with our show. So, let us see what is ARM 7 PVM. So, this is the processor core that we would be you know covering in detail especially for the assembly instruction. So, we should be able to understand you know if the name is given like this of ARM core what each of these letters mean. So, I have given only for this particular processor core what these names imply 7 is one series of instruction set architecture that ARM has come up with. So, ARM has started with one and what we are studying now is the 7th series in the instruction set architecture of ARM and T means that it supports some mode as I have mentioned briefly in the earlier discussion that some mode is a 16 bit instruction with mode which is for a compressed core execution where there is an embedded system where we have very very high limitation on the memory that to connect of a core that we can use. We can go in for some mode where 16 bit instructions are put in the ARM and that is read by the processor and it is expanded decompressed and then executed in the processor. So, we will not touch upon this now there will be one session dedicated for some mode. So, just thought I will let you know what it means. D is a debugger unit is present in the processor. So, that person you know as a developer we can run our code on the target platform and then we should be able to debug our code by single stepping it executing one instruction after the other and see the contents of the register. So, that we can understand how our program is running on the processor and if there is any bug in our code we will be able to fix it. So, processor supports debugging by providing a separate hardware unit unit and then multiplier unit and embedded eyes is for a built in developer hardware. So, these are all for these two are for the debugging perspective and this is for high performance multiplier unit present in the system. So, we will go into these details later this is just an introduction about the naming parameter in a normal data followed by ARM. Now, what is the processor core and what is the CPU core? See when we see ARM based SOC, it is already the ARM processor core is inside that chip SOC is the system on chip. So, we have a processor core it could be ARM 7 or ARM 9 or ARM 10 and that processor core is bought from ARM. So, this is the contribution from ARM of the unit ARM company and then it could be integrated with the instruction cache or data cache and the MMU that also is provided by ARM, but that comes as a separate unit. So, ARM for interface. So, the whole thing when you have a burst interface and the cache and memory management unit there is all of them going into a simple chip which will be a CPU. When you say a ARM board development board with a ARM CPU in it, we will call that ARM CPU as one of these will come 710 or ARM 720 or ARM 920. So, this kind of a CPU contains the processor core inside. We when we talk about instruction set and different register set and different modes, we are talking about what is inside this processor core and when we talk about different signals coming out, these are all the signals coming out of this processor core which is integrated with the rest of the unit and built as a single chip. So, I hope this makes you understand the difference between a processor core which could be ARM 7, PDMI or ARM 9, TIDMI or one of them and then the CPU core along with the different cache memory and other functions what were in the SOE SOC, they are combined together called as the CPU core. So, the other units that are used along with the processor core may not be from ARM, it could be from third party or it could be the module coming from the vendor who bought the ARM IP and integrating it with its own co-processor and then building a chip which will be used for a particular end application. It could be for network team or it could be for data processing or it could be for graphics. So, this is how ARM vendors buy the ARM IT core from the ARM and build a system. Now, if you see the name like this, you should remember that it is the processor core. Now, these are the signals coming from this 7 PDMI processor core. You might wonder where are the three numbers because we are all used to seeing a processor core with the signals input, output so going out and going some inputs coming into the processor. We are used to seeing some three numbers along with that, but here what you see is only the signal description which are the input signal and what are the output signal and what are the different kinds of signal that go into the processor and group based on the function. Now, why are they not giving any pin numbers here? Again the reason being this is not coming as a single chip. This is an IP again in the interactive property core which is going to be some other SOC. So, these signals will be going into some other modules within the chip and then those signals come out of the IC. So, those pin numbers it could be NC. So, it is the independent of what is coming out of this core. So, that is dependent on the vendor who bought this ARM core and built an SOSC. So, when ARM is giving the description of the signal, it does not talk about the pin numbers. Hope you understand this why there are no pin numbers in this discussion. Now, let us see what all this you know high level I will show you some signals, but we will not go into the detail of signals here, but as soon as you know as in when we cover some part of the modules, we will discuss about each signals also ok as you know forward. Now, one thing what we should remember is that when the processor is powered on, it has to start from some normal stage that is a processor needs to get a reset signal. So, there is a pin input signal going into the processor core which is a reset bar. If it is represented as n reset or you know in the single description it will be shown as a reset bar. So, once you know here what happens is when the signal is low, it is active. So, what happens when the reset signal is activated, the processor starts executing the core from the address 0x all 0s. So, this is the external demand of the enough address. So, I have given this many 0s because it is a 32 bit processor and the address range is 0 32 bit from 0 0 to all 0s. Now, what is the clock going into the processor? So, any processor needs the clock. So, in the ARM processor we call it as n clock which is actually for memory cycle clock. This is could be coming from the external structure 3, it could be a crystal or a crystal may be connected out of the scheme or it could be generated and multiplied. So, whatever modifications or changes going to have to know to this clock what is coming to this is n clock which is based on which the processor is n. Now, you know that this is a 32 bit processor. So, address with the 32, they connect to the memory. Now, ARM processor has a unique feature where it has got two types of database database. I will talk about this later why it is required and how it is implemented. There are so many control signals. Of course, you know that for any memory cycle there must be some read write signals to be going on and then other request kind of what is the bus data which is being written into memory. So, those control signals are going out from this. Now, in the early session I mentioned that ARM is a by-endend processor. What does it mean? We can make the ARM processor run either as a by-endend in the by-endend mode or as a by-endend. So, based on the signal given to this input it can it will behave as a by-endend and by-endend. So, you may wonder whether this signal needs to be no other constant. Of course, if the software running on the chip is always assuming that the by-endendness is followed this should not change between. Other way you will see the performance totally you know it won't work at all so totally. But if there is a requirement that this needs to be switched from little end end to big end end with all some application requirement that is left to the programmer and the system designer to take care of it. But from the processor code perspective it sends us this signal if it is 0 it behaves like little end end machine other way it behaves like a big end end machine. Now, any processor has to have some interrupts. So, all of you must be aware what the interrupts are for this to indicate what is a is a any action that needs processor's attention those interrupts will be generated by these signals and they are connected to two input signal which is called IRQ and SFIQ I will talk about that later past interrupt and the interrupt response screen. Then there are other descriptions there are a whole lot of signals which we will not talk about it now as in means there is a need we will talk about it ok let us go to end the session clock signal I mentioned that m clock is a every clock which is going into that this is all state change within the processor are controlled by this clock this is the main clock for all memory accession and processor operation now this m clock has a provision that we can slow it down to make the whole processor run slow if suppose slower percolars are memory or needs to be integrated with the processor. So, you may wonder why this kind of flexibility is given in ARM because when the ARM IC is made it could be integrated with any kind of system it could be with a a fast clock processors with a fast clock or it could be integrated with memory and other systems which are very slow because power requirements are less and which is the for a low end application then the processor should be you know configurable to run in any speed. So, m clock has a provision with the additional signal called n weight you can always set the clock signal to make it run slow. So, the internal clock is always taken from m clock signal and with n weight so, you know any clock will be having a high end function kind of a thing I will show you the description of this clock and when n weight is added it could be slow the clock is frozen as a kept as low. So, only when n weight is high that is 1 the m clock is taken in as a clock and the processor is running in the speed. So, if you want to stop the processor or stall the processor make this n weight low when the m clock is low and then you keep it as long as possible whenever you want it again for the processor to run you can make this n weight high and then when the m clock becomes high the processor starts running. So, this is another output thing coming out of the ARM processor code to just see what is the internal clock of the processor. So, this is actually e clock is the output of this 2 signal which was set into the processor. Now, this as I mentioned n weight signal is used to set the memory cycle if lower memory are in use. So, this is all about clock system memory. Now, I mentioned that ARM 7 TDMA is a one one one architecture what is one one we have a simply memory for both code and data. Now, so there is a only one address bus connected to the memory and there are some control signals apart from language and sequential access there is a ME address this signal gives you what is the kind of transfer I will explain this in detail in this slide. So, now you see here now when this bus enable is given at 0 then ARM processor is connected to the memory to this data bus which is the bi-directional bus. So, what happens both while reading actually writing the data flow through this bus. If suppose if bus enable is 1 these are the keys which are activated and there is a separate data in and data bus. So, having a separate data in and data bus does not mean that it is a hardware architecture. We need to have a separate memory and separate address data bus then we can call it as a hardware architecture which is simply again same one one architecture, but only thing is the data could be multiplexed or it could be separate for input and output. And you know this range of addresses are pretty good grid. So, this was the maximum range of the addresses for memory. So, both core and data reside here. So, when a processor is running it has to use the same address bus and the data bus to read the instructions as well as read any data that needs to be read in or written into through the same bus. So, you know that these two cannot happen together. Now why do we need this in a typical environment where we want the ARM core to be connected to a external memory the bi-direction bus is used normally, but if it has to be connected within some internal such a grid some you know in the SOS people can make use of these two buses for accessing the memory. So, only at a time only one of them can be used and it is the system designerís choice whether to drive this in a 0 or 1 and then use the appropriate data process for interacting with a memory. So, this kind of flexibility is given again because the ARM core is given as a IP and it can be integrated with any other processor to build an SOS. Now how is the memory access happening in the ARM? Address does provide 4GB of any type of space you know the 32 bit and actually 4GB. And the processor can transfer either world or half-word or byte quantity. So, as I mentioned this memory which is used is a byte addressable memory. So, ARM can transfer any of this data from the memory or it can write any of this 32 bit or 16 bit or 1 by 22 bit. So, who decides that the MIS input is a 2 bit input coming into you know sorry to the memory it is driven by the processor. So, this encodes the size of the processor. So, if a processor is transferring a half-word it will put in the proper combination of bits to indicate to the memory that I am transferring an half-word or a byte or a 32 bit folder. So, so based on this signal MIS signal coming out of the processor 4 the memory understands that the transfer size is 1 of these 3 and then accordingly it reads the data from the data. However, the memory system you know the bottom which based on the transfer size. Let me tell you if suppose it is processor is driving this 1 0 as a combination. That means it is doing a word transfer on the data first. That means for a given address there are 4 bytes of value which is either coming out or to be read from the memory by the processor. Now as you know the addresses of byte weight by you know this 4 32 bits indicate that there are 4 bytes which are read or written and they simply memory cycle. Because of this the bottom 2 bits are redundant because assume that 1000 is the address you have read 4 bytes now what will be the next address that you need to put it on the memory memory it has to be 1004. That means you are jumping the address is jumping from 1000 to 1004 to 1008 that means the intermediate numbers that is 0 1 0 0 0 1 and from 0 1 1 are not coming out of the address class because address is incremental every 4 bytes. So, because of this the bottom 2 bits will be ignored if it is a 32 bit access. If it is a half word access you understand that but if it is a byte address every all 32 bits are valid addresses and that needs to be understood and accordingly the memory has to add on. So, in summary support all kinds of transfers both input as well as output it can write into the memory in any of these word sizes or it can read from the memory also in any of these word sizes. But when it is doing it has to inform the memory that what kind of transfer size it is performing so, this is not this can change for from one cycle to the other side. Every memory cycle can decide whether it is it wants to do a any of this one of this transfer then based on this these bits are given and the memory needs to support this. Now let me give an example ok let us take an example of this particular combination that is a 1 of 0 this may know the address bit 1 of 0 is 0 1 ok byte is write on 0 1 that means here this is a address bit 1 and 0. So, once you are reading the byte that means all the bits in the address are valid. So, if the byte is showing this 0 1 that means it is the odd byte which is read by the password. Now you have to remember that based on the middle engine or big engine this you could be mapped to either one byte from MSB or it could be a byte next to the LS byte. So, what I am saying is based on the engine you have to have the processor you know this signal what is given what is being read or written into is taken from the respective data process. So, if it is a little engine you know that LS byte will come from this what are the memory whereas, if it is a MSB big engine machine it will be the value will be coming from say if it is a lower byte it will come from the MS byte because it is stored as a higher address right. So, because of that what happens is wherever the byte is read is coming on whichever data bus it is copied into the lower byte of the register and then as a sign extended or it is filled with 0 based on the kind of transfer which is being done. So, basically this helps in terms of transferring a word or a byte or a half word from the memory whatever may be the big engine and then transfer that value to a particular place in the register. Now, let us see what is the what happens when a memory write is performed. So, this shows the LS byte is coming to the LSB here data bus. So, this is a between mode then what happens is this data if it is a word write it comes on all the 32 bits of data, but if it is doing a byte write that is the processor is trying to write one byte this byte particular byte of the what is there in the register is the data bus. So, it copies the same byte into all the four the eight bytes of the data bus and writes it. You may wonder why that single data is copied onto four this just a provision you know comes now for the memory to use any one of this based on its convenience ok, but actually only one byte is getting transferred, but it is instead of sending if you are leaving these other data bits data bus then of the things mk this you are driven by the same data. So, that the memory would perform the you can read any one of this bytes to copy into its location. So, this is a half hour transfer then it is driven onto both the 16 bits of the data bus. So, this is a way memory is getting written into different words the word with written into memory from the processor. So, can use the most convenient copy of the data ok. Now, let us start with the bus it call this processor bus interface as a pipeline now what is that pipeline we it gives maximum time for memory to decode the address and respond to the address what it means is the address will be given ahead of the memory and the memory has a sufficient time to decode the address and put the data back into the data. So, this kind of pipeline mode is particularly used for DRAM because DRAM has a row and column addresses and it has to resolve a particular cell in the DRAM memory and then get out the value. So, it it takes some time for decoding the address and then putting the data out on the data. So, in the pipeline mode the advantage is that the address is given ahead of the memory cycle a one cycle before. So, so that the decoding could can proceed from the memory side and it can be ready with the data and when the processor can read it from the data. So, this is what is address expressed in this and then in this mode address does not remain valid till the end of the memory cycle. So, there needs to be a so you know agreement between the memory and the processor the signal details and then accordingly the address and data bit will be read by the processor. So, there is address pipeline enable signal which indicates to the memory that it is in the pipeline mode. In the deep pipeline mode could be used for DRAM and DRAM kind of memories where this kind of a delay is not needed from the that even address and the data read into the new. So, I will tell you a small you know I will show you a small bus cycle here. This is the M clock which I show you that it is given from the external security into the processor mode. So, this you know this is a complete on cycle here. So, what you see here is it is a pipeline mode these are this is high signal AP is address pipeline enable and M rack and SQ sequential is a combination which gives you whether processor is in a sequential mode or in a what kind of a bit of address it is being read. Now address is read on this particular falling edge of the M clock signal. So, this process requires memory access during the your cycle. So, what happens is during the cycle the earlier stage you know at this stage address is available address is available in this cycle and the data is available in this cycle. So, you see that during this time address is put on the address and in this time at the end of this clock the data is read from there ok. So, now let us talk about different bus cycles. I mentioned about sequential and non sequential to see what they mean. A non sequential cycle transfers to or from an address which is unrelated to the address used in the preceding cycle. What I mean by this is that of course, you look at the address first and the data first. There is one address coming out of the processor goes to the memory and the data is given out by the memory. Now next address is coming out of the processor is not related to the previous address. That means, they are not sequential ok. The random addresses coming out of the processor there is no relationship between one and the previous cycle and memory decodes every address and then puts the data into the bus. So, this is called a non sequential cycle where there is no relationship between subsequent addresses coming out of the memory cycle. Now in the sequential case what happens is when you have you need to read sequential by bytes or words from the sequential locations the processor can put the addresses incremented one by one based on the words width whether it is being a 32 bit transfer or 16 bit transfer and it will also indicate to the processor that it is a sequential address. Now what is the advantage when the memory knows the address that are coming out from the processor are all going to be sequential then the memory could be ready with the data because it knows that if it is the processor is reading at a thousand and the width is 32 bit then it knows that the next address is going to be from thousand and four and the other one is going to be thousand and eight. So, memory can prefix the data internally without waiting for this to come from the processor so that it can complete the cycle much faster. So, the sequential addresses are relatively faster than a non sequential address. Now what is internal cycle? Now as I mentioned in the CPU diagram which where as we have we saw the processor code sitting and then there are so many code processors and other cache and memory management units in a single chip. Now the same and the address that is coming out of the processor code is not only connected to the memory it is also connected to the co-processor or it could be connected to the some other units on the bus. So, when the processor is intending to do some transaction that is in itself to with the other co-processor it does not want any interaction or anything driven by the memory on the bus indicate to the memory that I am doing something other than talking to the memory. So, that is one way of informing the processor that and no it is not communicating with a memory now if the cycle is going to be used for something else. So, this is one scenario and another scenario could be that the processor is busy doing some operation inside you know it could be doing a MAC operation or some other IPC where it cannot use the address data bus for fetching either instruction fetching an instruction or it is not using the bus for accessing the memory it could say that it is in an internal cycle. So, these two are the different modes the co-processor mode is for informing that it is performing a co-processor transfer and internal cycle is for saying that it is busy with the internal operation and it cannot be doing free fetching at this time. So, these are the four modes. So, if I ask you which are the modes where memory should not try any signal onto the bus it is very clear in both the both these modes because internal access co-processor is a mode it is nothing to the memory the processor is talking to either co-processor or it is busy with the internal operation. If memory if the processor is doing a transaction on the bus it is using this cycle that means it is communicating with the memory either it could be non sequential accesses or it is a sequential access. So, based on this memory can respond according to the address which is coming out of the processor. So, this core cycle different types of cycles are understood by this. Now, how is it communicated? This is the way the signal the combination of these mentioned this is coming out of the system ok. Based on this you can see that whether it is driven by the processor or it is coming as an input or output to the processor. This is a output from the processor to indicate that it is doing one of these cycles. If it is doing n or s it wants the memory to be active. So, as I said mrat or is a 0 is active. So, this means that memory needs to be active to take care of the decode the address and write the data process. But if it is one memory the step up and the processor is free to communicate either with the core processor or it is free to do whatever is internal of the screen. So, non sequential is a simplest form because no no interact no no relationship between multiple addresses sending out of the processor and sequential this is a burst mode as as I told you first address is given and then it says that I am starting a sequential cycle that means it is going to access the memory starting from this address to subsequent address. So, till this sequential mode is changing to non sequential or some other cycle either it is the process you know internal cycle or a co-processor cycle it will continue to read from the sequential addresses starting from the addresses. But one thing you have to remember that every cycle the increment and address is also put on the address bus ok. But memory can comfortably go on to do the data access because it knows that the processor is interested in sequential address access ok. So, whether address is implemented either 2 or 4. So, you may wonder why there is no incrementing by 1. The reason being ARM does not support a byte sequential burst mode it does not make sense you understand right. 1000 suppose processor wants to access only a byte from the address 1000 then the next address will be 1001, 2, 3, 4. So, when the processor could read all the byte in one cycle you know by saying that I am reading a 4 byte value from memory if it is trying to do a byte burst transfer at byte level is a waste of time as well as waste of power. So, normally then you may wonder why is this you know half world is supported in the burst mode because we may have a system where the memory that you are having in that system has only 16 bit data ok. If the memory is a very cheap memory with a low cost application. So, we cannot say that ARM or PCP cannot work with the memory which has got only 16 bit data. So, ARM has provided that provision that half world transfer to half world transfer it can talk to a memory with a 16 bit data burst and it has to perform any operation or the operation is the memory only in the half world mode. And it could perform even burst transfers with the memory if the memory controller supports ok. And memory distribution can even often respond faster as I told you in the sequential access memory can respond faster ok. Now, let us see what is internal cycle. Now, I have already explained to you this is something to do with operation performed by the processor internally and it is does not want anything to be activity to be happening on the address or data. So, no prefixes are required and so processors does not do any operation, but at the end of internal cycle it can broadcast the address to start the next memory cycle. So, in preparation for the next memory cycle it can broadcast the address and memory will decode that, but it will not drive the address data burst until a memory cycle has started. It may be the next memory cycle could be a non sequential access or a sequential cycle, but anyway when the new cycle starts address will also be coming, but the memory has got the address ahead of the cycle. So, it can do the decoding and then ready with the data ahead of time. So, that is the provision provided by this particular support. So, co-processor register as I told you that there could be a co-processor connected to the processor and the transaction may be between the co-processor and the processor. So, memory needs to be discontinued or it should not drive any signal on the burst ok. Now, let us see what the reset signal is all of it. This is n reset that means if it is low 8 is the reset signal is coming over processor needs to take action. So, normally the reset signals are driven by an architecture. Now, a low level process the instruction be exhibited to terminate up normally. So, you know that when the processor is running a suddenly somebody comes and resist the board whatever is happening on the instruction execution is happening on the processor needs to be eliminated and then the processor needs to start from a known state. So, that is the intent of reset or when the development board while the system that you have with the ARM board running and you switch on the system then it powers on the ARM has to come up with a in a known state. So, the reset could be either the processor is running inverting somebody has given a reset signal or it is powering on for the first time. Whatever may be the situation the ARM core needs to start from a known state. So, the reset is very important and that is the first thing what we all know should know what is the behavior of a processor when a reset is given to it. So, as I told you n rate should be high to probably n clock signal to be used right away otherwise if you hold the n rate as low then the clock is held low and you have no stretching the signal ok. The clock is slow down because of that. Now, that supervisor more I will not talk about the supervisor more now you know in the in the in the seconds you know I will be talking about that this actually there is a mode in which the processor starts to begin with and I will talk about band registers before we say what is the specialty of supervisor mode ok. Now, let us go into a register step and the different operational modes of the processor. Now, this is a register that normally as a user we would be using. So, these are all a little bit wide registers they are called R0 to R2P but these three registers which are shown in Shaz and you know there are special purposes we will see what they mean and CPSR is a current processor status register which has some conditional course and means about some internal operation ok. So, there are 16 data registers and one status register R0 to R13 are orthogonal gender purpose register what it means is that these orthogonal means any instruction that you can do with R0 can be done with any other register. So, suppose if there is an add instruction and you say that R0 comma R1 to R2 you could write it as R5 to R6 to R7. So, these registers can be used you know in that instruction where one of them could be used. That means these registers can be you can comfortably use them based on which is occupied by some other value and which one is free for you to use the registers in your instruction. Now, what is the status registers I will interpret some special purposes I talked about a lot of things about status so, in the previous discussion. So, R13 is traditionally used as a stack pointer and especially if it is used with a if a processor is now OS is running on the processor then the OS operating system will assume that R13 is dedicated for the stack pointer. If of course, you are writing your own code you are free to do anything you want because it is part of a set of orthogonal register. Especially if you need to turn a connect to another library or some OS code that has not to use this R13 for some other kind of it should be reserved for stack and R14 is a linked register I can give you this brief example of what it means. Suppose there is a subroutine call you know we will talk about those things when the instructions we talk about. So, if a control is moved to some other place through a subroutine call the return address there after subroutine is executed where the processor control has to come back is actually available in the PC because PC is implemented from the current instruction. So, that return address is actually saved in the linked register. So, that on return of from the call the return address could be copied back from R14 to PC. So, that the processor comes back to the instruction just after the subroutine call anyway we will talk about this later that is the thought I will give you some overview of what it is R15 as I mentioned this is the program counter where the next instruction to be fetched is always pointing at. So, R15 is pointing at the instruction to be fetched from the memory. Now, CTSR is the current program status register that is just what they contain now program counter as I told you this is a 32 bit byte this because all ARM instruction we call ARM state because it is not in some more it is called ARM state ok. So, in ARM state it will be accessing 32 bit instruction. So, the PC will be pointing the set of 4 bytes whereas, if it is in some more it is 16. Now, when I say that it is pointing at set of 4 bytes it is always accessing the instructions as a 32 bit bit . So, as I mentioned in the previous discussion about memory interfaces if it is accessing an instruction from the memory the instruction is read in always as a 4 byte data. So, 4 byte is no instruction. So, if it is reading as a 4 byte then you can assume that the least 2 bits the bit 0 and 1 are always and it is mandatory that all instructions are 4 byte aligned that means, no instruction can start on odd boundaries that means suppose take an example of 1000, 1000, 1000, 2000, 2003 these are all different byte addresses instruction can start only from 1000 or 1004 or 1008 you cannot put an instruction starting from 1001 or 200 because always the processor reads from the memory all the instructions which are 4 byte aligned. So, it expects the instruction to be 4 byte. So, that means the PC will always be released to this 0. So, non constant which start only 31 to 2 bits of a R15 R15. So, it is a R15 instruction suppose because it is little different from on processor it is different from other processors and the PC is part of the general processor register set. So, you can use PC also as one of the operands for the instruction but it has to be used with the portion whenever we talk about instruction I will touch upon those things which you need to take care from the perspective of using the R15 as a general processor system ok. Now, conditional flat we have talked about this earlier when some binary operation is done how these flags are set we understood. Now, this is the place it occupies in the CPSR register. So, the MSP4 bits are mapped onto this flag. Now, these are all left unused and we will see what all these other bits mean. So, normally any processor know there will be some bits reserved for feature use. So, that the processor can be extended with the next family of ISA and new instructions can be added new conditions can be added. So, these bits are left unused they are divided into 4 states 4 classes. The conditional flag of course, mapped onto these flags. So, negative 0 what I mean by both those flags as you know both those flags is for binary operation. Now, let us see what is this interrupt marks bits are. I told you that interrupts are always generated it could be some internally also, but any external interrupts coming are connected to 2 bits of the control spins of the processor. So, they are IRQ bit which is coming into the processor. So, if this IRQ this particular I flag in the CPSR is set that means, even if there is an interrupt coming from the external system it only re-generates by the processor. So, if suppose if you want to disable the interrupt you want the processor to be not to be interrupted because you are doing some critical job and hopefully it is not you know like for patterning then you can disable this interrupt mark no flag by setting these bits to 1 then no interrupt should be re-generated by the processor. Same thing for FIT, FIT is a fast interrupt you may wonder what is the difference between these two actually the priority of this is like you know higher than the priority of this that means you can connect any interrupt from any source which needs to be attended to without any delay that interrupt has to be connected to this particular input and any other serial port or any USB or any other devices where it can afford to wait for servicing this interrupt it can be connected to IRQ. So, internally when both the interrupt come into the processor the FIT interrupts are given higher priority this should be serviced first before coming into this interrupt ok. Now what are the processor moves this is a very important concept you should understand. So, these 5 bits the lower 5 bits of the CPSR correspond to the processor moves it could be privileged or non privileged other thing must be aware of would attempt some force on operating system. So, there are privileged and non privileged states in the processor their user mode or terminal mode. So, the privileged mode is basically it is for operating system or some supervisor mode non privileged is for a normal usage normal users program to run on the processor. Now you can understand that compared to this privileged mode has a high accessibility right. So, in the privileged mode they have access to the access for read and write of the whole CPSR. You can change anything you know if the processor is in this mode they can go and modify any of these bits in the CPSR. Whereas in the non privileged mode the user who is in non privileged mode has only read access to that control. So, what is the current mode what is the current status of these you know whether the interrupts are masked or not whether it is in thumb mode mode or not what are the flags take by the processor. But in the non privileged non privileged mode you cannot modify any of the bits in the CPSR ok. Let us see now what are the difference modes supported by the arm. Now in the privileged mode which is in the top all our modes are privileged ok. That means in these modes the CPSR can be modified. Now this also has additional feature. When you say that in the privileged mode the CPSR can be modified in here in this mode another register which is called a CPSR which is for scale program status also made visibility to the program. That means I will take given an example. Suppose a processor is running in a user mode ok. Actually before getting into the user mode some supracery code was running and then it has enabled the FIQ bit in the CPSR. That means if any interrupt comes the FIQ interrupt will be processed and it will go to the service routine in the ISR ok. Now let us not worry about how the service routine is run now we will talk about the interrupt later. But suppose if the processor is moving from the user mode to pass interrupt mode because of an interrupt coming it will have a visible another register it is called the SPSR where automatically the CPSR is copied into the SPSR register. Because when it is changing the user mode to pass interrupt mode the original mode value was actually referring to the user mode. Now when it is in the pass interrupt mode it is going to be changed to pass interrupt mode. So you have to have the old content of the CPSR because even the in the user mode process where you know our program would have been running and then we may be performing some additional plans would have been changed. But when it is entering the FIQ it may perform some arithmetic operation and those conditions of the CPSR would have been overwritten. Now after the interrupt routine when you come back you will not get the same state of what you had prior to the interrupt. So to achieve that what harm has done is it has made this will be another register when they are entering into this mode and automatically the hardware takes over this I am telling you right now to just have an idea of why FPSR is needed but we will talk about it later on in detail. Now apart from user mode you see that there is a system mode also which also has the same set of register as user there is no special set of register this is all I will show you what are the special set of registers which become now visible in these different modes but in the system mode the only difference is that it can change the CPSR content so what is the use of that I will explain to that so in the subsequent session so the process of mode can be changed by a program that that is the CPSR or by hardware when the core response is coming so when the mode so you may wonder when is the mode changing how your mode of the processor can be changed each 5 minutes it could be by any interrupt coming so from the interrupt it will know that this is the interrupt coming from the signal so automatically it will be set or it could be done by the user program ok. Now what is that there are so many registers now I showed you initially that only these registers are there in the processor we talked in length about these processors now we are seeing a lot of registers please understand that the registers which are shown with this here are the special registers which are visible so if you ask me physically how many registers are there in the processor forget about the which mode they are in only there will be traditional register means you have to add up all the shaded portion and the user mode registers it will all be 37 now again you let us go back to the old example of from the user mode you come to FIT mode on interrupt what happens is suddenly during this FIT mode the this register is visible and you get a new set of registers for this four you know this eight register we have the seven registers now what happens to this actually in the FIT mode if you say RA it will be accessing this not this way ok so in the FIT service routine if you write no FIT FIT comma 100 the 100 is written into this register and original content of this will not be this so based on the mode in which you are you will be accessing those special registers with this name now what happens to this register they remain the same so it is same as this register so physically only one set of this registers are there but they are shown multiple times because in each mode how they each more you see the register is what is shown here so what is the function of having so many registers in FIT mode because you do not have to when you are jumping into the service routine you do not have to save this content because you are getting a new set of registers here you can use them and then come back without interrupting the normal flow so that is the implication of this register where you say that these are different banks registers are available in the model so what is it in system mode the bank register are same as user register and their bank register have to user mode register when the process mode is changed the bank register from the new mode replaces an existing register ok so for an example on the enterprise request if suppose R setting and R putting are accessed in the new type in IRQ they will be accessing R setting and R putting of IRQ and not using user mode register as I explained you earlier so user mode register R setting and R putting are not affected by this operation ok whereas R0 to R1 in IRQ are same as a user mode register so what is the register bank register bank is a whole register file whatever I showed you on different register with different modes those registers are called as a register file so the ARM 70MA process code has the additional features to enhance the performance what are they the register file has 2 read ports and 1 write ports what do I mean by this that means in the same cycle 2 registers can be read time is duration ok and 1 register could be written into ok so typically if there is a 1 register and then there is only 1 port available 1 read and write port you can either write in one clock or write a read from the register in one clock but if the whole register file is given multiple 2 read ports and write ports you can do 2 operations at the same time you may wonder why is it required if you remember 2 operands that are required for any addition or subtraction there are 2 operands needed right so those 2 operands could come from 2 different registers which are in the register file so you may say that R0, R1, R2 that means you are taking 2 parameters R1 and R2 from the register file and because register file has 2 read ports both the operands R1 and R2 operands can be read from the register file in single cycle so that is why ARM is provided and if you remember that R15 is also part of the register file and it is a special purpose so it is a program counter now you know very well that when the program has to execute it has to implement the program counter and keep on accessing the instruction, subsequent sequential addresses from the memory now where it has to be written into it has to be written into R15 which is part of the register file so to enable incrementing or changing the value of PC irrespective of without you know any interruption happening to the operands being read from the register file ARM has provided 2 additional ports only for R15 meaning for accessing the R15 you can use these ports so these ports allow reading and writing of R15 independent of any read or write happening on the other registers in the register file so they can happen in parallel so effectively there are 3 read ports and 2 write ports but one is very unique and special that it can be used only for accessing the program counter why we need to access the program counter simply because every cycle every instruction being executed the program counter is modified because it has to increment to the next instruction so that means the program counter has to be written into with a new order so we need a separate port for that so that instruction can keep on modifying the R15 in short affecting the data accesses from the other registers in the file so this is what happens in the last bullet shows that even update the R15 does not include any issue so now let us see what are the special mode privilege mode registers are for and let us take an example this special register like stack pointer and link registers are for 2 bank registers okay this is used for holding the stack pointer and return address so why do we need special registers for every privilege mode again coming back to the example of fast intrest when fast intrest happens any intrest happens it is going to another routine and then it executes the whole set of instructions so when it is using some of the intrest registers it has to save those registers into stack so we need a special stack for the intrest routines right so it can form a point to a different memory location in the memory and the saving and restoring of registers can happen with those stacks so each of privilege modes can be initialized with different register no stack addresses so that they can all point to different stack addresses so that any saving of registers could be done based on the mode it is easy we will talk about this in some more detail in the description like this it is better if you understand that it is needed it is provided for the sake of saving so we will talk about the registers which are used by those privilege mode functions okay the exception handles but FIT is given additional registers because it does not have to save those registers because it is getting those set of registers so it can perform the operation much faster than the other privilege mode exceptions so as I told you when the CPSR contents are modified the new registers become visible based on the privilege mode is written into the CPSR and the R14 is a link register which preserves the PC value before the exception or the interrupt has happened and then it can be restored from this value it can come back to the instruction after the exception which is to be executed okay so let us see what the reset that after the end reset was made see how the reset is given to the processor it has to be made though okay and then dot high now I am coming back to reset because earlier I could explain you about what are the different modes available so now having understood different modes are there and they have a special register reserved for each of the modes now you can understand and relate why on reset mode the processor need to enter the supervision so when reset is given okay either because of power on or it is given possibly by some external secretary the processor enters the supervisor mode what does it mean the LSB 5 bits of the CPSR is made as 1001 which corresponds to supervisor mode if you recall I told that supervisor mode has the same set of user registers okay but it has got SPSR as well as it has got its own SPSR as well as it has got a right access to the CPSR okay so what happens is on reset whatever may be the value which is saved in R coding and the currently what is there in the CPSR is copied into these two registers because it is getting too additional or put in SCC and SPSR SPB in the S supervisor mode so it saves the current address to current or okay value actually this must be a PC to R coding okay and then disabled IRU it saves the PC value and the CPSR current PC value and the SPSR value to SPSR and it disable this interrupt so on power on on reset it makes sure that no interrupts are enabled and then it clears CPSR that means it is going to start in ARM mode not in thumb mode and then the PC is loaded with a new value so actually this is to be corrected as PC so PC is moving to this so current PC wherever it is is moving to this maybe it could be used by later on for debugging purposes we know when was the interrupt given but if it is in a power on they are having unpredictable values and then the PC is loaded with a new set of value which is the 000016 so actually program ARM processor start executing from this back on reset okay so this is the reset behavior it is sent to supervisor mode and then comes back to normal ARM user mode and start executing from 006 but it saves the PC value and CPSR into this special registers which are LAN registers in this supervisor so this is the purpose of supervisor mode and this is also used for operating system routine then suppose OS is also running on your system and your user applications will be running in user mode and OS code will be running in supervisor mode so after all reset all the register value except PC and CPSR in this so this is the end of the class in this session we learnt about what is a processor code and CPSR what are the interface signals we talked about multiple databases available and what are the different signals available to interface with the memory and different panther sizes possible and then we talked about bus cycles which is sequential access or non sequential access or internal cycle or it is a so we talked about this and then we talked about we understood about register set where band registers are there and based on the lower 5 bits of the CPSR different modes are separated and based on the modes different band registers become visible and there is a special saved processor process state register which is used for saving the CPSR content in this so and then we talked about reset on reset when the processor enters the supervisor mode and then saves the PC value and CPSR current CPSR value into a CPSR special register and then it starts executing from the address 0 to 0 so with this we stop this session and hoping to see you in the next session to learn more about our manufacturer and we will be covering the instructions and before that we will talk about pipeline support in the processor in the inspection have a nice day, thanks for this view, take care, bye