 Hello, Myself Ravindra Chauhan, Assistant Professor, Department of Electronics Engineering, Vulturend instead of Technology, Solapur. So in this session, we will discuss the interrupts in real-time operating systems. The learning outcome of this session, at the end of this session, student will able to describe RTOS interrupts and different ISR processing times, means interrupt subroutine processing times. The outline of the sessions like this, first we will see what this interrupt mechanism is. In the different ISR processing times like the interrupt latency, interrupt response, interrupt recovery and the non-maskable interrupt in RTOS. Now what do you mean by interrupt? Interrupt is a process where an external device can get the attention of the microprocessor. The processor starts from the IO device and the process is asynchronous. Now what is the use of this interrupt mechanism? Now see, in any processor based system, along with the processor, the number of other peripherals or other IO devices are included in the system. Now whenever the device is required some sort of service from the microprocessor, for that there is need to define the particular mechanism. Normally, two mechanisms can be used for this. One is called the polling mechanism and second one is called the interrupt mechanism. What happens in polling mechanism? The microprocessor looks towards the device periodically to check whether any device required some sort of service from the microprocessor. That means the microprocessor is spending the time to poll the devices to find out whether the device is required service or not. So here in this mechanism, the microprocessor time will be wasted in just polling the device. So instead of polling mechanism, one can go for the interrupt mechanism. So in interrupt mechanism, whenever the any external device required some sort of service from the microprocessor, the interrupt the device will interrupt the microprocessor by sending the particular signal. And when microprocessor finds this interrupt signal, the microprocessor will provide the required service to that particular device. That's why this interrupt process, it starts from the any input and output device. An interrupt is considered to be an emergency signal that may be serviced. The microprocessor may respond to it as soon as possible for all these emergency signals. Now what happens when microprocessor is interrupted? When the microprocessor receives an interrupt signal, it suspends the currently executing program. But before that, the microprocessor completes the execution of the current instruction and then the current program will be suspended and the program control will jump to an interrupt service routine program to respond to the incoming interrupt. So ISR is the subroutine program written by the user and stored at the specific address. So whenever the any interrupt is occurred program control will transfer to predefined address which is called the vector address of that particular interrupt. So each interrupt will most probably have its own ISR. So whenever the particular interrupt is occurred all the times respective ISR will gets executed by the microprocessor. Now while responding to the interrupts what the microprocessor does? Responding to an interrupt may be immediate or delayed depending on whether the interrupt is non-maskable or maskable and whether interrupts are being masked or not. So depending on the type of the interrupt, the interrupt will be respond immediately or it may respond delayedly. There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored. Vectored interrupt means the address of the subroutine that is the address of the ISR is already known to the microprocessor means whenever any vectored interrupt is occurred the program control will transfer to predefined specific address of the ISR and that address is called the vector address of the interrupt. Non-vector interrupt means the device will have to supply the address of the subroutine to the microprocessor means the vector address is not fixed. Now we will define some ISR processing times. So first one is called the interrupt latency. This is the interrupt latency time which can be defined by the equation like maximum amount of time interrupts are disabled means disabled type of the interrupt plus time to start executing the first instruction in the ISR. Interrupt response time is defined by the equation interrupt latency time plus time to save the CPUs context. CPUs context means the different CPU registers whatever the data required after returning from the ISR as well as the return address all these will be saved. The interrupt response time is interrupt latency time plus time to save the different CPU registers. Now interrupt recovery time is the time required for the processor to return from the ISR to the interrupted program. Now interrupt recovery in a foreground or background system simply involves restoring the processor's context and returning to the interrupted task. Interrupt recovery is given by the equation time to restore the CPUs context means CPUs register plus time to execute the return from interrupt instruction. Now these three timings that is the interrupt latency response and recovery can be explained by figure one. So suppose here at time t1 the interrupt is occurred means device has sent the interrupt request signal to the microprocessor. Now at time t2 up to time t2 the interrupt is disabled and at time t2 the microprocessor will start responding to that particular interrupt and for that it will take the time from t2 to t3 that's why the interrupt latency time in this case is t3 minus t1. Now from t3 the microprocessor will start to save the CPU register and the next is the processor will transfer the program control to the ISR code. So the time taken by the processor from t1 up to the executing the first instruction from the ISR that is called the interrupt response time. Then after completion of the user code before going to the interrupted code microprocessor restore the CPU context and then it will go to the interrupted task. So whatever the time required to restore the CPU register plus to execute the return instruction is called interrupt recovery time. Then non-maskable interrupt you recall maskable interrupt and non-maskable interrupt. Maskable interrupts can be delayed or rejected enable or disable by executing the defined instruction. Non-maskable interrupts cannot be delayed or rejected and that's why cannot disable. Now since the non-maskable interrupt cannot be disabled interrupt latency response and recovery times are minimal. The non-maskable interrupt is generally reserved for drastic measures such as saving important information during a power down. So can be used to service most time critical ISRs when non-maskable interrupt is servicing kernel services cannot be used to signal a task. However parameters can be passed to and from the non-maskable interrupt but these parameters must be of global variable type. Non-maskable interrupt can be disabled by adding the external circuitry as shown in figure 2. Now here the interrupt is positive going signal we have shown and this interrupt just it can be disabled by adding just one AND gate and the two inputs to the AND gate are the interrupt source and the second input is connected to the one of the output port pin. So just by writing the zero to the respective output port pin the non-maskable interrupt can be disabled. Now from a non-maskable interrupt ISR the kernel cannot be used to signal the task but you could use the scheme shown in figure 3. Now in this scheme the NMI service routine would generate a hardware interrupt through an output port. Since the non-maskable interrupt service routine typically has the highest priority and interrupt nesting is typically not allowed while servicing the NMI the interrupt would not be recognized until the end of the service routine. At the completion of the NMI service routine the processor would be interrupted to service the hardware interrupt and this ISR would clear the interrupt source and post to CMA4 that would wake up the task. So these are the references used for this session. Thank you.