 We shall begin with today's class. What we are going to do is that we are going to continue a little bit on the device basics that we had started with on the first day. Because we want to understand how MOS devices actually operate and how logic can be constructed. Then after that we will look at a few of the parameters of logic design and then we will go over to specific logic design using TTL and CMOS circuits. There is a set of nodes that I have uploaded today to the model site for CMOS and NMOS logic design. Please notice that these nodes are much more detailed than what is expected of a basic electronic course. So, it is because we believe that teachers should be at least one step ahead of the students that the treatment in this as well as in my previous basic electronics nodes. The treatment is one step higher than what you expect the students to understand. Please exercise your choice in what you include in the lectures to the students themselves. That said let us now first of all review the things that we had done in the very first lecture. So, what we had done about semiconductors was that you have N type and P type semiconductors. It is made N type by donors and P type because you have added acceptors that donors are normally ionized at room temperature and because they have donated an electron they are positively charged. So, they become ions because they are fixed in space and they are positively charged and acceptors because they have accepted an electron become ions which are fixed in space and are negatively charged. In addition to that we have free electrons and holes. In many discussions on Moodle and through email we have seen what is the difference between a hole and a positively charged ion. So, the point is that the ion is an impurity atom it cannot move the positive charge is held by the atom and therefore, it is a static charge. In case of a hole also an electron has been taken away, but the location of the electron deficient atom changes because there is a transfer of electron from one atom to the next. As a result the atom which was earlier electron deficient is no more electron deficient and its neighbor from whom an electron has been taken now becomes electron deficient. So, therefore, the main difference between ions and holes is that the apparent the actual location of positive charge changes as electrons transfer and the location of the positive charge cannot change in case of an ion. So, now we have four types of charged objects in this there are positively charged donor ions, there are negatively charged acceptor ions, there are negatively charged free electrons and there are positively charged mobile holes. So, these are all the charges which are there inside a semiconductor we had also seen through numerical examples that in fact, the majority carriers are very much more numerous compared to minority carriers which makes it possible to ignore the charge from minority carriers under many circumstances, but we should be careful to make sure that we are operating in a condition where this is indeed true. We now want to look at the band diagram of these semiconductors I had mentioned this in response to various letters on moodle and also during the class if this is the energy level of the free electrons and that is called the conduction band. This is the energy level of those bound electrons which are in the outermost shell and can be easily transferred from one electron deficient one atom to an electron deficient atom and thus lead to hole transfer. So, that is called the balance band this is the least bound of the bound electrons and this is the band gap. We had also seen that these statistics of carriers is controlled by this equation which comes essentially from the equilibrium between the creation and inhalation of electrons and holes. So, we had seen that in equilibrium condition you always have the product of n and p to be the same what it really means is that therefore, the logarithmic value of the two sides leads to log n plus log p that is equal to constant it is indeed twice log n. Now, the point is that this equation provides a constraint on the number of electrons and holes you can specify one kind of carrier, but then the other kind of carrier is not free to attain any value its value is then fixed by this equation. So, there is indeed only one free variable and we can visualize this free variable by putting the constraint in this logarithmic plane as we have said. So, let us define a quantity called n by n i which is the normalized number of electrons to their concentration under intrinsic conditions. So, in that case this could be written as log of n by n i plus log of p by p i equal to log of 1 which is 0. So, these two being constant essentially what it means is that as electrons become more than n i holes actually become less than n i. Now, suppose I was to represent this log n and log p by some distances in that case what we are saying is that suppose I was to represent in the energy plane this concentration log of concentration of holes by this distance then the value of electrons is already fixed it is not free anymore. In that case provided I have chosen appropriate normalization constants in that case the number of electrons is always given by this. If you tell me that there are this many holes then it follows that there must be this many electrons. So, therefore, it is this level which determines the concentration of both electrons and holes what we are saying is that the concentration of electrons and holes are not two independent variables there is only one independent variable which simultaneously determines the concentration of electrons and concentration of holes because of the constraint provided by this equation. And that is graphically illustrated essentially by putting this energy level in the band gap and this energy level is called the Fermi level. Now, notice that the energy is given by minus q times a potential when you have a potential electrostatic potential multiplied by minus q and that gives the energy of the that gives the energy of an electron because the electron carries minus q charge. So, therefore, corresponding to E F there is a value of phi f the Fermi potential. If you multiply the Fermi potential by minus q then you will be able to plot it in this energy diagram because this is the diagram of energy. So, we can define a Fermi potential phi f and multiplied by minus q and that will then give us this phi f turns out to be k t by q this provides that normalization l n of p by n i this ratio. Now, in this essentially what we have done is we have shifted the 0 of this energy. So, let us calculate find out where the 0 of this energy lies. Suppose we have an intrinsic semiconductor in that case n is equal to n i and p equal to n i and in that case how much is this potential? We have p divided by n i which will give you 1 its natural log will be 0 and therefore, the Fermi potential is 0 and correspondingly the Fermi energy is 0. So, when electrons are equal to holes in an intrinsic condition then we know that these two distances will be equal because these distances are just proportional to logarithm of the concentrations of electrons and holes. So, therefore, the midway point of this band diagram is called the intrinsic Fermi level because when the semiconductor is intrinsic we are at 0 distance from this point by this formula. When the material is p type then this number is greater than 1 and we have a positive Fermi potential and therefore, by this formula a negative energy compared to the intrinsic level. That means the Fermi level will be found below this. On the other hand if p is less than n i as would happen for an n type semiconductor in that case Fermi potential will be negative and the corresponding Fermi energy will be positive and therefore, it will be found above this at some level. Now, all of this is repetition this is what we had done just to remind you I have just taken it up. We now want to consider the MOS structure with which we will be doing most of our electronics. So, consider a structure in which you have metal here and first let us not even go to MOS transistor. Let us go to the plane and familiar parallel plate capacitor which we have all done from school onwards. So, suppose you have two metal plates and with an insulator inside separating the two. We know that the capacitance of the parallel plate is given by the dielectric constant times the area of these plates divided by d where d is this distance in the insulator. Let us however, understand physically what this capacitance implies. Suppose I put some charge on this and let me plot this capacitance as a function of 1 by d and now what I am going to tell you is that the capacitance is actually not fundamentally dependent on d. It is fundamentally dependent on the distance between the charge that we place on one plate and the corresponding induced charge on the other plate. So, in fact, d should ideally be in the most general case the distance between the charge that you place and the induced charge that it creates. So, suppose you were to place some charge delta q on this and assume that this charge is plus what will happen to the lower plate. Well clearly a charge minus delta q is to be induced in the lower plate and negative charges will be attracted by this positive charge. So, there is a force of attraction between this positive charge and the induced negative charge which is here and as a result these carriers will try to come as close as possible to each other. As a result all of this plus delta q will be found crowding at the lower end of this metal and similarly the induced negative charge will all crowd around at the upper end of this metal plate because in this state the electrons and holes are positive and negative charge are as close as possible they cannot come any closer because this is an insulator and the charge carriers cannot enter the insulator. Therefore, the distance between the causing charge and the induced charge is exactly equal to the thickness of the insulator and it is for that reason that you have d here in this expression. Let us now generalize this structure and remove this lower plate and put a semiconductor here. For the sake of argument let us say that this insulator is the oxide of the semiconductor typically silicon and you have the semiconductor here and it is this structure which gains the name to the MOS transistor that is metal oxide semiconductor. Let us do the same experiment now and for the sake of argument assume that this semiconductor is p type dope to 10 to the power 16 per centimeter. These are numbers that we have taken earlier and we are familiar with it. Notice that the electron density in this case was about 2.25 into 10 to the power 4 because n i is 1.5 into 10 to the power 10. Now, given that if you put positive charge on this negative charge is required here and I will reproduce our earlier discussion and classify it according to charges. What is positively charged? Donors, donor ions are positively charged and holes are positively charged. What is negatively charged? Well, acceptor ions are negatively charged and electrons are negatively charged. If I have put some positive charge here then I need negative charge here and if I put some negative charge here then I need some positive charge in the semiconductor. Let us consider both these cases separately. First of all if you make the gate negative and put some negative charge on this metal then you need positive charge in this p type semiconductor and what is positive in the p type semiconductor? Well, there are no donor ion ions because this is p type we have put only acceptor ions here. There are no donor ions therefore, there is no positive charge available from ions. The only charge available is from holes and holes are mobile. As a result when I put negative charge here I have negative charge here, the charges here are mobile and they will do exactly the same thing that this metal parallel plate capacitor did that means the negative charge will come as close as possible to the insulator and the holes will come as close as possible to the surface of the semiconductor and they cannot come any closer. The holes cannot jump into the oxide, oxide is an insulator and the negative charge in the metal plate cannot come any closer because it is it cannot inject charges into the oxide. So, they come as close as they can and that is the same distance d here and as a result if my applied voltage is negative then on this plot the capacitance remains constant and is given by this same expression epsilon a by d. So, this is not very interesting this is the same as the metal parallel plate capacitor that we had learnt about. On the other hand suppose I was to put positive charge on the metal plate. So, now we are considering the case when you have positive charge on the metal plate. Now, if you have positive charge on the metal plate you require negative charge on the other side of the insulator and what is negative except the ions are negative and electrons are negative, but we already know that the number of electrons in a p type semiconductor is pitifully small, extremely small number of electrons exist in this. So, no considerable amount of charge can be provided by electrons. If you need negative charge the only way is to have acceptor ions there which will provide the charge. So, as a result what happens is that when you make this positive then holes which are in plenty in this p type semiconductor are now driven away from the surface and they leave the exposed ions here and it is the ions which are immobile which are fixed in their positions they provide the negative charge. So, as a result a slab of this electron is now devoid of holes and the exposed acceptor ions which are negatively charged as we had seen here they remain here. A very important difference is now taken place and that is that the answering charge to every incremental positive charge will have to go deeper and deeper into the semiconductor. If I put some more positive charge here the additional negative charge cannot come from this slab because all the ions are already accounted for. Now, new ions have to be exposed and as a result additional ions will have to be exposed from this region and therefore, the responding charge is further away from the causing charge and this will continue as I put more and more charge. So, as a result the capacitance is no more constant it starts reducing because the effective distance has become more. How long will this continue? Well the answer is that holes and electrons are not independent and as you drive away holes start reducing in number, but as holes reduce in number the number of electrons must come up. At some point it will so happen that the number of electrons which is going up now becomes as high as the holes were to begin with. That means, it is possible that the number of electrons now starts becoming 10 to the power 16 and then the concentration of holes has dropped to a few tens of thousands as it was the other way round in the beginning. If you now look the major negative charge can come from electrons because there is a plentiful number of electrons available. As holes have reduced electrons have increased and as electrons increase they can become the majority carriers in this and then their numbers will be of the order of 10 to the power 16 or what have you and the number of holes will be only 10 to the power 4. Since there are no holes left you cannot remove them to expose the extra ions and since there are plentiful electrons available. Now, the answering charge will be by way of electrons and not by way of extra ions and as a result the electrons which are mobile they will move to the surface and the original condition will now prevail that the causing charge which is here and the induced charge which is electrons is here and you are back to the original value of capacitance. So, essentially you reach a stage this is the voltage across the capacitor this is the capacitance and you reach a stage after which suddenly the capacitance will recover back to its parallel plate capacity. This is the characteristic at low frequency of MOS device. If on the other hand if you put and remove this charge very very quickly then there is no time for carriers to be generated and move and in that case the capacitance becomes constant and remains at this low value. So, this is the C at low frequency this is the C at high frequency in either case the total capacitance corresponds to this maximum width of the definition which is caused by this by holes being question. So, this is the MOS capacitor notice that even though this semiconductor is p type just the surface has lots and lots of electrons and therefore, it is almost like an n type semiconductor. This effect is called inversion and now what I am going to do is to put two n plus pockets on either side of this inversion and make an MOS transistor this terminal is now called the gate. Now, notice when this gate voltage is either negative or small enough positive then inversion has not occurred and I have an insulating silicon separating this n plus to n plus the rest of the silicon is p type and therefore, I have this back to back diodes n plus p and p n plus and irrespective of what polarity voltage I apply between these two terminals no current will flow because at least one of these diodes must be reverse back. So, as a result I shall not be successful in sending current through from one terminal to the other. However, once this voltage exceeds this voltage and which is called the turn on voltage at this point the surface of this p type semiconductor will turn electron rich and therefore, n type and now I have a continuous path of n type n plus n n plus from one terminal to the other and now current will flow. An interesting question now comes up let us say that I have put some voltage like let us say of the order of a volt on this gate and this is higher than the turn on voltage. Now, in that case if I am one volt above the turn on voltage then the amount of charge which is required from the inversion that is equal to C ox into one volt. So, I need this much charge from electron now the order of magnitude of C ox per unit area is of the order of 10 to the power minus 7 farads per centimeter square that means, if I put a volt above that turn on voltage then the amount of additional charge that I need from electrons is 10 to the power minus 7 coulomb per centimeter square. Now, how many electrons is that if I want 10 to the power minus 7 coulomb how many electrons is that well each electrons carries 1.6 into 10 to the power minus 19 negative charge this is indeed the value of q. So, therefore, to provide 10 to the power minus 7 coulomb I require 10 to the power minus 7 divided by 1.6 into 10 to the power minus 19 that is roughly 6 into 10 to the power 11 electrons per centimeter square. Now, what was the electron density the electron density was in the bulk of this semiconductor was of the order of 2.5 into 10 to the power 4 per centimeter cube. Now, if you assume 1 centimeter square area then how much volume of silicon will be required to find 6 into 10 to the power 11 electrons. So, you will have to go 6 into 10 to the power 11 this is the number of number of electrons that I want and in a depth of 1 centimeter I have 1 centimeter square area and a depth of 1 centimeter that is 1 centimeter cube and I have only 2.5 into 10 to the power 4 electrons in that volume. So, therefore, if I divide by this 10 to the power 4 which is roughly 2 into 10 to the power 7 centimeters that means my semiconductor will have to be 2 into 10 to the power 7 centimeters deep. Well, that is 2 into 10 to the power 5 meters which is 200 kilometers. Obviously, my semiconductor is not 200 kilometers deep 200 kilometers is from here to Pune nearly my semiconductor is not that deep and therefore, that many electrons are not easily available in this semiconductor. The question is where will these electrons come from and the answer is that you have applied a voltage to these 2 n plus pockets these are these are very rich in electrons you want 10 to the power 11 they will have 10 to the power 19 electrons. So, they come and volunteer quickly it says 10 to the power 11 electrons no big deal here they are that is just a small fraction of the number of electrons I have. So, those electrons are quickly provided by this n plus pocket. Now, if one of them is positive and the other is negative then the positive terminal is going is not going to give away electrons it likes electrons it attracts electrons that is not the one which is going to give these electrons. On the other hand the negative terminal repels electrons and that is the one which is going to say all right I have too many electrons take them and as a result the negative terminal is called the source it is the source of these carriers. And the other side as you inject these electrons keeps on taking them out as if it was a drain and hence the positive terminal is called a drain and now current flows. So, more and more carriers are injected by the source these are collected by the drain a steady current flows and as a result a concentration of electrons steady equilibrium concentration of electrons is established here which is equal to C ox times 1 volt which we have. So, this is what happens and you have current flow in this MOS transistor. So, I think I have now explained the basics of an MOS transistor there are interesting things which happen very much like the JFET. So, like the JFET saturates so does the MOSFET unfortunately we do not have time to do it in that detail the nodes that I have put down has the details and we will look at some of the aspects as we go along for logic design. So, this MOS transistor then has characteristics of this kind I have plotted the drain current as a function of drain voltage here and below some voltage like 1.0 here there is hardly any current flowing that is the turn on voltage. So, turn on voltage here might be 0.6 or 0.8 or there about for any voltage higher than that current flows and it increases with the drain voltage up to a point and then saturates this is the pinch off condition just like the JFET case that we had seen. So, in short first look at these V G value and for V G values below about 0.8 volts or so no current will flow at all. However, for any value above this value and let us take this one 2.5 volts we notice that initially the current increases with V D and then it reaches some saturation voltage and beyond that as you saw for pinch off case in JFET the MOS also pinches off and as a result we now have steady current which remains constant and this is called the saturation the transistor is set to be saturation. Be a little careful about this terminology by the way a bipolar transistor is considered to be in saturation in this curved region and is supposed to be in the active region here. The terminology for MOS is opposite the MOS is set to be saturated here and is set to be in the linear regime here. This difference is because bipolar transistors are current operated devices whereas MOS is the voltage operated device the output is current and here because the current is not changing anymore it is this region which is called the saturation. In case of a bipolar transistor you are using it as a switch to reduce the voltage and when it reaches this region you say it cannot reduce the voltage because of current flow anymore and therefore, that is called the saturation region. So, be very careful there is a difference of absolutely opposite convention for MOS device as opposed to bipolar transistor this region is called the saturation region for MOS transistor and this region is called the linear region because the current initially starts quasi linearly here. Now, the characteristics for this are given by this the first equation says that if the gate source voltage is less than v t then irrespective of anything else the current is 0. If the gate source voltage is greater than v t and this drain source voltage is less than v g minus v t then we are in the quasi linear regime and the current is given by this equation which is a function of v d s. However, once you once the drain source voltage exceeds this value you are in saturation the current becomes constant and independent of the drain source voltage and as a result the current is then given by k v g s minus v t whole squared by 2 it is not a function of v d s anymore and therefore, as plotted as a function of v d s it shows up as flat it still depend on v g s minus v t of course. So, the current is different for different values of v g s even in this linear regime, but it is independent of v d s. So, this is the transistor that we are going to use in our design equations. Please notice that this is an extremely simple model the real transistors are complicated beast and particularly so for modern short channel transistors. Those of you who are interested in devices might want to look up some modeling books or some solid state electronics books to see how more complicated models are developed for transistors, but for us for basic electronics this model is adequate and this is the one that we will be using. When the channel is short then actually the current does not quite become saturated and then it increases sort of linearly in this region and this is like the early voltage for a bipolar transistor. So, the corresponding effect because of channel shortening is there for the MOSFET also and there are equations corresponding to that they are written here in your notes, but they we shall not be using these more complicated equations most. So, now let us go to a somewhat generic discussion of logic. In digital design we want the output to be either 0 or 1 and we do not care what is the exact value of the voltage when it is in 0 logic state nor do we care exactly for the voltage. If it is high enough it is 1, if it is low enough it is 0 and we are never concerned in the detailed value of this voltage. So, how do we ensure that? Well we have we use special electronics in which the transition from low voltage to high voltage is very quick. So, that the electronics does not spend any time in that in between region where we may have a doubt whether it is low or high. In short we are talking of essentially in the ideal case two switches these switches are controlled by some input and we take the output from here. This is the supply voltage and as for bipolar transistors it used to be called V c c the fixed voltage connected towards the collector. This is because it is connected towards the drain side of an n channel transistor this is called V d d in case of MOS logic. Let us say this is positive. Now suppose you want the output to be 1, what should be the state of these two switches? Notice that the upper switch shorts the output to V d d therefore, if you want the output to be 1 that is what you want you want the output to be close to V d d. In that case if the output should be 1 or high we are using positive true logic here then the upper switch should be on. At the same time we have to ensure that the lower switch is off because at if at any time if both switches are on in that case we will be shorting V d d to ground and our power supply will have to provide infinite current our switches will burn out. So, in no case should both switches be on. So, therefore the lower switch should be off. If we want the output to be 0 or low then obviously the lower switch should be on because we want to connect the output to ground and again by the same argument the upper switch should be off because if that is on then there will be a short all the way from V d d down to ground. So, therefore for output equal to 0 or low the upper switch must be off and the lower switch that means exactly one of the switches should be on at any given time and exactly one of the switches should be off at any given time. That means we should never have both switches on never have both switches off if both are on then as we had discussed earlier there will be a dead short from V d d to ground and that we do not want. On the other hand if both switches are off then this output is floating and it could acquire any voltage and there is nothing to put it pull it high or low. So, that is also an improper condition under this and therefore we need to have at least one of the switches and exactly one of the switches to be on. And as a result ideally what we would like is that whatever turns this switch on automatically also turns this switch off and similarly whatever turns this switch on should automatically turn this switch off and this is something which is provided by the MOS transistor that we have just learned. Let us look at it we learnt the NMOS transistor which was made in a p type semiconductor and if the source is grounded if this metal is positive then this acts as a switch and current flows therefore it is on. At the same time if this is negative or 0 below V t in that case this looks like an n plus p p n plus diode and therefore it can never conduct because at least one of these diodes will be reversed by it. So, therefore if this voltage is less than V t then this switch is off and if this is positive more than V t then this switch is on. But we could have constructed the counter part of this transistor we could have constructed an MOS transistor in which this semiconductor is n type and I put p plus type of pockets here. We have an oxide or an insulator here and we put metal in reality this metal is very often poly silicon and not really a metal and that has technological reasons for it. In this case when will this conduct? Now notice that for conduction to take place even though this semiconductor is n type I must invert it to p type by attracting holes to the top and then I will have conduction p plus p p plus. But when will holes be conducted to the surface? Only if the metal is negative with respect to this right. So, the source should now be positive after all it has to provide holes. So, the source should be positive the drain should be on the negative side and with respect to the source the gate must be negative. So, now we have the happy combination the same input namely a high voltage which turns this guy on will turn this guy off and a negative voltage will turn this guy on and this guy off. This is precisely what we were looking for in logic design and therefore, we can construct an inverter. This inverter will have a p channel transistor on top and n channel transistor at the bottom and now I can use the same input to convert the switch from on to off off to on and take my output from here. And let us see what happens in this case? Notice that V d d is positive therefore, the upper end is positive the lower end is negative. So, which is the source which is the drain for the n channel transistor? The more negative end was the source of electrons the more positive end drains electrons by pulling them. Therefore, the source for the n channel is here the drain is here. On the other hand for p channel we must source holes and only the positive terminal can source holes. Therefore, this is the source and this is the drain. So, in short the 2 drains are shorted together and the output is taken from the junction of the 2 drains. The n channel source goes to the to ground and the p channel source goes to V d d and the input is applied to the gate. Now, if the input is towards the ground then this guy turns off, but the gate is largely negative with respect to the source which is at V d d. Therefore, this guy turns on and the output becomes high. At the same time if the input is low then for a low input meaning towards ground that is what we have seen that this guy is on this is off output is high. If the input is high then this transistor turns on and this transistor turns off because this is high and therefore, there is not enough negative voltage here and this being high is enough to turn this on. Therefore, the output is connected to ground and this connected from V d d and therefore, the output becomes low. Therefore, this circuit is called an inverter. When the input is high the output is low because this transistor is on, this is off. When the input is low this transistor is off that transistor is on and as a result the output is high. So, the output is in an opposite state to that of the input and therefore, this is called an inverter. It converts 1 to 0, 0 to 1. Let us look at the transfer characteristics of this and as an inset I will draw the circuit that I had. By the way for a p channel transistor I will use this symbol which has a bubble here which shows that if it is negative then it will turn on. Without the bubble the same symbol means an n channel transistor and the equivalent of this is that there is this acts as a switch. The other transistor also acts as a switch and this switch is on when the input is negative, this switch is on when the input is positive and there is a quick transition from high to low as we go. So, if you look at the characteristics what happens is the following. As I start from low voltages though this is I am plotting output voltage versus input voltage. Remember the transistor characteristics are that the input voltage has to be at least a v t positive or negative with respect to the source for conduction to take place. As I apply input and start increasing the input in this particular case till I reach v t n till I reach v t n the n channel transistor is off the voltage is less positive compared to its threshold voltage. At the same time compared to v d d since this voltage is quite low at this point there is a large negative bias on this p channel transistor and therefore, this transistor is on and as a result the output is equal to v d d. If I go beyond this point then the n channel transistor starts turning on. As a result it draws current and because both transistors are now on it acts as a potential divider and you get a voltage which is half way between v d d and ground that means the output starts decreasing towards ground. When this voltage becomes high enough that it is close enough to v d d so that the negative bias between here to v d d is less than the v t of the p channel transistor. The p channel transistor now turns off and now it is high enough for this to be fully on and as a result the lower transistor is connected the upper one is not and as a result the terminal becomes the output becomes 0. So, we have transfer characteristics of this kind. We now must define how high is high enough and how low is low enough. So, we will look at it qualitatively in this lecture detailed quantitative work is there in the lecture notes that I have uploaded and we shall now go over to that set of slide to see exactly what happens. So, this is the transistor, this is the stage that we had just talked about. You have the p channel transistor on top, you have the n channel transistor on the bottom and then you have a capacitive load and this is the input voltage and you can see that you will get characteristics like this. Now, let us mark off various parts of this characteristic as the input voltage is small enough the output is fully v d d and till the input voltage reaches the turn on voltage of the n MOS the n MOS is off and p MOS is on. So, this is that region where the n MOS is off and p MOS is on till we reach the v t of that and till that time the output voltage will remain v d d. After that the n MOS is saturated it is in saturation because the output is high and its drain is high the p MOS is in its linear regime and the output starts dropping. Finally, both will be saturated then as the voltage reduces n MOS will become linear p MOS will be saturated and finally, you will reach a situation at which n MOS is on and p MOS is off and you will reach 0 volt. Now, the way to solve is that notice that the v d s of the p channel transistor the v d s of this p channel transistor and the v d s of this n channel transistor must add up to v d d. Therefore, v d s for n channel transistor v d s is nothing but v output because this is this is the voltage between the drain and the source this is output. On the other hand for the p channel transistor v d s is this which is v d d minus v out. Similarly, v g s the gate source voltage remember this is the source. So, v g s is nothing but v in for the n channel transistor whereas, for p channel the input volt the v g s is measured from the source terminal which is v d d. Therefore, the mod value of v g s remember it is negative this is equal to v d d minus v in. So, the n channel v d s and v g s are v out and v in respectively the p channel v d s and v g s are v d d minus v out and v d d minus v in. Putting these we can now compute the current through this and compute the current through this and if we put these two currents equal remember these currents will be a function of v out because of this dependence. So, if we put these two equal then we will get the value of v out by solving that equation because these two currents must be equal they are connected in series across v d d and ground. Therefore, same current should flow through the two in a steady state condition and by equating these two currents the only unknown is then v out and we can evaluate the value of v out and if we now plot it then we will get quantitatively this curve. So, essentially taking in all these regions the value of i d for the two transistors and putting it equal you will get all sorts of solutions and I am going to you can read the details later, but I am going to skip the quantitative part of that and come to this consideration of noise margin. In a real case there is going to be noise and it should not happen that a level which is low because of the presence of noise is considered high for a short time. Therefore, the definition of the low level and the high level should be sufficiently apart. So, that even in the presence of noise the low level should not pretend to be a high level nor should a high level pretend to be a low level because of the noise. Therefore, we have we now have to design the levels and these have to be defined separately for input and output that means the output high level should be much greater than the value which is considered high by input. So, that even if there is noise the reduced possibly reduced value of this voltage is still higher than the input high value. Therefore, the output high should be greater than the input high. Similarly, the output low should be lower than the value which is considered low at the input and these differences are called the low noise margin and the high noise margin. That means this is the amount by which my output is better than my input. So, that it gives me robustness against noise. So, if my output is high even though some noise may pull it down it would still remain high compared to what is considered high at the input of the next stage. Similarly, if my output is low it may be pulled high by noise, but it would still remain low enough that it is considered low by the next stage even in the presence of noise. So, this is the requirement for robustness.