 Hello and welcome to the series of video lectures on the subject microprocessor for secondary IT students. I am Dr. Srisail Sharadkarjbar and in this video lecture we are going to study the architecture of 80386 microprocessor. At the end of this session you will be able to write key features of 80386 microprocessor. You will also be able to describe architecture of 80386 microprocessor. Intel 80386 was the first 32bit microprocessor. A major no feature in the 80386 microprocessor was its protected mode. Although the protected mode was also available in 80286 microprocessor, the protected mode in this microprocessor case is very advanced. The protected mode in this microprocessor fixed many shortcomings that existed in 80286 microprocessor and its protected mode. Let us see some features of 80386 microprocessor. The 80386 included complete set of 32bit registers and 32bit instructions queue. It has 32bit address and 32bit data bus. These buses are not multiplexed unlike its predecessor microprocessors that is 80386 has dedicated address and data bus. Since it has got 32bit address bus it can address 2 raise to 32 that is 4GB of physical memory and 64TB of virtual memory space. Apart from memory segment architecture 80386 microprocessor introduced one more memory architecture namely the paging system. The memory management unit provides virtual memory, paging and 4 levels of protection. The concept of paging enables it to organize available physical memory in terms of pages of 4k size under segmented memory. It became possible to switch from protected mode to real mode without resetting the processor. The 80386 has a family of scale modes which is a special kind of addressing mode. And in case of scale modes any of the index register values can be multiplied by a scale factor 1, 2, 4 and 8 to obtain the displacement. It introduces 2 or more segment registers namely FS register and GES register. Now pause the video for 2 minutes and write down the answer of the given question. I hope you have written the answer. The answer is 4GB of physical memory and 64TB of virtual memory can be addressed by 80386 microprocessor. Now let us see the architecture of 80386 microprocessor. The architecture of this microprocessor contains 3 main units namely the first unit is the central processing unit, the second unit is memory management unit and the third unit is bus interface unit. Now let us see each processing unit in detail. Let us first see the details of central processing unit. Central processing unit internally consists of 2 main parts namely execution unit and instruction unit. The execution unit performs the arithmetic and logical operations. It consists of 8 general purpose and 8 special purpose registers which are used for handling data and calculating offset addresses. The instruction unit decodes the opcode bytes received from the 16 byte instruction code queue and arranges them in a 3 byte instruction decoded instruction queue. After decoding the instructions it passes them to the control section for generating the necessary control signals. The barrel shifter increases the speed of all shifts and rotate operations. The next unit is memory management unit. The memory management unit consists of a segmentation unit and a paging unit. The segmentation unit allows segments of size 4GB at maximum. Segmentation provides a mechanism of isolating individual code, data and stack modules so that the multiple programs or tasks can run on the same processor without interfering with each other. When operating in protected mode some form of segmentation must be used. Segmentation gives a mechanism for dividing the processor's linear address space into smaller protected address spaces called segments. Segments are used to hold code, data and stack for a program and to hold system data structures. Each program running on a processor is assigned its own set of segments. The processor enforces the limits between segments and ensures that one program does not interfere with the execution of the other program. The segmentation unit provides a four level protection mechanism for protecting and isolating the system code and data from those of the application program. Paging provides a mechanism for implementing a conventional demand-paced virtual memory system where sections of a program execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation between multiple tasks. The segmentation scheme may divide the physical memory into a variable size segment but the paging divides the memory into a fixed size page. The paging unit organizes the physical memory in terms of pages of 4KB size each. Paging unit works under the control of the segmentation unit that is each segment is further divided into pages. The virtual memory is also organized in terms of segments and pages by the memory management unit. Paging unit converts linear addresses into physical addresses. The control and attribute programmable logical array that is PLA check the privileges at the page level. Each of the pages maintains the paging information of the task. The limit and attribute PLA check segment limits and attributes at the segment level to avoid invalid accesses to the code and data in memory segments. Each of the pages maintains the paging information of the task. The limit and attribute PLA check segment limits and the attributes at the segment level to avoid invalid accesses to code and data in memory segments. These two mechanisms that is segmentation and paging can be configured to support simple single program systems, multi-tasking systems or multi-processor systems which can be used with the shared memory concept. Now let us see the bus interface unit. The bus interface unit has a priority resolver to resolve the priority of various bus requests. This controls the access of the bus. The address driver drives the bus enable signals that is B0 bar to B3 bar and address signals A2 to A31. The pipeline and dynamic bus sizing unit handles the related control signals. The data buffers interface the internal data bus with the system bus. The bus controller generates various control signals such as read bar, write bar and ADS bar that is address status signal etc. The cache control unit is used to provide the controls for internal cache. These are the references. Thank you very much.