 I think we have done this much part okay. So we say defam can be solved using a half circuit method and the condition we said that the system should be symmetric across some vertical line and then left side and right side can be independently handled okay. And we are shown last time some theorem which is given in Razawi's book and using the same method and across this there is a symmetry. Please remember here one of the thing I assume that it is a differential system what did I say v1 v2 are such that one rises by delta the other decreases by delta but this is not a really a condition we will prove that this is not necessary but initially we assume that that should be necessary part now I show you that is not really necessary but first let us prove if it is assumed that typically this opium can be converted into half parts and you solve output voltage at this by a simple amplifier minus gm1 rd parallel r1 similarly you do for the other side which is vy by minus delta vn1 which is vy upon this minus gm2 rd1 rd2 and if I subtract or add whatever it is I will get gm1 rd1 parallel r1. Now this idea that av dash 0 which is essentially when I say r o equal to r o2 is equal to rd1 equal to rd2 gm1 is equal to can be reduced to 2 gm rd and rds are smaller normally than r0 and it is same 2 gm r o nothing very great appears we can do it analysis which is much more rigorous which we have been doing all the time. So there is a second method which I am not showing you read from the Raza's book which is actually a circuit technique what essentially they will do for example they will assume that one of the input is grounded v2 and then see the performance influence of vn1 on v o1 and v o2 then they will figure it out what is the vn1 is 0 and then and then they superpose the results to get the net gains so that is a very standard technique of superpositions. So lead that other technique which is more popular circuit technique this was shown to you because defam shows symmetry and therefore it is much easier to solve this this method it is not that this is the method or something but if you see something simpler you probably go through it please remember in that case if you are using this this will be driving this so some kind of a source follower outputs are given to the common gate or common source system vice versa and then you have to do some real analysis to get the normal analysis done which probably you can read in case some of you did not find that okay or not understood come to me individually I will solve for it that is nothing very big but this method I liked it very much because for a defam case at least this is very good and simple yeah in the region of v o vn circuit is linear devices are in such you are right. So there is an issue if you are looking a difference gain as v o 1 minus vn 2 upon v in 1 minus v in 2 which is called AV difference mode then this will become gm rd parallel r0 that 2 will go away that is that is only thing however the point which we actually took care in all our definition so far we said the v in 1 v in 2 are such that they are differential what does that mean we said if one changes by plus delta v in the other must go down by delta but that is not very necessary as I show you later okay this is a good condition to start with and we still say it can be still doable even if they are not fully different we can see that v in 1 can be broken into v in 1 by 2 plus v in 1 by 2 then we can add half v in 2 by 2 and subtract half v in by 2 in series power supply 4 in series such that v in 2 cancels otherwise and v in 1 adds so this is still v in 1 is that okay v in 1 2 v in 1 2 they are in series so v in 1 this is opposite v in 2 are opposite in pluralities equal so they cancel so this can be written as 4 supply in series v in 1 2 plus v in by 2 minus v in by 2 plus v in by 2 keep doing this any number if you have this now this is 4 similarly I can say if this is so that I can write then I v in 1 plus v in 2 by 2 and v in 1 minus v in 2 by 2 so the statement that this can be represented by 2 such series power supplies or supplies or signal supplies now you can see from here what is this value could be looking for v in 1 plus v in 2 by 2 it is defined as common mode voltage which essentially can occur because if v in 1 is equal to v in 2 so v in 1 plus v in 2 by 2 is v in 1 so it is essentially saying it is a common mode voltage whereas subtraction is difference so any signal therefore can be represented as common mode signal plus difference mode signal because at the end why I said defam what is the important characters of a defam that it rejects all common mode signals as much as possible so now we are representing this into series combination of common mode signal and this similarly I can do it for v in 2 on the other side okay and I am not saying it should be this I repeat this is that okay okay so equally saying I have a two sources in something like this and only thing is you can see here v in 2 minus v in 1 here v in 1 minus v in 2 because that is what the values you had and correspondingly you wrote this and then we define as I say a common mode voltage v c m is v in 1 by v in 2 and difference mode signal is v in 1 minus v in 2 is that okay so this representation of the so now I am not saying that it goes delta this my I am not saying I say whichever it is I will break into equivalently this which will always give me some common mode signal and some difference mode signal okay. Now the idea behind all this game was that what is the gain for this and what is the gain for v c this since there are two sources now okay so we say what is the method we will use we will figure out the gain for difference and we are get the gain for common mode and check it whether one is much higher than the other or vice versa whatever happens we will see what is and if it so happens that the of course there is another term which you should know there is called common mode gain converted to differential mode so it is called a v c m dash d m okay which will calculate is that okay this is only a definition everyone knows for last so many years I have not figured out anything I do not got anything great new thing in this I repeat I just broken the signals into common mode and difference mode signals you can see this is plus v i d by 2 this is minus v i d by 2 v c m is same that makes my job much easier because if v c m is same on both cases then the circuit will become even simpler so I have now two signals one is plus v i d by 2 minus v i d for the difference mode and for the common mode I have another equivalent circuit we say where it is common to both v c v n c m individually putting is as much saying common to both okay so I have two circuit to solve if I can solve these two circuits then we know just now we did v x is minus g m 1 r d parallel r o 1 into v i d by 2 at this point output just now we calculate the other side is v y g m 2 this is since it is minus v i d by 2 I have put this plus so it becomes g m 2 r d parallel r o 2 v i d by 2 so I calculate difference again which is v x minus v y divided by v i d so which is nothing but g m 1 g m and let us say g m 1 is g m 2 equal to g m and r o 1 equal to r o 2 is r 0 what does that mean the two transistors are identical we will get rid of this also and say if they are not what will happen so if they are identical again becomes just g m r d which we just now calculate that nothing great happens however if you look at for this second circuit and do similar analysis v x minus where this this gives me since v x is equal to v y then both input will give same voltage outputs so the difference being 0 the gain is 0 see if I now take a ratio of a v d m to a v c m it is infinite that means at no time common mode signal will actually get amplified is that okay this is what essentially the main feature of differential the assumption in all this was I repeatedly say that why this cancellation we said is important because in real life when believes these two transistors will not be too far there may be two input signal lines or sometimes one ground in one other line in which case the noise may not over put separately for different places so assumption is if noise sits on this something same noise will put something on this and if that happens the common mode noise will actually get rejected so that is the feature this defense provide so wherever you are looking for rejection of noise you better try with a differential amplifier system in which you can reject common modes of course in real life we know VCM is not 0 it is some finite quantity so the ratio of a v d m to a VCM is not infinite but large enough in finite numbers that value we will call it as common mode rejection ratio slightly different different way we will explain that but that is what we are looking for is that okay so what is the defam property it will only amplify differential signals but not amplify or actually will be not amplify anything output will go to 0 difference if they are common modes please remember individually you will still can get outputs single stage coins but difference of them is 0 please remember VX is same as VY it does not mean VX is 0 and VY is 0 is that okay so this issue has to be clear that transistor is amplifying it is not leaving its job still amplifying but both side being identical outputs reach identical and therefore the difference of the two is 0 okay that is the reason why we say it rejected so if you only pick up output here say oh there is a noise reading yeah noise is riding on it and amplified noise is riding on it okay but the other side is also riding the same way so if I take difference the common part will cancel and that is how we say noise gets cancelled so please remember that if I make sometime wrong statement which you are very smart to catch immediately what I again say that I am never saying that VX is 0 or VY is 0 I am saying VX and VY are equal okay that is the statement I make even if there is some issue please come back is that okay these issues are actually all of you have done this earlier I am just trying to see how do we use them in defam design today of course will not be able to design we are going to design a defam at the end and there are certain other parameters of interest other than CMR one of course is the difference gain how much you have the other is we will like to know what is the common mode gain you get reality and we also will like to have more specification for a given defam two of the specification maybe I will tell today one is called output swing at the end of the day how much output is available to you from minimum to maximum is very crucial for the next stage okay therefore I will like to know what is the output swing and the most important among them is what is the possibility of device remain in saturation for any kind of VID that is minus or plus so the what is the minimum and maximum input which is possible for keeping devices in saturation this is called input common mode range ICMR so these two the another two more parameters which will look into later not today possibly is the power dissipation because for any design that may finally limit all your performance if I say this is one milliwatt that means we and VDD is so much the maximum current given to you is so much IDD into VDD is the power okay so once I say one milliwatt three volt two volt you divide and that is the maximum current drawable from the power supply okay so now you have to assign how much here how much here how much here the net current flowing from the power supply cannot exceed the given value for the given power and the last but not the least after all in a MOS transistors base any circuit there are hardly I mean though I am using RDS but they are generally not there we will like to have outputs driven driving next stages and what will be the next stage input impedances capacitive so they will be actually driving a capacitance okay so when you give input change how much the output takes time to change is called the slew rate how fast that is CDV by the zero how much current is available at the output for capacitive charge or discharge is very crucial because that decides the speed of the circuit or somewhere related to next stage how will it respond so another term which will actually lie these are terms why I am using same term because this is what open specs are by the way the circuit which we are just shown which will show now is the first stage of open okay the first stage of open is a difference defam so I am trying to use but the final specs also are same for either open or defam so I repeat I am looking for power dissipation I am looking for slew rate I am looking for output swings I am looking for ICMRs and I am also looking for difference gain I am also looking for CMRR there is another term which will come at particularly in the case of this which is PSRR we will see if power supply has some changes what it influences then the output will also have another parameter at least not in defam I will say I will put it finally to opam it is identical stage so I will solve all of them for opam so PSRR so that also is another important issue which you will have to address to so these are the specifications so normally what they will give you okay another thing which I did not say the bandwidth okay so far I am not putting capacitances so I am as if thinking there is no and then finally it will come from the bandwidth and bandwidth is something to do with not only the RC time constants you get but also on the FT value which the device is able to give you and I repeatedly saying you that typically 10th is what you should be able to use safely if your device has to operate in proper mode of operation okay now that is something we will talk about in the frequency response part that what is the bandwidth relations we have already solved one small problem you should say bandwidths and these are somewhere related because it is first pole or dominant pole is essentially related to bandwidth if many cases we solve assuming this is the dominant pole but in fact we will show you later those who have done my earlier device course I have used that method zero time constant method instead of using normal bode technique will show you that we can figure out at least quickly if not very quickly quickly what is the which is the dominant pole and if you get the dominant pole that is your bandwidth okay if you want to plot full bode plot that is all poles on zeros for stability purpose you will have to go through all transfer functions get all poles and zeros and plot it and find phase which is another terminology which will use later how much is the phase margin okay so there are other parameters will come in opamp so wait for that till then we will only look for defam characteristics which is the first stage of an opamp okay so is that okay so these are some issues we must address now so that at the time of defam opamp design I in my mind what I am designing at okay okay let me look into common mode again if you say vx is vy okay I join them and I there is a common mode signal which is v in cn sorry this this is here this is v in cn both are both side same as shown like this Rds are this so if you see it it is essentially equivalently saying and let us say this current source is not really ideal current source which is will never be in reality there is nothing called ideal current source so there will be some resistance associated with and that resistance is Rss okay so what I am saying is so if I say equivalent circuit for AC of course this is shown but that is actually going to ground I have Rd by 2 parallel combination and this is Rss with signal of v in cn equivalently this is a very simple amplifier which is this amplifier this is a common source amplifier with source degeneration okay so I have solved it I inadvertently did not realize that I should not solve so I kept solving and then I realized that I already solved this problem so I need not re-solve again but just for the heck of it the equivalent circuit is as shown here this is the Rss this is Ird Ird is minus Irss because sign is taken down okay in fact I should have taken sign up okay so that would have been same but does not matter the voltages would have changed in the sign then this would have been plus and that would have been minus so it is saying the same Ird which is v0 by Rd by 2 okay then vs which is the source voltage here is Irss times Rss but Irss is Ird so this is this Irss is minus Ird which is gm v1 plus current in this you can see the current here plus current here must be equal to current here which is Irss which is minus Ird so this method which we have earlier applied I am just rewriting you need not even rewrite this is exactly what we did earlier and just as I say inadvertently I forgot that I have done I keep solving thing then I realize why I am doing it I already done once okay this is not it normally what we will do in the most cases in the fans or something will source and bulk we are connecting most cases specifically but if not given just gm v must you can even now add gm v is not circuit we are already solved with gm v so it is not that we cannot but for the first take we always say the IC circuit will be allowing us of course in a long channel devices we always did that but in a short channel we cannot neglect gm v which at the end after when I say if I scale down what I should I will get hurt and how will I get out of it so that may be after all that I say okay from here to here what is the my problem which is your problem my time it was very straight forward I worked well nothing went wrong but now everything goes wrong so how to get out of it okay so this analysis please I mean those who wish to write figure it out but I do not think there is nothing great I had done just see the last expression all this is given by me earlier so finally v0 by vm same which we call a vcm is minus gm ro parallel rd by ro into rd by 2 upon rd plus 2 rd this is expression as we derived okay and if we say rss is much larger than gm 1 upon gm which will be rss is a current source output resistance it is very very large so this may reduce to firstly you may say minus gm rd upon 2 1 plus gm rss or if you say this is also true then it is minus rd by 2 rss this is same thing what we derived for source degeneration load resistance divided by source resistance that is exactly what we get however why we actually derived this because now we say that this a vcm is not 0 is that point here we are now saying at this at one end at least the voltages are is g rd by rss because rss is not infinite okay this is the most important part which I want to explain rss is finite and therefore one must say that the v0 by vcm will be finite and it will be minus rd by this is rd by 2 so this 2 is only coming because of that so rd by 2 by rss this is essentially we still assume that gm 1 is gm 2 ro 1 is ro 2 or something like this but in case they are not there which is what what is why it can need not be there what is the cause you are anyway doing technology course you are doing other design course what will be the cause in which two transistors may not be identical what could cause it anyone the reason why this mismatch occurs a variety of reasons the doping on different transistors in the what we call channel implants are not correct there is spacer problems there are many issues boron depletion is another issue and there is issue of different W bios actually during lithographies okay so these are called mismatches age effects and mismatches they will be there do what you how small they will be is what is important we will prefer them to be almost identical but never identical as close as possible but that happens that the device two devices normally m1 m2 being so close this difference will be very very small but ideally this is only a statement in real life the issues are different there may not be only one defam there will be n defams each will have different variations in real life variations may cause on chip variation chip to chip variation refer to refer variation so there are huge problems at the end of the day is called variability issues and one has to take care in design now variability issues okay I like threshold may vary plus minus 10% then what do we do our assumption is it is constant so everything is fine W bios is constant all that issues are temperature is constant all these issues are not true in real life so at least we should look at least some of those variations and see what will it influence and that is why designers should know a priority is that okay the issues are related to technology and they must be brought in in your thinking because at then device will be fabricated on silicon okay our circuit will define and silicon does not listen what you want to tell okay she it does what it wants and then you are left with thinking why did the other way okay I wanted this he is not doing so what should I do now that probably he will do what I wanted that some game you can play okay so here is the case which is of relevance in real life let us say M1 M2 do not have identical characteristics which is very true in fact okay so that then the Vx is not equal to V bar okay that is but for sure because then if they are different they will not have the same values even if signal is common mode if GM's are not same how can you have same drops across the RDS okay and therefore firstly even RDS are not same I mean if the delta already goes with that some plus some minus so there are issues and issues mismatches are very very difficult to handle then of course the symmetry thing should not be really used because they are not really symmetric essentially we can but I do not think we should use that then we just calculate the currents as simple I have one input common mode and let us say this voltage node is VP now if we say so IDS1 is GM1 VNC MCVP and IDS2 is GM2 VNC and minus VP then VP from this solution can get GM1 plus GM2 by RSS 1 plus GM1 plus GM2 into RSS and then Vx is something like this where this one yeah yeah sorry if that is so that is true I am sorry I made I think lower down many correct Nihon Iche likhdi I mean is okay fine thank you so if I find Vx and Vy it is minus GM1 VNCM minus VP into RD bank I have a common and then I solved this is minus GM1 RD1 plus GM1 GM2 RSS into VNCM similarly I can calculate Vy drop nothing else okay drop across RD okay so I can calculate Vx and I calculate Vy what is the gain we are now looking for that is what is called conversion of common mode into difference mode because we are going to get a signal difference gain which is Vx minus Vi with reference to what VNCM okay so gain which is of more relevance is not just the way I showed you earlier this essentially this Vx minus Vy divided by VNCM that is the gain which is many times is called AVCM dash have you written down then I can show you next slide okay fine so if I as I said I am interested in the difference gain for common mode signal which is Vx minus Vy divided by and then I subtract GM1 minus GM2 delta this this into VNCM and that and then I define the gain is AVCM dash DM is that clear the new definition is AVCM dash DM which is Vx minus Vy by PCM say if I divide this here I get GM then I define GM1 minus GM2 is delta GM normally how much ideally how much it will be delta GM will be 0 if you say GM1 are equal to GM2 or what it is and we also define a term GM which is GM1 plus GM2 sometimes they define half of it I have defined as it is so in some book if you say divide by 2 so 2 GM will turn up here in replacing this term okay so that too sometimes if you see do not think why I am a bullgani many define because I realize I figured it out in the book they are used to I think but I was solving and I have defined something I kept it so please remember this is my definition generally it is half they will put it average they will say but since I have not used it my value may not show those tools somewhere and then we define the term AV DM divided by AV CM dash is essentially what we call as common mode rejection ratio and if you now divide that it can be figured out it is 2 GM because GMRD will cancel from there so 2 GM upon 2 delta GM into 1 plus GM RSS so since we said we are one of the main feature of a diffam is what what did I say it should be able to reject common mode so if I want larger CMRRs typically what is CMRR in DBs for a opams which is used in the lab typically like 741 how much is good 741 has at best 80 DBs 80 DBs normally we will prefer a good opam is how much 120 DB so if you have to design a 120 DB opam you will figure it out it will create hell of a problem for other parameters particularly the phase models so there is an issue how much CMRR I should be allowed so that I should get the other performance also as good as I want that is the design issue is that clear CMRR is therefore kept flexible term they say minimum CMRR should be 80 DB okay so you are not saying 120 because otherwise you cannot design it so issues are always clear same way we will never say power supply power dissipation should be so much it is very difficult it should not be more than so much okay or the slew rate should be at least this much gain should be greater than so much okay these are the bars or the upper and lower bars we must decide because then only design is possible at any time you put rigid specs nothing is designed okay so one cannot design a chip with very very rigid you must say more than less than where the bounds you can give please give it because then the designer has something to play on okay so that has to be understood so if I want larger CMRR from this expression as good the two transistors better is CMRR okay delta GM jitna kam hoga jitna CMRR jadha hoga jitna jadha GM hoga that is transistor they have larger GM means what is larger GM means either it is driven by larger currents or they have large size transistors please take it this large size word should be taken with a pinch of salt why because large size means large generally lengths are very rarely changed so it is the widths which are changed if widths are changed what will change capacitance because capacitance are normally limited proportional to W all parasitics essentially you change the W by L you will be actually talking about increase in capacity and change the W to higher value yeah ideas will increase everything will go nice we GM will be higher but then the bandwidth will be affected is that clear and therefore one must not say increase W by L but one catch I may say I may why it has said also any time you are worried about device to be in saturation put larger W by L for given currents it will always enter saturation think of it what they say if I make particular current which is quail autumn then see to it your W by L are much larger comparatively then it will always remain in saturation the other possibility of improving RSS CMRR is to make this RSS very large which is what we will try because current source as good a current source I will give for bias that will be better and if you can do this obviously your CMRR will be larger so now you can see there are parameters which you are governing CMRR so if you change something somewhere to get other spec this also will get affected and therefore do not see CMRR not a spec it is a spec which is great extent variable greater than oh I cannot tolerate less than 80 dB fair enough but do not say it has to be 80 can be 85, 90 or whatever it is what typically 80 dB all op-amps general purpose op-amps at 80 dB special op-amps like LM 2 3 2 3 or 3 2 1 or 85, 76 which is another device they are CMRRs at 120 dB they are low noise amplifiers and they specifically try to improve CMRRs but their bandwidths are not very high so there is an issue that is what I keep saying there are games different applications require different op-amps or different amplifications and they are different specs so you have to choose if you are doing board design then you have to choose from the data sheets which one you should check in chip you do not have a data sheet we have to design so we actually solve it and figure out what is the another thing I keep saying when I design something and I convert to layout which is what one of the major output of any course of design then the first thing we will do is we will that layout which I had drawn for the poly for every region then I will extract the circuit back from the layout and then I will resimulate that and we will be surprised that whatever initially specs with which you have drawn the layout they do not match so you have to redraw or resimulate change something redraw it re-extract till they are close by assuming things are okay because this layout is for a given technology rules which come like you are working on 90 nano UMC 90 nanometer technology so they have their layout extraction tool will actually follow them so you are very close to foundry is that clear but even then there is no 100% guarantee that silicon will show you same performance but it will still be close to what you are looking for is that clear so at the end of the day which is some turnarounds will be required as many turnarounds is cheaper or costlier larger the turnarounds cost increases the one fab you go through now spend only lakhs of rupees typical cost for a 90 nanometer process for a 2 mm by 2 mm chip or per mm square you can say is around 8 lakhs these days for academic discounted price on a 612 inch wafers cost is 2 mm per mm square is 8 lakhs on 90 and 65 nanometer for 2.25.35 it is 2.5 lakhs so most of the designs which we do in the lab is only for the sake of money because otherwise the money is too high okay defam with now let us see defam designs or at least defam analysis once again and there are 3 defam shown here you can draw each of them instead of showing V in by 2 and minus V in by 2 I am showing you one together as V in that is the only difference from what I said earlier okay the most important part which I did not say these are all CMOS defam okay apne course cannot CMOS ena this layup we will not use any N channels now AP channels other than together is I mean so these are all CMOS defam which probably are the ones which we will design whenever gate is connected to the train then it is called diode connected okay the P channel the source is at the power supply side because you need negative supply VGS it has to be at higher voltage so positive high voltage so that VGS is minus gate is connected to drain the device acts like a actual diode what is the difference between this diode this is also a diode and a normal diode you know what is the difference the diode has IV characters which is exponential is that correct so in all technologies in CMOS there is no real diode made actually diode is this okay side change curve sometimes thicker oxide dialogue characteristics but diode is this is how diodes are made is it okay last but not the least so the first one is a diode connected load which I just have said this is standard N channel 2 devices which is forming a defam pair which is biased through a ISS source okay and this is my input the second one is these are current sources you can bias it properly some standard biasing system which will show later and this can remain as the constant current source it is called current source loads please remember these are P channel devices and we are all the time feeling as if only N channel devices can be defam pair you can have inverse you can have a P channel defam pair and you have N channel loads as well okay the third and the foremost of all these these are very specific ones and not often used in most of the opams okay the advantage of these two are essentially I did not draw it okay here also these are double ended outputs okay these are double ended outputs whereas the third one which is the most common defam used in operational amplifier at the first stage is a single ended output stage which is shown here the feature is very interesting here because here the two P channel gates are connected to one of the drain of this side at time if driver is you can do other side also then the output will be the other end there is nothing they are symmetric so it does not matter but normally shown this everywhere so I am also you can as well do here and then take output from there this is only question of mirror the only thing which I did not say very specific here this ISS there in most cases will come from either applying a bias such that this device always remain in current source mode or actually it will be mirrored the current will come from a current mirror so if the gate of this is connected to current mirror gate then same current which you are passing in that will pass in the this transistor and this will act like a current bias circuits so it is either putting a bias which sometimes good if you have a good reference bias voltage I mean like band gap reference or then you do it normally with current mirrors this is what the single ended defam essentially is most popular defam which is as I say most popular simply because all first input stages of opens are these but there as I said other there is a fully differential defam okay or fully differential opens then you do not need both outputs okay fully differential and at those time this cannot be used either of them will be used in that so inputs to outputs is that called fully differential so in those cases only you will require first to otherwise most general opens first stage is simple one single ended defam now before we solve the case for the third one which is most important quickly we will repeat for the diode we already solve this so diode connected load the load resistance is essentially the gm pad 1 upon gm parallel ROP gm is normally very large compared to 1 upon RO and therefore it is normally 1 by gmp and therefore the gain is gmn by gmp which is now you see the difference it is nu n by mu p into WL by n by WL by p so for a diode connected this the load for diode connected loads the gain of a defam is already is if mu n by mu p ratio is 2 you have already got little extra gain out of using P channels then what is the advantage if they are same they could have been same then this will have cancelled then the increase the ratio I will have to increase more size of n channel compared to P side to here already mu n by mu p ratio is giving additional boost so still n channel device will be larger than P channel is that okay the current source load the load is only ROP then AV is gm Rn RON parallel ROP the two ROs of the n channel and P channel at the output are parallel so they are parallel if they are equal they will not be equal because of the mobility but many times they may be equal also because you may adjust sizes therefore you may have gmn Rn parallel ROP so these are standard difference gains for two of this but what we are interested into the end of the day is third one which is what we are going to design therefore we should look into it little more carefully is that okay these are trivial standard this can already already done earlier these two we are just repeating the results there again only difference in earlier case and this is there here this n channel P channel device of mu n by mu p will also beta so mu n is one time mu n C ox the other is mu p C ox so mu n by mu p ratio will appear and that you must take care typically how much is the ratio of mu n by mu p in the actual semiconductors silicon I am not saying what type what is the typical value of mu n by mu p in a normal semiconductor bulk three okay it is almost 3 480 to 1400 something however in mass transistors this can never be attained because of the surface mobility is not as high as the bulk mobility so the best of ratios you may get 2.2 2.3 and therefore most of our designs are for 2 because you may not get 2.3 okay so we may say okay 2 so generally if you are not given any value assume mu n by mu p as 2 I may specify beta n dash and beta p dash so there is nothing you have to worry but in case I do not specify you can always use this as 2 because that is the most likely value the best of mu n you may get is 600 centimeter square per volt second and best of that you may get is 300 centimeter square per volt second for holes in most most technologies higher technology even it is worse so it is becoming very very difficult now to maintain even 2 okay but that is the game we play enough so that the infestates are very much in control so that the mobility is roughly 2 these are called surface mobility these are not bulk mobility very good normal diode I V characteristics as out there forward go to diode hi DS V DS was square law but if you adjust your sizes and it is they look closer to that so they though they are not square laws but they look similar and therefore it is called diode as they are not diode is that clear essentially this is their difference this is a square law term is that okay but this is good enough in most characteristics requirement the major reason is in either case the current here also is very small and here also is also diode blocking is still possible in the other case therefore one says it is like a diode okay okay let us look for the third one which is the one which is of great interest to us which is the first stage of open which is called current mirrored diff am current sink or current it can be called what is the difference in source and sink whenever current starts from power supply it is called sourced whenever the current goes to the ground it is called sink okay so definition wise I just thought I should tell you it is actually sink source current is sinking into the ground okay so in some books if you say sink I thought I must write that that they may also call it sink source still source of a current but call sink it is ground okay so it is normally derived out of a transistor M5 and normally this VGG either has to be controlled or a mirror can be brought mirror current can be brought to pass in this this now we will like to first try to find out before we do gains of this quickly look into it there are some voltages of interest this is VGS please look at it as a first you draw figure and then do not write this right when I see first draw the figure that is most important have you drawn the figure first then I will start talking and then you can write I repeatedly saying that capital and small and everything should not be unless stated otherwise by me please do not worry too much about it there is a voltage VGS 3 for M3 there is a voltage gate to source voltage VGS 4 for M4 both are P channel device the gate is connected to the drain of M1 or drain of M3 both are drains so that is our output 1 V out 1 which we are not very keen to know what we are interested in output at this end which is called the actual output of the VG1 and VG2 are the input signals then this is VGS1 this is VGS2 or to say VG1-VG2 is the different signal ID VG1 is therefore VID by 2 VG2 is minus VID as we did equivalently say then VGS1 is essentially this voltage minus VP VG-VG-VG now here is a catch this is a DC current flowing in this ISS and normally it is a good current source whose output resistance RO5 is very very large that is what the good current source is about so I am postulate now if it is a excellent current source the change in VP is 0 is that clear VP does not move or AC wise it is 0 delta VP 0 means AC so essentially VGS1 is VG1 and VGS2 is VG2 this is my statement I may prove now that VP has not moved anyway so that I did for earlier demo I am doing now for real circuit the consumption now I am saying please remember this is the statement I am making and based on this statement I am going to make this statement to you that I can assume VP to be grounded as far as AC is concerned is that clear if this is not large some current will flow that is the problem okay so we say right now RO5 is extremely large even if not very large is still doable but at least we assume okay is that okay is that statement clear here is an equivalent circuit of the system please say it very I have done it very intentionally a different way of drawing the circuit this may help you to appreciate what I am saying so look at the input side one is VID by 2 other is minus VID by 2 and this is that common point where we say the output is I mean this is grounded physical signal which is that point I am saying I am actually saying from the ground this to the ground okay if you see the M1 M2 transistors then it is GM VID by 2 into parallel RO1 is the equivalent circuit for this please remember this is your VP the other side is please see the sign now because of this VID sign GM 2 VID is shown down going from source to this this is AC signal please take it this is AC signal across which there is a RO2 is that okay so M1 M2 have an equivalent circuit this is common point VP this is GM 1 VID this is GM VID same way if we go ahead for 3 and 4 1 upon GM 3 RO3 now whichever die if it is diode this will dominate if not this will dominate GM 4 RO4 now there is something which I am right now not showing here another source it will bring it little later but right now as this as if see I see that is the equivalent I see I will show you why why I have not done then and now I will show now the idea is something like this if you see RO5 transistor this side is ground now we say the current in VO1 by RO1 or VO2 by RO2 are very small why we are there very small because ROs are very high so we believe that those currents are extremely small if that is so this current and this current does pass through RO5 to the ground is that okay this current and this current passes through RO5 is that okay now the direction if you see it is GM VID by 2 goes like this GM 2 VID by 2 comes out of it if you now say GM 1 are very close to GM 2 and that the RO5 is what is the current through RO5 GM 1 VID by 2 minus GM 2 VID by 2 and that is very close to 0 is that okay in which case we may say the potential here is equal to potential here so if the VC is ground VP is equally grounded is that clear so that delta VP does not move by lemma is what I have used but I now showed you through a circuit point of view that VP remains constant so no AC current that voltage for AC is same as VC okay so this idea that in circuit how people use that sometimes you know because they may not show you this they may suddenly put a ground there so you must know from where this theory has come that VP can be treated for AC as ground is that point clear because in a book if you see they may not show all this they may only show this and show ground then you must not feel why this is grounded this is how it is looks to be grounded okay this is what you say you know between the lines what they do not write and what I can tell you from where they derive this okay is that okay so will be it is current sources and which is what I am assuming GM 1 are very close to GM 2 then we say this there is no current in this a floating it may make me check our point with the ground but the upper the ground is yeah Joe potential need a way over a register low your potential is this may current need a drop name a potential your potential same on that clear that is why you say VP is as much as ground as much as is a very important one it is not really ground but as much as it is ground which okay the reason why I did it was because I figured out in the books they just draw circuits without telling you any great thing so I just thought so this is your input okay this is your GM 1 VID 1 this is GM 2 VID okay RO 1 parallel okay please just a minute you can see if this is grounded this is grounded I can connect them is that correct this is grounded this is grounded so I connect them okay so if I connect them now there is some catch word is going on again this equivalent circuit is not accurate I mean then I what I did I use this as a one common line ground then a circuit either liar is key I get the circuit you see ground this is what normally the figure in the class books will be this kind this has come from this so this is a technique which I showed you given as a kitchen finally castle okay now we see from here if it is GM 1 VID RO 1 parallel this of course it may you may keep GN 3 or not is up to you because the values will decide but in real life we can keep them whichever is not there we will go away now this fact is most important have you drawn this circuit then I will explain that is the issue which I am now telling so the output of the first stage M 1 M 3 can be figured out by a current source of GM VID I do shunted by RO 1 shunted by RO 3 parallel GM 3 is that okay okay have you drawn all of you okay so look at it this is the first stage M 1 M 3 stage I repeat now you should I put this figure okay so I have figured out I first solve this M 1 M 3 and got V out 1 but now look at this V out 1 where is it get connected to the gate here this voltage is same as this voltage for AC this is ground okay so this voltage is same as this voltage they are connected all three is that correct and now there is an issue start that is what you are saying which for what may I get it now you can see the output at this second stage which is M 2 M 4 stage one input is coming from this VID by 2-VID but the there is another input coming from here M 4 may be at input I have the crap for the AC because I see how to do my current okay so when I see output now I see I have two inputs one at M 4 and the other at M 1 M 2 so I must now actually superpose the two I must get the voltage due to the VGS 4 and also should get output due to VGS I mean VG 2 or VID by 2 so I need both sources to be now used in evaluating the V out that is the interesting part is that clear is that clear is that clear to you why this the turn which I am now showing there are two sources for this output one is if I input here if I give input here okay so there are two transistors are receiving input now okay so what is the method I use initially do not treat this treat with this next time treat this or output due to VGS 4 and output due to VG 2 or VID by 2 I will add them superpose them to get my V out this is the technique which all of us directly or indirectly use okay so I have shown you how from where this method has been chosen is that clear if I do not connect this this issue will never appear is that clear to you but as I connected to make it single ended the first time I realized that the output of the first stage is input to one of the transistors of the second stage is that clear and that must be now taken care in solving okay is that okay so if I do that which is what is relevant for in my opinion now you can see what Raj was saying I am hiding since V01 is VGS 4 is that okay V01 is VGS 4 so apart from the first M2 current output high both the GM2 VID by 2 source what is the resistance it is going to see RO 2 parallel R4 R1 upon M4 but the same resistance is also getting additional voltage because the output will still remain same resistance will remain same because resist M2 M4 are still same but there is additional current source sitting here which is because of M4 which is GM4 into VGS is that clear there is a additional current source which is GM4 VGS 4 and there is one normally GM2 VGS is already there now you are two currents the only interesting part there is ACY both are a upper learning the koshish karna ek and that is why their signals are current sources are shown opposite is that clear this is the crux of different outputs is that clear if I do not show this then I am making a great error okay this is the reason why you see a gains as shown in the books because but as I say most books do not show this kind of equivalence so I thought maybe this is a high time that I show you that from where they are getting those expressions is that point clear to you if there is a transistor M4 is also receiving AC input at M2 you are actually putting an AC input okay both contributes to the output of the second stage okay they must be super post the problem was that one is pushing the because of VGS is a P channel device the other is N channel device so the direction is opposite so they are as but one of them is minus sign so probably they may still add physically in numbers is that okay okay last quickly we will finish up maybe we will stop here we will show you next time the gains so is that equivalent circuit please now remember this is the real equivalent circuit of a single stage defam is that okay this is the equivalent circuit of single stage defam okay now calculation are very easy output is here substitute back here in that and calculate V out finally which is then V out by VGS VID by 2 will get us or VID will get us the difference scheme is that clear so next time.