 Giridhar Jain, Assistant Professor in Electronics and Telecommunication Engineering, Walchen Institute of Technology, Sholapur. Now today I am going to deliver a lecture on digital voltmeters using a dual slope A to D converter. Now learning outcomes of the session are at the end of the session students will be able to draw and describe block diagram of digital voltmeter using dual slope A to D converter. Contents are block diagram of digital voltmeter using dual slope A to D converter and timing diagram of voltage conversion. Now figure shows the block diagram of DVM using dual slope A to D converter. So starting from the input you can see analog input which is to be converted or measure using DVM that is analog V in and the reference voltage is minus V reference. Then switches S1 and S2 after switches there is a integrator inverting integrator using op-amp output of integrator is applied to a comparator and for the comparator you can see positive that is non-inverting terminal of the comparator is connected to the ground and the output of comparator. So it is given to the 180 ohm resistance and the Zener diode which will clip the output to 4.7 volt. Then there is a AND gate and one of the input to the AND gate is 1 megahertz square wave and the output of AND gate is given to BCD counter. So this DVM consists of integrator followed by comparator AND gate then 4 digit BCD counter followed by 4 BCD latches to hold the output of counter and then for display 4 number of BCD to 7 segment decoders and the 4 number of 7 segment display as shown in figure and to control all the actions there is a control circuit. So control circuit will have the inputs which is the output of comparator that is one input second is MSB of the counter and the output of the control circuit is going to control the switch S1, S2 and it will go to control reset and reset of the counter and latch enable of the BCD latches as shown in figure. Now what happens initially is switch S1 and S2 is open and initially S3 is closed for some time so that the capacitor is discharged to 0 voltage then S3 is open. Now to start the conversion cycle the S1 is closed. Now when S1 is closed the input let input be say positive voltage so input is applied through switch S1 to the input of integrator therefore output of integrator goes to negative ramp output of integrator is a negative going ramp. Now when the output is negative going ramp then output of comparator now as the output of comparator is negative because the voltage at positive terminal is 0 and voltage at negative terminal is here a negative going ramp therefore output of comparator is high. So that is clip to 4.7 volt by the Zener diode and therefore AND gate is enabled. Now output of AND gate will be the 1 MHz square wave and that will be applied as a clock to the BCD counter means BCD counter starts counting and the output of the integrator goes is negative going ramp. Now when the MSB of the counter is set which is sensed by the control circuit at that point what happens when the MSB of the counter is set then control circuit will sense that event and it will take the action so that it will activate the reset signal so that counter is reset and it will change it will open switch S1 and close switch S2 means it will stop integrating the input voltage and now the switch S2 is closed and the counter is reset. Now let minus V reference is say minus 2 volt so negative V reference is applied and that will be connected to input of integrator through switch S2 and therefore output of integrator is now the positive going ramp. So T1 is the period for which input is integrated and when MSB is set then integration of input is stopped and now switch S1 is open and S2 is closed and therefore integration of minus V reference will start so it is positive going ramp. Now this positive going ramp this will continue up to a 0 when the output of integrator become slightly more than 0 the output of the comparator is negative and that is low and therefore AND gate is disabled and counter will stop counting. Now if you look at the integrator so for the integrator you can see the there is a virtual ground at negative terminal so input current is I in and the current through capacitor is I f. Now by the considering ideal op-amp I in is equal to I f so if you can go through this so I in is equal to I f. Now I in can be written as V in minus V 2 and V 2 divided by R and I f can be written as V 2 minus V o divided by C. So here you can see V in minus V 2 divided by R and the current through capacitor I f can be written as C d by dt of V 2 minus V o. Simplifying now here due to virtual ground V 2 is 0 therefore substituting V 2 is equal to 0 we get V in my R equal to minus C d V o by dt and therefore simplifying we get d V o by dt equal to minus V in by R C means the slope of ramp during period T 1 is minus V in my R C as shown in figure and after T 1 the minus V reference is integrated therefore the slope will become plus V reference by R C. Now for the small input you can see the period T 1 and T 2 now after period T 2 the integrator output will become 0 and after at that moment if it becomes slightly positive output of comparator becomes negative right or low and the conversion cycle is completed. Now pause this video and think on the following question what is the timing for enabling reset and latch enable. Now if you look at this conversion this ramp during T 1 and T 2 you can see the conversion is complete at T 2 so at T 2 for the small input the count T 2 can be loaded and here you can enable the latch and after enabling latch after some time you can reset the counter. So, more details you can observe by this timing diagram so in the timing diagram so during T 1 input is integrated switch S 1 is close and S 2 is off and during period T 2 S 1 is off and S 2 is on means the positive that negative V reference is integrated. Now after T 1 plus T 2 you can see the integrator output will become 0 and conversion is complete. So, this figure shows the waveform for the integrator output then switch S 1 S 2 positions then the clock 1 megahertz and you can see at time T 1 plus T 2 conversion is complete means when the integrator output become 0 and latch is enabled. Now once latch is enabled the output of counter which is proportional to the input voltage so that is stored into the latch it is latch and after latch enable is activated after some time you reset the counter so that it is ready for the further cycle that is a next cycle. Now here you can see that the time period T 2 is proportional to the input voltage. So, for that you can see output voltage V o is minus V in upon R c into T 1 during period T 1 let this is equation number 1 then V o can be written as minus V reference by R c into T 2 let this is equation number 2 so during period T 2 and this 1 and 2 should be equal. So, equating equation 1 and 2 we get V in upon minus V in by R c T 1 equal to minus V reference by R c T 2 and simplifying we get T 2 is equal to V in upon V reference into T 1. Now in this equation 3 you can observe that the T 2 is the period and here V reference and the T 1 are constant therefore, T 2 is proportional to the V in if T 1 and V reference are constant means we can say that the T 2 is proportional to the input voltage and the count which is latch and displayed that is also proportional to the input voltage measure. So, these are references. So, thank you for watching the video.