 So, this takes care of the CMOS design style. By the way, I noticed that in many universities, a lot of time is being spent on NMOS, ED, enhancement and enhancement and so on. These design styles used to be important when we were learning VLSI design. But now NMOS technology is hardly used. So, therefore, I have a feeling that both at a curriculum level, if you have, if you are part of the curriculum committees and so on, the emphasis on pure N channels should be reduced and CMOS design should be taught much more. Almost exclusively, most designs these days are done in CMOS. So, in your paper setting, in your time that you spent, etc., if you spend more time on CMOS, then your students will be able to meet the requirements of the industry much better. Because once they are in the industry, they will practically never design pure N channel. Is this the only way to design logic? And the answer is no. There are other logic designs and we shall, in the next half hour, quickly go over other logic styles and see when are those logic styles important. First of all, since you have done a lot of NMOS, the idea is that this is the CMOS summary, right, that logic consumes no static power. That is the main important point. But suppose I do not care, can I make my design simpler by doing C2NMOS? All of you have taught NMOS, ED, inverters, etc., okay. So what happens? You have a depletion device which is always on. But in CMOS, there is no depletion device. So what am I going to do? So the answer is that take the PMOS and connect its gate to ground, it will be always on. So instead of depletion device, you use a PMOS whose gate is always connected to ground. Okay? So this is equivalent to your NMOS design, therefore it is called C2NMOS. So the question is why should I do it? If I have a CMOS technology with N-channel and P-channel transistors, both available, then why should I hobble myself like this and design things like this? Well, there are times when this is important. This is advantages. What are those times? Notice that the advantage of this is that each output drives only one transistor. Okay? In case of CMOS, every output goes to an N-channel transistor as well as to a P-channel transistor. That means the capacitive load is high on every output, okay? Here the capacitive load is low. Remember that the interconnect is also more complicated because the P-channel device are in a separate well, they are far away from the N-channel device. So the same signal has to go to this well as well as to that well. Therefore the loading capacitance is high because of that reason as well. Whereas here, it is short and sweet. From the drain of one N-channel, it goes to the gate of the next N-channel. And the P-channel could be remote, could be connected somewhere, right? So as a result, this design reduces capacitance and when it is that advantageous, when you have very fast circuitry, where most of the power is not static, but it is dynamic. So CB squared F, right? So therefore, C2NMOS could be important in those cases where you want to design some very small part which works all the time is very fast. Now I will not drag you through this but similar to the CMOS design, there are all these regimes for etc., etc. And there is the corresponding algebra which we will take as red right now, okay? This is a one semester course and we are finishing it in two hours. So we cannot do everything in the class here. But all this material is available to you. Sir, one doubt sir. In that NMOS, but there will be static power dissipation. There will be static power dissipation. So it depends on which power dominates and therefore that is attractive only if the noise never remains static. So if you have suppose some computation being done every clock cycle and some very very fast clock, then you may find that CMOS while it saves static power but it is never static. On the other hand it consumes a lot of dynamic power because of the large capacitance and in such cases this might be a better choice. There is actually one other application where CMOS won't do at all and that is the PLA design, Programmable Logical A design. I am not sure whether I have perhaps included it here but that is because of the configuration that CMOS cannot do it at all. One important point is that we have we noticed that the beta must be greater than this number. This is what is beta? Beta is the ratio of the N channel to the P channel transistor in this case. The CMOS never put this restriction. CMOS simply said that VDD should be greater than VTN plus VTP. That is all. Otherwise the solutions came out but here the solution won't come out real or nicely unless beta is greater than this. That means that this is ratioed logic. That is because the upper transistor is all the time dumping current. This guy is all the time dumping current unless the lower transistor is much bigger than the upper transistor it won't be able to pull it down to ground because after all this is a potential divider and the upper guy is always on. So when this is on it should be so much stronger than the upper one that it pulls the output voltage all the way down and that will be true only if the ratio is correct. So this kind of logic is called ratioed logic. It works like digital logic only if the ratio of the P channel and N channel is assured about some value. That comes out actually from that algebra. And similar to that you can now do rise time, fall time, speed etc etc. I am just going to skip all of this but this is done in painful detail here. So in classes of course you will be taking many classes and deriving all these equations. And the conversion to other logic is simpler. You follow the same rule for NMOS but there is only one PMOS transistor which is always grounded. So that you leave untouched. The other things are converted to this. And here is an example of that same expression. So this is A dot B plus C dot D plus E. So for every dot series A dot B for every plus parallel plus C dot D plus E. So you can implement fairly complicated logic in a single stage. Now let us look at complementary pass gate logic. You would have done it in the digital part where often there is this favorite question how can you use a multiplexer as a logic element. And that depends on this Shannon's theorem. What it says is that if you have a logical function which is a function of x1, x2 through xn of Boolean variables then it can be expressed as two simpler functions. This is the function when x1 is 1 therefore x1 dot and this is the function when x1 is 0. So it is like a multiplexer where xi is being used as a multiplexer. If xi is 1 it selects this function, if xi is 0 it selects this function. And now f1 and f2 can be further simplified by the same logic. So this is the multiplexer logic and this multiplexer logic finds a physical implementation in this logic called the complementary pass gate logic. So to implement a multiplexer you need both xi and xi bar. So therefore complementary this is the hallmark of complementary logic that you need both true and compliment signal and you provide both true and compliment signal as a result. So the only difference is that now there are two wires for every logical level. You must take that into account. Now this is the basic multiplexer structure. Look at this. What happens when xi is 1? When xi is 1 these switches are on and these are off right xi bar, these are n channel transistors. Now we need to put an inverter here otherwise there will be a vt drop across this n channel transistor and the output logic level will not be good. So you need to put a buffer to restore the logic. So that is what we do. This is f1 bar, it passes through and you get f here. So this is f1 bar, f2 bar, f1, f2 and pass it through inverters and you get f and f bar. Now why do we bother with this new structure? These are the beautiful property. What is that beautiful property? First of all look at the layout of this. Whatever be your logic the layout will look like this. So you can have a standard layout and like a stamp just go stamping it and each logic will have exactly the same shape and size. This is a great advantage in making compact circuits. The other part is look at the delay. It does not matter what logic you are implementing. You have one switch delay and one inverter delay, whatever be the logic. So it does not depend on the level of the signal and it does not depend on the kind of logic and XR has the same delay as a NAND. The other thing is that now the type of logic required is much less because the same logic will produce AND as well as NAND. So you do not want separately inverting and non-inverting logic. So the overall variety of logic is smaller. Even within that variety the delay is very predictable and the delays are automatically matched. That means the delay of this signal being 0, this signal being 1, it does not go through series path here, parallel path here etc etc, rise time is not equal to fault time no such problems. On the other hand for every signal 2 wires must run. So that is a disadvantage that you have and you may pay some power penalty. As it turns out it actually consumes generally consumes less power than CMOS and this is a preferred logic at low speeds. So that was too abstract. Let us look at some actual logic. So consider the XR and XNOR functions. Now all of you know what a pain it is to implement an XR. So you have that famous 4 NAND combination or 4 NOR combination that you must have taught in the digital logic. But here XOR is no different from any other logic. So let us look at XOR. Here there is an inverter. So the function here should be the XNOR. What is XNOR? AB plus A bar B bar. So I get A and A bar here. If A is 1 then I must pass B. If A is 1 you just put A equal to 1 here. What do you get? B because this term is 0. You put A equal to 1. So you get B. So you bring B here. Now if you put A equal to 0 that is when this switch will be selected because A bar will be 1. So put A equal to 0 what do you get? This term becomes 0 and you get B bar. Similarly you put B bar here. Similarly this is eventually XNOR. This is an inverter. Therefore this must be an XOR. So what expression do you want? AB bar plus A bar B. Put A equal to 1 what do you get? B bar. So A equal to 1 this is the switch and put B bar here. Put A equal to 0 what do you get? B. So this is the switch which will be on if A is 0 and put B here. So it is as simple as just evaluating those sub expressions and this circuit has not changed at all. What does change is what gets connected to what. The circuit has remained the same. So basically the difference between the previous logics and this one is like in the previous things each input becomes part of the gate of each transistor here but you are connected the two inputs to the same transistor one to the gate and one to the drain or something like that. Correct. But the important point here is that suppose this is the circuit. Now I want an AND let us say. So here is the AND AND. Look at the circuit. The circuitry has not changed whereas in CMOS if you go from AND to OR to XOR series parallel the circuit will be different but here the circuit is the same only the input connections are different. So you can implement any logic with the same basic circuit. Circuit is not going to change and that has great advantage. But you also made a statement sir that this is used only for low speed applications. Why can't you use it for high speed applications if you know modify the physical properties of that gate. It can actually be used for high speed also. In fact it is used for high speed also but then you consume more power because there are two interconnects per logic level. So the capacitance doubles. So your dynamic power will be high in this case. If you are very fast logic then both wires are continuously being charged and discharged. So you pay the price for that. So let us take the same combination and quickly go through AND AND logic. So this is A dot B therefore this must be NAND A dot B whole bar. Put A equal to 1 what do you get? You have to give me proof that you are all awake. Put A equal to 1 what do you get? B bar. A dot B whole bar. Put A equal to 1 you get B bar. So A equal to 1 put B bar here. Put A equal to 0 what do you get? You get 1 but we want to connect only signals here. We do not want to bring in the power supply. So if you connect 1 and A is 0 you can connect A bar. So you bring A bar here. Similarly this is NAND therefore this must be AND so this is A dot B. Put A equal to 1 what do you get? B. So you connect B here. Put A equal to 0 what do you get? 0 so but A equal to 0 0 that means put A here. So that way your layout becomes simple. Your power supply lines do not come into the inputs and notice that these two outputs just go so they can just concatenate. Similarly this is OR NOT. Notice that the circuit remains exactly the same. There is no difference in the circuit and therefore delays remain exactly the same otherwise so this is of particular importance to arithmetic circuits because XOR occurs for almost all some calculations and for multipliers and so on. So XOR occurs unfortunately often and XOR is a very complicated gate in the standard thing. A dot B bar plus B dot A bar cannot be minimized whereas here XOR is no more expensive than a NAND or a NOR. So you just put it through and you can make very compact arithmetic circuits here. So these are the plus points of this pass gate logic. Now there is one problem here which we still have to solve. I have sold you this logic. It has its attractive points but there is one point which is unattractive. What is that? Look at this particular circuit okay I have taken only half the circuit. Suppose this X is 1 okay that means just so that I am not talking in the air let us say this is 5 volts and this is also 5 volts and let us say all VTs are 1 volt okay. So if this is 5 volts gate is at 5 volts and this is a source because this is at 5 volts this is lower. So this is a source so this will start charging up and it can only reach 4 volts because as soon as it reaches 4 volts this transistor will turn off. So it cannot charge it beyond 4 volts as a result the voltage here is only 4 volts. In fact it is slightly lower than 4 volts because it will take infinite time to reach 4 volts. If this is below 4 volts then this PMOS cannot be turned off okay. So there will be some even though this looks like a CMOS inverter there will be some leakage current here okay and that will consume static power. So there is a trick for that. What you say is that alright the leakage current is in the static when it has already reached 4 volts. Can't I use some circuit which will help it okay. So what I do is that I take another PMOS here and feed it with the output okay. Now let us see what happens. This input was low first it is charging towards 4 volts right. Now once it passes half the VDD or roughly the output will drop low right. As the output drops low this other PMOS will turn off okay and as it turns on it will quickly charge it up at 4 volts this guy will go off but because the output is already low this will take it all the way to 5 volts like CMOS. Problem solved everybody agrees what is happening if the input is 5 volts. This would have reached only 4 volts that would have left this PMOS partially on right but as the input reaches 4 volts the output would have gone down by that time. So this low value turns this PMOS on which then takes it above 4 volts turning this PMOS off so that there is no leakage current okay. I want every neck nodding a lot okay have you solved the problem we have not solved the problem. We have solved one problem and we have created another problem okay what is that other problem. Suppose this guy is already at 1 okay suppose this input is already at 1 then this output is 0 that means this transistor is on now how do I take it to 0. If I want to take it to 0 that means this guy should be 0 right now how does this circuit look this transistor is on and this transistor is trying to take it to 0 this is at ground so does it not look like CDO and MOS this transistor is on and this transistor is grounded right so it is like a CDO mass inverter therefore it will work only if it is ratio okay otherwise this guy would not be able to take it down to 0 at all because this guy will happily source current. So if this is turned on and if it gives you only a little bit of current then that won't be enough to pull it down to 0 once it pulls it down to 0 then everything is fine because once it pulls it down to 0 then the output goes high and then the PMOS turns off now no more problem but this guy should be ratioed to be fat enough like a CDO and MOS that is why we studied CDO and MOS before. So anyways sir you are going for a ratioed transistor configuration no that is the case we are not going for ratioed in this otherwise no I mean not to solve this problem you are going for a ratio transistor correct so rather than going for that ratio transistor what if the you know the external this output CMOS circuit if you you know change the characteristics of the transistor so that you can't change the VT you can't change the VT that is not in the designer's hand that is in the hand of the technologist and if you don't have a problem at 1 then you will have a problem at 0 okay suppose you use a very high VT P channel transistor then it will be a very slow circuit it won't charge up properly okay so the reason why this problem came was that it is actually a latch right this is an inverter and this is driving another half inverter right so it is a self perpetuating circuit and therefore it is not easy to budge once it has reached 1 or 0 you must fight to pull it down okay so that is what we do so therefore this transistor must be much wider than this transistor these two transistors must be much wider than this and then it is okay then it doesn't consume any additional power okay so this is still a pretty good circuit to use okay so this is what we are saying this need for ratioing look at this circuit it looks like this right so this is a pseudo NMOS inverter this is the pass transistor which becomes the lower transistor and this is the pull-up transistor so you must make this pull-up transistor weak so that this guy can pull it down because its job is only to keep it at 1 it is only a keeper transistor so normally this is a long channel transistor okay now that was one way but suppose I want to improve the pseudo NMOS okay so let us try to find what is the problem with pseudo NMOS power consumption when does power get consumed when is it that power is consumed when the input is one so the lower transistor is also on and the upper transistor is one so I scratch my head and say is in there some way that I can look at the output and turn the PMOS off when the lower switch is on okay but then you will reach CMOS back okay so the point is I will not look at the input I will look at the output right so what am I suggesting find me a way so that I can turn the PMOS off when it is being uncooperative and dumping power when I am trying to sink power right so give me that logic which will do this okay so let us look at this example what do I have here and nor right A and B in parallel A plus B whole bar right so I have a nor here so when can I drive this okay static power is consumed when the output is low right then the lower transistor is on output is low so when should I turn the upper transistor off when for nor right therefore complementary of nor that means when A or B is true then we would like to turn the PMOS off right because it is a nor so when A or B is true then the output will be low right so either A or B is true then I must turn this PMOS off right so that is just a NAND circuit if I this is the standard CMOS right so I can make a NAND circuit correct if either A is off or B is off then this output will go high and I will give this output to that right normally I do not have unfortunately non-inverting gates right when is output low this is nor when is the output low nor either is one right then the output is low so therefore when do we want to turn the thing off when either is low right so we want to when either A or B is true right then I want to turn this off okay sorry nor is low when or is true right nor is low when or is true so I want A or B but A or B cannot be generated correct because you have only inverting gates so I can say A or B is nothing but NAND of A bar and B bar correct so that is what I am doing that alright I will create take A bar and B bar take their NAND and drive the PMOS with this you got the idea what I am saying is that our problem is that when the output is supposed to be low then this PMOS is unnecessarily wasting power by leaving the tap open when it should be closed so can I not turn the tap off so the answer is okay what logic so that it is turned off only when required so the answer is that then you need the NAND of A bar and B bar okay unfortunately then I have not solved the problem because if I need this then this guy will consume the same amount of power that I will prevent here okay so it is very easy to give up at this time that is this idea will not work but fortunately I kick myself and say look what will prevent this current then I do not give up easily okay so when is this guy unnecessarily taking power when both these transistors are on that means both of them are 0 but that is this output right so I can make this circuit and this circuit both of them and drive this PMOS by this and this PMOS by this and now I have solved the problem okay you got the construct I will go quickly over this take this case when is the output low this is nor so either A or B is 1 then the output is low in that condition these transistors are trying to pull it low and this guy is unnecessarily dumping current so you want to turn it off right that condition is when A or B right because this is an or it will be low when or is true so I want the or but or I cannot generate without inversion so I take the NAND of A bar B bar okay so this is the NAND of A bar B bar and I drive the PMOS using that now the problem came that this PMOS will be unnecessarily dumping power so when is this dumping power when both A and B are 0 correct only when then both these transistors will be on right when both A and B are 0 then this output will be low that is when I am wasting power but when both A and B are low then this output is high nor so rather than giving this to ground I can give this output here and rather than taking this PMOS to ground I can give this output there okay now I have solved the problem neither gate consumes power let us assume I have you know only 2 inputs A and B I still need to generate the A bar and B bar is not it no so this is the complementary logic this is also a complementary logic okay in fact that is what I have done here so this is the this is called cascade voltage switch logic and this also needs both A and A bar okay and it also provides A and A bar because this output and this output are complementary okay so it is just like the complementary switch logic except that it it is continuously driven and consumes no power okay so this is a this is called the cascade voltage switch logic it has similarities to both pseudo NMOS and this like CPL this logic requires both true and complement signals it also provides both true and complement signals this is called dual rail logic okay dual rail logic by the way has become important these days when the power supply voltage has been brought down and signal to noise ratio is important so therefore since it is a differential mode it works better like pseudo NMOS the inputs present a single transistor load to the output right you are not taking the output to both an NMOS and PMOS and the circuit is self-latching okay it is in fact a latch so the circuit is self-latching so that is the advantage of this okay we will stop here