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Published on Oct 20, 2015
An Altruistic Processor (AAP) is a free and open source processor ISA, intended as reference architecture to improve software tool chain support for small, deeply embedded Harvard architectures. These are still in very widespread use (for example the Atmel AVR architecture), but compiler tool chains often suffer from assuming all targets are 32- or 64-bit Von Neumann RISC architectures with many registers (such as ARM).
AAP is a 16-bit Harvard architecture, with a 24-bit word addressed code space. It can be configured with as few as four 16-bit registers and has an extensible instruction set offering 16-bit, 32-bit and longer instructions. It thus provides a robust test of the generality of modern compiler tool chains.
Embecosm has implemented a LLVM tool chain and instruction set simulator for AAP, and is in the process of creating FPGA implementations in Verilog for the DE0-Nano.
In this talk, we will explain in detail the feature and philosophy of AAP as well as some software features we aim to improve through this project. We will present the implementation of both the ISS and the FPGA designs, one of which is a simple student implementation, and the other a superscalar pipelined implementation.