 Before we finish start with the last chapter which is back end, let me complete what we were discussing last time about etching in VLSI and we discussed the, we discussed last time about the wet etching and today we will look into dry etching quickly and then go to back end. One of the problem which I said last time that if you are doing a wet etching, most wet etchings are isotropic in their nature and when they etch, they not only etch vertically down but also on the lateral side and that gives you whatever is your mass pattern, the etched area is more than what the mass actually we are asking. Now the additional both side area which is etched has been given a name B and it is called bias and if you look at this, this we have done last time so I am just trying to be quickly on what we did. We did say that if this is larger, much bees are much larger so that the mass distance or width is much, the total film which is etched is much larger than the mass width then this is essentially a bad area. I may do little better etching in which less amount of lateral etching is done. So I will have a better compare to this however ideally I want anisotropic etch in which whatever is the mass width same is the etched area. Now we define an anisotropic term as AF which is 1 minus etch rate in lateral direction upon etch rate in vertical direction and if you see if etch rate of lateral is 0 that means nothing goes on the left side or right side then AF is 1. So the ideal etching, ideal profile if you want then AF should be 1 but if all lateral is positive and sufficiently close to vertical it can be 0.1 to 0.1 is the value of AF can vary. Smaller the AF first is the dimension you are getting and larger the AF better dimensions are what exactly mass wants we are transferring. Now this proportional if you need etch rate is into time is equal to the distance B on the lateral side and on the D which is the depth of the film which is all vertical into T. Similarly what I am saying that AF is 1 minus B by D okay so if this is the film thickness this is the bias and AF decides how much is the value if you are getting, B is the film thickness vertically down, B is the bias lateral. So B by D is essentially 1 minus B by D is the anisotropic coefficient and we are expecting that to be as close to 1 as possible. There is little maths I did of course this is given in plumber so you may even see later. Here is something what the pattern looks like this SM is the mass size you want to etch below that okay this is another mass area and in between is the distance X which is going to be etched okay. In the mass ages the distance is X which is where the etching is going to be done okay. So we now define some terms if this is my H profiles on both side of X I define the term SF as the film width which is taken from age of this mass to the age of the other mass it is called pitch of that this is the total width please look at it from this point to this point is to SF okay SF is the film thickness shown here SF is whatever is the this much part. So from here to here it is to SF this is your SM this is your B this is your B. So if I do little maths on these one can say to SF minus SM is the H to H mass distance X which is what we are etching actually X is what we are etching we also see SM is SF plus 2B BB so SM plus 2B please remember SM minus 2B is the SF what is SF is the film width which you actually H H to H so SM is SF plus 2B we do little calculation again as we did for AF we will come back to this later AF is equal to 1 minus B by X film thickness but here it is I said it is XF so B upon XF 1 minus of that is AF so B by XF is 1 minus AF so B is XF into 1 minus AF this simple maths I will come back to it SF is the distance shown here okay so you calculate that will be 2 basis okay. So X is equal to then I if I derive B is equal to XF 1 minus AF I substitute back in this equation SF plus 2B so I write SM is equal to SF plus XF 1 minus AF into 2 this equation has been now reduced to this or rather expanded to this and then from here I can get a value of X which is 2 SF minus SM is X 2 SF minus SM SM is this expression so if I write this I get the expression of XF X is equal to SF minus 2 XF 1 minus AF what is that we are trying to say from this what is the ideal etching we are looking for SF should be same as X SF should be same as X so if AF is equal to 1 X is exactly what H to H you want same etching it will go if it is not so then whatever you wanted actually it will be different from it will be larger than X and something additional window will be opening okay. Now this film thickness which so one can see from here if I write this SF is X plus 2 XF this formula I can make SF is equal to X in what conditions one is AF equal to 1 what is other possibility if the XF is 0 or smaller or thinner smaller the XF but that is obvious if the film thickness is very low the lateral etching will not have enough time to really go deeper so essentially we are saying if the film is still then it is not that great to get X equal to SF but the film is thicker then the lateral etching may happen and then X will not be same as SF so possibilities that X is equal to SF is very unlikely unless I make AF equal to 1 which in most cases will be very very difficult but we will try I will get AF is up to 0.8 to 0.9 when can get but never we can get one some lateral etching will happen okay why it can happen even if something is going down at the edges it will hit something called at the edge there is a field they say so ions will be pushed even inside a bit of them so there will be additional be always will be there which will not be 0 so AF can never become so the figure which we draw last time this is only ideal figure that AF is equal to 1 which is very unlikely to attain now why we are worried about because the people who design the mask they will design with the S they have two parameter SM and X H2H what is the distance between the mask and the mask size itself they are fixed it but now you are going to etch it and you say okay the actual film thickness which you etched actually giving larger than what X wanted that means you are in there because there is a next device may come closer to it it may happen both device may merge in some cases because etching may overtake the other side also okay so such a situation we want to avoid so what you are telling the designer okay at least away this much this is called design rule okay we are actually telling them a do not we may never get one so go at least this distance but at least larger the distance I ask them to go what does that mean the area of the chip will start increasing for the same function so designer is whole effort is to see making it compact as much transistors and interconnect I can push per unit area that is my aim and now you are going to tell oh I have a problem so the technology must try to achieve as good AF as is possible and one possible mechanism is done is using what is called as reactive ion etching so that is our ultimate aim I repeat X be equal to SF is what we are looking for okay film whatever width etched is same should be the H2H mask which is window for us so what is the reactor and HR a reactor and HR this of course is this formulation is given in books so there is no great thing I am talking about can you see this figure slightly different from the plasma depression system I made yes in this case the papers are connected to RF source and the top plate is essentially grounded in other cases what was there the source was here and whatever is the target was kept here okay is that less of a first of now target and the upper is grounded plate okay now one can see from here the way it happens if I apply RF plasma RF across an order in cathode the gas may be discharged because of the field is large enough however if you see ions and electrons electrons are more mobile compared to ions I answer heavier mass their velocities will be smaller electrons are lighter they will move faster so it may happen that electrons may first hit the cathode or the plates substrates earlier than ions can come and they may actually charge the substrate by negative charge is that correct that is why that cathode potential higher was shown because cathode may become much more negatively charged is that clear to you but since some electrons are left this from the plasma but there is still not all electrons are left there so this is still a plasma but now it becomes little more positive because negative electrons are left therefore if you see other day figure there is a plasma potential positive shown to you is that clear now it is clear because faster electrons move out some of them by the time they absorb and second electron start the plasma be gets into by the time the RF frequency allows you to go opposite polarity so this charge big plasma getting positive charge with reference to cathode is very dominant effect which allows now whatever is the plasma ions they will be accelerated by the field across this and will hit the substrate is that correct will hit the substrate the resist normally stops many of these ions like I am I am implantation we see I resist actually can h can stop most of the ions in this case also if you are resist there during itching ions cannot remove resist but whatever is the window developed ions can get inside is that clear and they will hit whatever film there may be SI2 nitride or metal or any film which is there it will start attacking it now there are two possibilities exist in this if the gas which I use is not just argon or some kind of a neutral gas okay if let us say I use a gas which is free on okay CF4 or whatever equal to and it may release fluorine ions but for you at least for silicon dioxide silicon nitride and in some metals as well fluid attacks very heavily what is this reaction will be chemical reactions fluorine is actually chemically reacting the film down but at the same time the fluorine ions are moving in which direction vertically downward because of what because of the electric field sets in there okay so ions are accelerated but they are active they are charged and also they are reactive to the film itself so this is what kind of acting we are doing chemical as well as ionic is that correct what the two kind of itching I did chemical itching because fluorine is attacking as well as the bombardment is done which is causing energy to hit the target and remove that from the like a sputtering so we are two processes going on in the case of reacting and itching the reaction is taking place from the chemicals and bombardment is taking because of ion being energetic vertically going down is that correct if I only use argon then what will be called sputter edge because then there is no reaction between argon and this so that is the difference between sputter edge and RIE the only difference as I say the gas used is reactive kind if you look at the without going into two detail of chemistry look for yourself a free on gas when it picks up an electron it becomes CF 3 plus fluorine plus electron then CF 3 plus electron is this CF 3 plus Fe minus CF 4 this is called three step process called dissociation ionization recombination and because of this fluorine ions actually travel down react with the film below and also since they are vertically down they also hit ion energy is given so they also do sputtering so there are two mechanism going on in itching what is the first fluent reaction and second bombardment of fluorine ions okay these two mechanism lead to additional H rate please look at it there are two H rates now going on one essentially because of the reaction the other because of ionic bombardment is that clear to you so normal RIE has two kinds of itching mechanisms which we must model in case we want to find the actual H rate however many times I am not very keen to have bombardment I am not really looking for anisotropy where do you think I do not need anisotropy itching during itching after I do lithography I developed the pattern then I did RIE itching okay but what is now left after itching the resist everywhere but that I am not itching selectively I want to remove itching as photoresist everywhere is that correct I am trying to remove photoresist everywhere this is called ashing okay this is called ashing so I want to remove the photoresist okay for doing this I do not really need ions for that I need I mean I do not need directional ions I only need fluorine to be available or something else to be available which can H photoresist so oxygen plasma is good enough without any direction it can remove the resist this is called ashing and here is an you have written down these reactions for these are also given I do not know about in plumber but in every itching book you can see the same reactions which gas is now banned in the prion is banned gas now okay so which gas is used in air conditioning which gas is used even prion is now getting banned so now the gas probably is going to use is S2F6 which is also used in some power electronics which is what are those called contactors okay so their vacuum arc system if you go and look at in power system we are using now SF6 discharge okay okay this is just additional information now no one is using prion but I think many VLSI companies are still using prion and not telling probably okay this equations are clear is that two mechanisms are clear is that two mechanism clear in RIE one bombardment other chemical reaction so this please the sentence you may it is not non-reactive it is a reactive species of fluorine is used can be used no is not but need not be foreign any other species now this is a isotropic etching why it is called isotropic because it is not directional or it can reach any direction it does not I want to remove every place anyway and it is used in ashing of resist using oxygen plasma so here is a reactor which is called a very famous reactor actually that is how we started with it is called barrel reactor this is the end view and this is the side view of the reactor you can see from here there is a boat on which wafers are kept okay then between these two plates we apply RF this is you know one plate this is your other plate in our cathode this is the RF applied I enter the gas the most important different before you do I figure you see this there is a small some wired mesh I kept there is that clear this this is a wired mesh okay which is essentially grounded not very shown correctly this shield is it is called shield so a shield is all around the wafers that means shield is all around the wafer this is a shield so wafer sit inside the shield and shield is grounded so when I get a discharge ions will be created which are positive plus charge ions however this when they pass through shield they will lose their charge to the shield so what is left there is only say oxygen plasma is used so only oxygen atoms which are not necessarily charged some of course some will still pass through but few of them most of them will be only oxygen and this is oh why oh because the reaction I am using in a plasma I am not getting O2 so what is the difference between O2 and O nascent oxygen is highly reactive okay because does not get a bond so it starts reacting that oxygen then reacts with any photo resist carbon material and will convert into carbon dioxide okay which is exhausted out and the whole wafer is cleaned out okay so this itchers are only used for photo resist ashing or some film where you want to remove all the films across okay so this is another etching which is used this is dry etching the other is also dry etching but what is the difference there it is it is reactive as well in this case it is only reactive but it is not bombardment is that correct reactive ion here only reactive species is that correct that is the only difference between the two H systems the first one we said it has two possibilities one is plasma ion bombardment other is etching so I want to create a model based on this mechanism for other there are two possible mechanism etching one as I said related to chemical etching the other is ion bombardment is that okay figure is drawn this this figure is also so very popular also you can go to applied materials lab they have one barrel etcher kept corner so there are two possible mechanism are two possible models are created for displaying describing the etching in the plasma systems okay which one oh this is RF coil also not this there is a call diffuser sorry this may cause a little ahead but below there is a diffuser that means there is a circular plate and holes in this is called diffuser why because gas if it comes from one end it will be heavily pushing on the one end only so it actually allows you to gas go through number of holes so that everywhere plasma pressure is constant is that clear if I push gas from all sides everywhere like plasma pressure is uniform so that is why it is but just above this is the shield is the RF coil just above that because you know otherwise the gas which is coming here this plasma will be less ions than this plasma okay so I want uniform plasma so I want to push gas everywhere is that clear the two models which allows you to model the etching is linear etch model and saturation adsorption model for our is called awi the first model both are for awi I think I made a mistake but linear etch model says it assumes something yes we have said two mechanism chemical and ionic however our assumption is during the etching they independently react they do not interact with either one is happening other is also happening and they are like a super positions okay so we say chemical and ionic components in plasma etching independently act and superimpose in the result then the H rate can be given as one due to the chemical reaction and one due to the ionic reaction or ionic bombardment so we figure out this model is given and can be derived also but I just wrote down there is a term called SC KF FC by N plus Ki FY by N where F stand for flux in all cases okay so FC is the available gas flux what is flux is number of atoms per unit area per unit time which is decided by what the pressure of the gas inside flux is decided by the pressure of the gas inside okay so I know FC how much gas pressure I use I know fluxes of this KF is essentially is called rate reaction constant due to chemistry what there is the reaction rate between the species as well as to the substrate which you are etching SC is called sticking coefficient okay we will discuss this little later and N is the number of atoms or number density per CC of the film so whichever film you are there what like in silicon what is the N number 510 to power 22 per CC for different materials this number will be different in looking at this side for ionic Ki is the reaction rate due to ion flux rate constant and FY is the ionic flux at each point on the surface now why this word SC has been introduced in the first case because the chemical reaction can only take place if the incoming atom actually stays on the surface you know it has to react so it must stay there okay because it will stay and it start moving and then can make a unit also okay so as long as it sticks there only then it can edge so the coefficient we describe this sticking possibility which overcomes the surface energy is called sticking coefficient okay for different materials and different gases SCs are different typically SC all atom getting attached may SC is 1 none is getting attached may SC is 0 so SC remember typically between 0 and 1 can be as high as 0.5 in most cases never one not all atom stick partly they move and emit also okay so SC is not more than 0.5 but certainly not very small number either okay so if I know now FCA days and I know KFKI for the film I am etching for the flux I am using then I know my H-rate I know my H-rate due to what are I reactive as well as bombardment total H-rate is this if I multiply it by time then what I will get is film thickness okay so if given a film thickness I want to etch in certain time I know how much should be H-rate and depending on the H-rate I can find what fluxes I should use so our pressures I should keep so that this film can be etched in this much time is that clear this is how bad calculations are performed first you are asked this is this film it should be F should be one close to one this I want this I want so you have to back calculate and come and find how much should be the gas pressure okay that is how we adjust the gas what is the other method keep on changing the wall maybe take 100 readings someday to hit correct okay so please remember vertical etching is in what which direction vertical etching is because of which mechanism with chemical as well as ionic but lateral will be because of what only chemical ions cannot of course few ions dose scatter but generally most of it will be chemical etching in this model we say vertical etching is due to only chemical and ionic processes however etching is lateral direction one can say that only chemical reaction occurs as ions travelled mostly in vertical directions and in that case to get the lateral etching what should I do H-rate put F i equal to 0 no flux due to ions on the lateral side so I can get is that clear how to get lateral H-rate just make F i equal to 0 this was one model suggested which were reasonably well in many cases but it was our assumption was both processes are independent itself is not correct okay firstly because when the ions come our assumption is mean free path is sufficient they do not scatter but it does not happen they hit the walls and they actually will be electron which actually takes the energy from the ions so their direction changes so the at the end one cannot say guarantee me that everyone is coming only down some ionic concentration may go on the lateral size as well because of both acting together and affecting each other okay this is our first assumption we said but in reality it may not happen if that happens that both are acting together one can derive little similar fashion H-rate is 1 upon N 1 upon K i 5 plus 1 upon SCFC and this this model has fitted well in some gases particularly fluorine based but did not fit in the other gases etchings so one does not know that this model is correct this model is correct whichever fitted to your data we may say this model in our case is correct okay so it is a fitting data model which we did enough etchings and we figured out typically which model normally reacts okay but this has more chances of fitting why because it assuming both together okay reaction of each other on both sides so there is a positive but modeling a scattered ions is very not very easy scattering scattering ions so this becomes only a first order equivalence and therefore not very accurate but otherwise this at least takes care of interactions okay so this finishes the possibilities of etching any film what was the etching we did first we did weight etching and then we say dry etching so why do you want to prefer dry etching selective etching and anisotropic etching why selective because one finds that different gases weight etchings can lift many things what happens if there is a film under the window the solution goes in and from the corner it may go in okay and then lift the film upper field which is stopping actually so the worries are in weight etching is solutions are what kind of socialistic in their thinking they do not think that this I have to go I have not to go everywhere whereas these are more capitalistic people they go vertically or wherever they want and therefore they are much more accurate okay and much more not much more less clumsy or films than anything however what is the problem with ion etchings ions are sufficient energy so they are hitting what during etching the lower surface will be damaged surface so you have to recover that damage so you have to anneal that means one thermal budget you are increased is that clear so it is not at free cost firstly I have to take it away clean it redo it this and again you have to put extra thermal budget for actually getting this better film etching is that okay so nothing at zero cost okay so this finishes each the last part of this course which should have taken more efforts than what I am doing today as I said the back end engineers are the ones who make the chip success system success and therefore should be really looked into much deeper but since they overlap with the designers so one feels whether designer should teach this part or a technology part so I am only going to talk about that part in this technology effort is required though designers are the ones who decide what I should do okay so what is back end essentially back end means the first one or two layers of metal which are from the devices or to first interconnect as we call may be part of the front end process okay anything above this as number of layers of interconnect layers you create these are called back end there back end technologies why because they decide the interconnect for the chip typically how much is the length of the interconnect on a good Intel chip I said you 5 kilometers on 1.7 centimeter size chip okay so one can think the one which is going to decide everything for you I am finishing in 10-20 minutes okay there actually it should demand that at least 8-6 hours I should spend only on back ends because these are the ones which will make chip fail everything goes well till front end and chip fails and the back end okay so issues which are very worrying are back end issues but as I say I am not going to spend time though I wish I could so back end technology in IC fabrication refers to metal layers above first metal layer which leads to interconnects and as I said these days 6 or 7 layers of interconnects are even 9 have been tried now for a more complex circuit so these are essentially what so what are the problems in creating number of interconnecting metal layers I have to talk about contacts okay I must talk about vias through which this something goes down okay and of course then between the 2 metal layers I need a dielectric which separate this into metal layers interconnect lines so when I say I am looking for back end I am looking for contacts I am looking for vias and I am looking for inter metallic dielectrics of course root is wrong so how do you place devices or transistors and how do you interconnect is another game typically if you are a circuit man they will say they there should be something called local something called global interconnect that local interconnects are close to the device source drains these are called local interconnects anything away outside that is called global interconnect now we keep saying some should be synchronous to the clock some should be non synchronous to be clock okay so these are issues with circuit people are worried about because to maintain certain speed of particular processor or any circuit these are called globally asynchronous and locally synchronous is what is one tries in most cases gals is the technology which used globally asynchronous please remember in circuits asynchronous does not mean clock 0 it is not synchronous with the system clock okay so interconnects run at different frequencies and actual device runs first interconnect runs with some other frequency which is synchronous to the actual system clock so okay so please remember where do you keep your devices and how do you interconnect on so many layers is another software possible is called place and root but with many layers of metal it becomes very very difficult for even place and root to get smallest amount of delay which is what we are really looking for there can be multiple choices so here is why we start interacting with designers now an interconnect which is a metal line on a dielectric is like an RLC circuit typically we always believe it is RC circuit for a great amount of research we did for many years that was sufficient that is typically around few gigahertz a metal line on a dielectric can be thought as R and C however how what is I am saying this is only RC transmission line so most of the time we calculated using simple Elmore formula or others or actually solving the transmission line the delay of this line and we say that is the delay we are worried about okay. However now the metal itself is becoming thinner because of scaling and the voltage I mean the frequencies are increasing so a simple wire is not a resistor alone okay it may actually have now inductor along with the resistor okay so a circuit trans of a transmission line is now more like a RLC there is also R across C now because of the capacitors are not ideal capacitors so the kind of lossy transmission line network solving is what is now needed if I want to find a delay in a interconnect now this delay has a problem if you look at a very simple RC model larger the length of interconnect I run larger is the R C may be area is also C but R is also increasing so if I take a signal from one end to other in a longer line the RC delay will be larger and if this one upon RC is the same as your system clock or close to that it will actually one may actually become zero by that actually clock age okay equivalently saying because you are getting one phase out because you are delay off one cycle this essentially means your whole data transfer will be actually are you okay so we must see to it that this RC delay or RLC delay should be much smaller than the actual system clock I am running okay that is why that asynchronous can we do not want to run at all the highest frequencies that is why we were globally we want to go asynchronous so this idea that RC should be reduced essentially if you look at the time constant associated with the delay towel larger the area larger is the towel smallest the feature size if this feature size is small it is film size feature size square inversely it goes to delay so if you are working on 11 nanometers actually the RC delays are much longer because everything is thinning down okay so actually my delay become worsened if I go from 45 to 30 32 to 22 to 16 11 the delay is even worse so I have to do additional features to see that delay is avoided it also depends upon inter metallic distance and the dialect if you keep so kiosks and it also depends on the metal resistivity so should I use aluminum at all now okay so I may use for which are the better resistors smaller resistivity so copper for example so these are the area when I look for high performance circuit I must see to it that I conform to a circuit performance why I am worried about because device people always believe that they are made so drain they are made channel lengths so what everything what you wanted I have given you okay that is what the front end people feel but the problem starts afterwards the circuit does not work each start blaming your this was your problem this one but at then the money who person who put the money he lost it so he is more worried so one issue which you must not forget that the back end design is very very crucial so how do I put interconnect I suggest technology which metals I should need what is the delay maximum I expect from you okay all these issues of course I if you do not need I will put buffers after every small length of interconnect I will put a buffer which will reduce my delay okay however buffer means I consume power I put extra area area and everywhere I only buffers okay so that is not the of course circuit person will say I will get you out okay but that is not the best solution yeah large size and it should be it is called non-inverting inverter in the sense epsilon by this C is proportional to K okay but we are not going for gate that is what I am trying to say you all this time I said you now do not go around and see the we are outside device now okay we are only interconnects okay the disc dilated between two metal lines need not be high K if that happens it is the worst thing to happen oxide does not mean silicon dioxide insulator in general for all these years even now the first layer still can be an aluminium as a contact and then as an interconnect what is the difference between contact and interconnect contact is with the source drain okay so it can be a contact material but the line running in on the aluminium so it but earlier we used to run aluminium as a con I have done as a interconnect as well as for the contact why aluminium was so preferred material there are many reasons why we started with aluminium first of course if you only look for conductivity and aluminium has delayed 5 to 10 to power minus 5 ohm per ohm centimetre is the moist per centimetre is the conductor so very low okay so what is wrong with aluminium fantastic aluminium all good features okay which one wanted but it is still not the best conductor copper is still better conductivity than gold and silver are also equally good but somehow in India or abroad anywhere if you talk about gold everyone fears as if it is very costly in fact platinum which is very often is costly much costlier than gold but when I come to it gold is very costly so the gold technology is never preferred for not being costly gold is very bad conductor bad trap centre creator in silicon it gives amphoteric means one level is above the lower which should be opposite side the acceptor is above the donor which gives huge amount of trapping okay and that is essentially killing the lifetime that is what used actually for killing the lifetime so where I do not want to come silver get oxidized without doing anything it just sees it and blackens okay so left is aluminium so people worked on then why not copper copper also get oxidized one is secondly copper also has a trap level in the silicon okay so in my time we never used the copper line of gases because which is very good to run all gases should pass through good conducting gas lines but we never used it because copper was anthem oh it may kill all my devices okay mere may not happen but we always were worried that copper should not be used within 100 meters of the lab okay no copper tubings yeah but that is the fantastic part aluminum on the top layer it forms but the layer layer it does not form that is called analyzation that it protects the aluminium is only thing which did does whereas copper oxide it actually pours down to all the films okay you have a point aluminum has all the features which you wanted actually protection so aluminium has all good features why we went from aluminium was that RC delay then we started looking for better conductive material okay that is the reason typically aluminium has many advantage of silicon technology aluminium silicon allies formed around 450 degrees it is called detecting so aluminium silicon forms a lie is around 450 degree even lower 423 hours 3 itself with the 450 most of it forms alive also aluminium is a dopant in silicon type 3 so at least on P it will make P plus so good homicity it can create okay fantastic it has a good very low temperature it can form a contact alloy between silicon and aluminium please remember alarm is better contact same uniform uniformity so I can this is something contact I should say if a normal metal semiconductor junction which is called short key barrier if I plot IV this dotted line is normal metal semiconductor short key barriers whereas the kind of contact I am looking or omicont I am looking should be very low resistance both in forward bias as well as in reverse bias so almost ideally I want like this zero resistance but that is not possible so close to that as low as possible this is what I am trying to achieve so silicon and aluminium forms a good ally aluminium is a type 3 dopant so it will give even better contact resistance or lower contact resistance and therefore more likely to give me more omic contact so no voltage drop at these contacts what is the problem if the voltage drop goes on the contact if source drain has additional voltage drops so the delay increases because for the channel pds decreases okay so I am trying to see that my source drain contacts have least voltage drops source drain itself will have some drop but this is additional one that there is a area with it the line may run longer much more area may create so I somehow wish to avoid the this part very quickly so I want to make good omicity however I mean aluminium has its own problems one of the major worries with aluminium as was found was when I made a aluminium contact to source on drain this is my aluminium and this is my n plus silicon n silicon or whatever it is please remember silicon has also solubility in aluminium and aluminium has a solubility in silicon is that clear this is called phase diagram aluminium dissolves in silicon and silicon dissolves in aluminium so around 450 itself aluminium has a silicon has sufficient diffusivity in aluminium so what happens when you start annealing for allowing the contact part of the silicon actually comes into aluminium okay it creates voids because aluminium silicon gone from there aluminium tries to diffuse down because it finds voids and silicon down so it comes down so you have aluminium contact to the substrate this is called junction pitting so why source drain gone is that clear the top contact is to the substrate no source drain of course this is not that everywhere it will happen but additional resistance certainly will occur and there will be an issue which sometimes circuit may not even function is that clear so the very large of junction pitting is actual when it will not occur if source drains are deeper in my time we are 3 micron source drains aluminium film was hardly 1000 to 2000 Armstrong's so it was very unlikely that it will goes to 3 micron deep so I mean ever saw junction pitting in earlier times but when I saw them become 1000 Armstrong's then this pitting is very very possible okay so currently so you can see scanning has actually created reality issue it is gives a pitting problems 450 anneal has to be done to make an alloy between aluminium and silicon it says you take thing if I come from aluminium this to silicon this at 450 they will form alloy look for a phase diagram okay okay so is that point clear so first major worry in a back end is that if you make aluminium contacts everywhere the prints scale down devices this issue may actually hurt you okay so what should I do between aluminium and silicon I should put something in between which will not allow aluminium or silicon to cross diffuse that is called barrier titanium nitride is a good barrier layer but it is certainly not as good a contact to silicon nor as good a contact to aluminium so normally thin titanium nitride layer is essentially interposed between silicon and aluminium layer just to make it barrier to for inter diffusions it is also called buffer layer in some books but most VLSI people call it barrier if you are noted down there is a another effect of course there is a third effect I forgot but may well say the present day tendency is to actually give some stresses to the silicon device what for we want to stress the device anyone mobility enhancement by compressive and by tensile one of the mobility could be enhanced so we are now really trying to shrink the device and trying to even create stresses okay now this compressive stress is particular is very harmful for aluminium actually if aluminium line is running and this structure is similar shown here and it receives because the device is under compressive stress part of the aluminium actually please remember aluminium is a metal is not crystalline what is the form of metal all metals are amorphous or polycrystalline at best poly or mostly amorphous okay now there is already grain boundaries in the polycrystalline now what happens when the metal is running over the side to layer due to the grain boundary diffusions or movements some aluminium moves away from its position and actually climbs over one and actually break the contact between the so it is a hillock formation which actually one can see in an under an SCM it is not a very even normal 100 X to 10 X microscope you can see this hillock okay and a breakage of contacts the similar effect if not same is also seen by electro migrations what is electro migration I said if in the metal layer huge current density is applied 10 to power 5 amper centimetre square then the number of electrons ions are very large there this num per unit area it is called electron wind electrons are more mobile so they try to move away and this moment of electrons causes a force and if aluminium ions or atoms there cannot stand to this force then they come jump okay similar like they jump and that is called electro migration if you put titanium nitride that itself will stop it because the electro migration coefficient of nitride is much lower compared to what is for aluminium okay so copper is the best for electro migration it is not easy for copper is more metallic than aluminium in grain boundary system so it does not climb so easily so current higher currents can easily be taken by copper compared to aluminium copper has better conductivity so now we have started thinking aluminum so we start looking for this to give some history on this the copper technology was first tried by Texas instrument and of course there is a word maybe I will come back to it for lower resistance interconnect per unit length aluminium is replaced now by copper in upper layers at least copper is a trap giving impurity in silicon I just said okay and hence needs again separation between anything to silicon it must get separated so what should I need between copper and this some kind of a barrier and that it wherever copper is going it should be surrounded by that barrier material so what is surrounding some system should be called in fibre what do we call cladding so all copper lines or copper this must be cladded by titanium nitride or some other barrier material okay so tantalum based alloys or vanadium based oxides nitride sometimes both or titanium nitrides are excellent cladding materials and they are normally surrounding copper lines okay just to give a history copper interconnect process was invented by claimed by I do not know whether they invented but they claim their patents both by IBM and Texas instrument around the year 98 and the interesting part why they did it that by just replacing aluminium by copper at least the three upper layer interconnects they found their circuit started speeding up by one and a half times without no architectural change those dimensions on anything just putting copper layers they figured out the speed to one and a half times so 3 gigahertz processor on those of course 2.1 gigahertz suddenly became 3 gigahertz processor for doing nothing except this new process okay so that is why copper has replaced at least for top interconnects that is decided by the technology films films are decided by technology people typically vias are of the order of 0.2 microns or 1,000 amstrong so only that much copper lines can run no vanadium X as a rega or we become there a plug no no no it is not circular I will show you a plug instead of plug I will tungsten plug there is a copper plug asset let us say I want between the two metal layers connection okay so I do a hole through inter bit oxide and connect top portion to the lower but can I connect the same upper metal down so that I do not want to drive on guaranteed contact from upper layer to the lower layer so I create a via which should be which which process will create vias are I because I want vertically dimensioned H okay then I will put some material in between which is conducting and easy to fill in this so that it fills up that we are okay this is called plug this is called plug which fills up that we are so I how do I create a plug let us say I have an oxide I open a window then I deposit titanium nitride first I open a window by lithography and I actually create titanium nitride okay film on that which is by CVD and then I deposit tungsten either by CVD or even by sputtering but normally by CVD yes WF6 is the gas which is used tungsten hexafluoride and that gas is passed through because in CVD what is the thing I kept on saying it is it will follow all the contours of the wafer conformal and therefore it will if this is like this copper will also I mean the tungsten will also flow this so I deposited tungsten sufficiently thicker than the via itself so you can see from here some thicker metal was deposited okay in the all proportions other than this okay then this thickness may be you know many a time the upper layer is deposited by sputtering the first you do CVD and then just deposit dumped by sputtering so that I do not have to worry about doing the ones it has come up I deposit even thicker on that okay is that okay 1 2 3 then I do little etching of the tungsten it is called H back this is very important process how much to reduce tungsten okay because the next process which we are going to do is our chemical mechanical polish and one very thick layers cannot be polished out so I have to reduce that tungsten thickness okay earlier I did not know I put sputtering I put some large numbers so then I monitored it I said okay at least 80% I must get rid of that so that is I normally do by etching only okay since tungsten is everywhere it ages everywhere so it reduces the thickness of tungsten and then I do chemical mechanical polish from this surface and tungsten just gets inside and please remember even nitride will be removed by mechanical this so there is a tungsten nitride and in between there is a sorry titanium nitride in between there is tungsten block or plug as it is called okay this process is actually called damson process is that okay how do I do it H the silicon dioxide titanium nitride tungsten thicker reduce thickness do CNP flattened so now I have a tungsten plug which is created here the next problem in the as I said we are of course as I said by Ion etching contacts I did I now want to see how do between the two metal layers which dielectric I should use okay two metal layers whether it is copper or aluminum are separated by dielectric layer and called IMD why IMD inter metallic dielectric IMD plus if you look at an IMD structure here this is a metal metal and a dielectric what it looks like a capacitor okay so now the problem starts for me the structure is now a capacitor so if any signal is passing on any of the transmission any of this metal line let us say M1 is carrying a signal and let us say the capacitance of this is such that the Z is 1 upon j omega C okay if C is large enough then Z will be smaller if omega is large enough Z will be smaller so higher frequency signal and with larger C if you have there is a connection at least at that frequency connection between metal 1 and metal 2 this is called crosstalk okay this is called crosstalk so what is the criteria I should to avoid crosstalk now there are many things we can try somehow C to it that the Z between the two metal is very high at a frequency of operation now to make Z very high another problem which I am worried about if I want to make Z high C should be smaller if C should be smaller that means T should be higher but if I use T very high what will happen the VR connection from top to bottom I cannot guarantee vertically down all the way deeper vias unlikely to get same size vias okay it will actually get a V grew on that okay the way it happens if thickness is larger I need deeper vias so it is reliability issue tungsten though they say that can go any conformality but if the VIA size becomes smaller in the lower side gas just goes above it is called surface tension effect so it does not cross the surface energy there so it does not stick to the lower side is that clear so there is a air gap is that point clear what I said if the VIA size is smaller the gas goes in but does not just the lower surface because there is what is called as surface tension effect which means there is no surface waiting so the gas just goes above and does not connect with the lower ends which means there is a air gap that means the resistance of VIA is going to increase now because how much is air gap it depends on that okay now this issue was very tough when I started shrinking earlier as I say 5 microns so obviously I do not want to increase thickness I wish I could but I do not want is anyway increasing drastically why because interconnects are in lengthening and lengthening so area of the capacitor is every time increasing so smaller the dimension device I make larger interconnect links I am using because I want larger circuits so more capacitance I am creating out of A P I cannot reduce or increase A is going to increase anyway so the only possibility left from here is to reduce epsilon is that correct so to avoid some kind of this increase some thickness and increase inter metallic dielectric whose epsilon is smaller okay is that point clear why back end people are worried about this because they find trust us too high okay with that okay function wise I want to make Z infinite or Z larger C should be smaller C should be smaller A is increasing T cannot be reduced too much so epsilon is the only which also I cannot play too much what is the smallest epsilon I can get one what is that here so air bridge is now being tried you are right okay here is what further as interconnected longer area is to increase the capacitor this to then reduce Z has to avoid grass talk or to increase Z at operating frequency we have only two options increase oxide thickness but it leads to more non-planar structures deeper vias reliability issues non-filling of vias by metal has this option is of limited option but limited second option is to use dielectric with lower epsilon k epsilon 0 so one of the material tried was hydrogen silly sequo zone sequo xn which is hsq in short which are the dielectric constant of 2.8 how much is dielectric constant of silicon dioxide 3.9 so at least by one insulator highway silicon dioxide 7 even higher so I want to reduce 2.8 is at least lower than silicon dioxide so I may use this kind of a glass which is a organic glass which I can put to which will slightly improve the capacitance ratios and therefore some better cluster property not build better and not best I want but something better there are also now people are trying organics like fluoropolymers as it is called these are polymers with fluorine their formulas are too big a carbon chain so benzene rings so I thought just to show on a page lot of carbon rings does not make sense so I did not draw but it has 12 carbon chain 2 in the one spin side 4 in the other spin side so lot of chemistry involved all said and done is dielectric constant is 1.8 so even better than silicon dioxide better than hsq so the most likely there is another material similar like polymer is called polymide which are the dielectric constant of 2.1 so next first we tried hsq then we go to polymide and now we are looking for fluoropolymers for the internal matter so what is the problem with these dielectrics for a higher temperature and higher humidity their properties change so their protection is very difficult so they need huge pacification on the top hsq flows also hsq flow but its flowing temperature is less than glass it is 600 or something it flows but the way it is it is soil gel deposition so it is a gel form so you actually dip and spin the spin surface occur that is how it is all processes normally for polymers are soil gels solution gels so you put drops and spin that is how it is deposited there is another material people are recently trying and to some extent successful in 1992 one of my PhD student worked on porous silicon actually not SiO2 porous silicon this is also porous SiO2 as well as porous silicon both are tried what is porous silicon anyone it is not an amorphous just silicon or amorphous this but there are pores along the crystalline there is no actual crystal anywhere there is no order and there is a gaps these are called pores it has a very different property than we are some other day we that time we did not realize that this can be useful in VLSI we were looking for LEDs because it will give electro luminescence porous silicon is used for electro luminescence okay so we are looking for LED replacement from the semiconductor so other normal so we were trying for porous silicon but we only left doing a lot of theory and never made a device so I do not know whether it gives light hopefully yes so no no no the silicon is etched in a etched in a particular solution so it gives lot of porosity deep into the solutions some other time maybe I will discuss it okay typical porous silicon and silicon dioxide layers have a dielectric constant around 1.2 to 1.8 which is what the best probably people will be able to achieve now okay of course the last one is air bridge there is a method of creating pressure structure that is shield structure in which air can be filled in between the two layers this is called pressurized air bridges it is a very complicated technology is done under vacuum very high vacuum 10 to power minus 16 tors but it is very difficult to maintain if small leak occurs it will just go away but it is possible to trap air in a smaller regions okay that is done through an MB machines okay that is done and it has a key of one ideal so between two metal layer only air gap it is doable but it is very complicated costly as if not right no between two metal layers when I actually I put a air bridge there and then I put the next metal that is why I say MB machines so there is a very tough situation but it is doable some effort have been successful but not 100% so I just do not want to discuss in known as industries last but not the least slide for this course is this this is another back end problem from one metal layer to the other metal layer how do I go interconnects okay that is most important you are nine layers seven layers at least but nine also can happen so from the layer to upper layer or upper layer how do I come down okay so here is the method of interconnection between let us say this is my source drain one of them this is my silicon this is my n plus then this is my IMD which is there there on IMD is this window please look at it first dried then we will discuss okay we have a silicon we have a source of drain n plus region I deposit IMD on that open a window this much deposit titanium nitride okay all three sides okay two sides then deposit metal which is tungsten in our case either by first CVD and that by dumping and then what do I do I do a CMP so that I get a plug okay then I deposit titanium nitride once again I deposit the next layer of metal which can be aluminum or copper now okay then over which I have another titanium nitride please remember any metal layer should be buried by both sides by a titanium nitride this so what you are saying when idiom when idiom plus this is occurs here exactly same as titanium nitride then next plug which you want to create should not be in this directions because this oxide during if you actually open here there is a misalignment issue because you will never see this if you actually put the next contact on that now I can see this in my pattern and I can start looking this size where I am putting the next contact if I use it here one is porosity issue some materials can go through second this contact I will not see below because lower side will be masked there so if I separate them first thing I must separate them so our next plug is again titanium nitride tungsten plug CMP another titanium nitride another metal layer another titanium nitride then the IMD in case you want to go ahead or if not you put the final passivation oxide in Chile mostly it is not oxide either it is borosilicate or phosphosilicate glass or Si3 and 4 the top layer of a silicon wafer is protected by silicon nitride whole wafer is coated with silicon nitride only pads are etched out the rest whole circuit is protected by nitride nitride is a very hard material difficult to if you touch it scratch it it does not go below the surface so that is why it is also it stops water molecules it also stops all kinds of impurities to go through this is a relatively thicker nitride it does not allow anything to go through it so it is called excellent passivations so all wafers are passivated finally the last masking is done for only pads pad patterns okay the rest whole chip circuit part is protected by nitrides then you are taking to the whatever the package you want first buy sit into chips put each ties on a different kinds of ceramic or metallic or whatever oh yeah there are two technologies there either by wire bonding you can take from the this or there is called ball bonding you have created a ball pattern and put flip chip it is something like this I have a metallic balls and this has the layer of actual wafer so here is the one pad here is another pad here so this pad pattern is flip chipped on the ball patterns and soldered soldered balls are quite thick so they their inductance is very low we are more worried about the way it is in a package see this is your package patterns pads which are actually external pins and this is your chip you have one pad you wire bond here now this length is not very small so because of that there is sufficient inductance with this now this inductance is used in RF and analog as an inductor itself because I need an inductor it is available there so it is called wire inductor but in a normal digital circuit I do not want this to happen okay so I do not want this connection like this I want flip chip I will just bond it on the balls okay that is how I will use it okay these are all back but once you are passivated both sides you just put passivation an epoxy dull though everything no generally that vacuum is released hoja that porous kithna be hoz material is porous accumulates this finishes the VLSI silicon integrated circuit VLSI course as best as we could there are many hundreds of issues which I have not touched I wish I could have from your side it is good I did not but from my side I missed a few