 Hello everyone, welcome to lecture on VHDL module for decoder and encoder. At the end of this session, students will be able to analyze design and implement encoders and decoders. Now, before starting with the actual session, let us pause the video and think about what is the process. Now the process is nothing but is a sequential section of VHDL code, which is located in the statement part of the architecture. And in the process, only the sequential statements are allowed, sequential statements are nothing but the if statements, loop statements, case statements, only those statements are used inside the process. Now let us start with the encoder, start with the attest to three encoder. Now, now this is the attest to three encoder, which is having eight input, which is encoded in the form of three-bit output, right. So, here i is the eight-bit input, i0 to i7 and z is the three-bit output, z0 to z2. This is the truth table for this attest to three encoder. These are the inputs, all eight bits, these are the output, all three bits. Now depending on the which input line is bit is one, according that you are having output line. So, if the i0 is one, in that case your output bits are 0, 0, 0. If the i1 is one, in that case your output is bit having value 0, 0, 1. So according that the last combination is if the i7, i7 bit is one, in that case you are having all the output bits are one. Now let us go for the VHDL module for this attest to three encoder. Now, while writing the VHDL module, first there are three parts. First part is a library declaration. So, you have to include the library and packages whatever you are using. So, library IEEE, then from that we are using STD logic 1164 package. So, that is why use IEEE dot STD logic 1164 dot all. Once you done with the library declaration, second important part of the VHDL module is entity. So entity which describe the input and output ports of your system or design for which you are writing the VHDL module. So now here we are writing for the attest to three encoder. So entity encoder 83 that is the entity name is now port in that you are having you have to declare the inputs and outputs. Now input is i's input which is of 8 bits. So that is why it is written as a STD logic vector 7 down to 0, Z is output which is again 3 bits. So, it is that is why it is written as a STD logic vector 2 down to 0. And the last once you done with the port declaration you have to end the entity. So end entity, entity name same name supposed to be there. After that comes the third important part of the VHDL module that is architecture. So architecture name of entity name is architecture begin process, inside the process you have to write the sensitivity list which is nothing but the inputs. So in this case the input is only one that is i. So that is why i is there that is a sensitivity list then process begin. Now because of the 8 bit input you have different combinations of that. So we have to use the case statement. So case i is when it is 0 0 0 0 0 0 0 1 in that case output Z equals to 0 0 0 same V i just did in a truth table. So complete the remaining combinations and according that you have to end the case if the inputs are not among these other than these possible combination in that case you have to write when it is others your output is having Z Z Z that is high impedance on the output. Then end case then end process and the last you have to end the architecture. So this is the structure or flow to write the VHDL module. Now this can be verified with the help of simulation. So this is the output forms of the 8S to 3 encoder you can verify that for example if I show you if it is not from the possible combination input is not possible it is undefined. So that is why the output is having high impedance. Second combination if you saw over here the all the input bits are 0 which is not from the truth table not from the possible combination still that output is high impedance. Now here it is become last bit is 1 means it is a from the combinations those are available for the input. So that is why you are having the values according that similarly second bit is 1 you are having 0 0 1 see. So this is how you can verify this your VHDL module with the help of simulation. Now let us go for the decoder let us try 3S to 8 decoder which is a reverse version of your 8S to 3 encoder. In that case encoder you are having 8 inputs and 3 outputs here in the decoder you are having 3 inputs and which is decoded in a 8 output. So this is the 3S to 8 decoder 3 inputs 8 outputs this is the table truth table for similar to the encoder only the condition is what here the inputs are 3 bit and output are 8 bit. So depending on the input combinations yeah according that the output 1 bit from the output is 1 other bits are 0 see. Now you know the working of your decoder using this truth table. Let us go for the VHDL module for that. As we know first part is a library declaration we have to write the which library we are using so library IEEE and from that library which package we are using so that package also included so use IEEE dot std logic 1164 this one is a package. Now from that package which components you are using or what are the part you are using we are using all whether they from that package we are using constants or packages or functions mentioned in that we are using all that one. So after library declaration second part is a entity part which describes or which gives the brief introduction about the inputs and outputs of your system design. So entity entity name is port now in this case I is the input which is a type of bit vector so std logic vector 2 down to 0 3 bit the z z is the output again type of vector so 7 down to 0 right then end entity name that is entity part is done. Now you have to write the third important part of your VHDL module that is architecture. So architecture, architecture name of entity name is now architecture begin process after that process inside the process you have to write the sensitivity these are nothing but the inputs now in this case the input is only I so that is I is there if it clock is also included over here you have to write the clock also right. So I after that process begin now because of input having 3 bit so 8 combinations are there so we have to use case statement so case I is when it is 0 0 0 in that case the output z equals to this value when the I is 0 0 1 in that case z is having this value. According that from the truth table we can complete all the possible combinations and the this if the input is not from these possible combination in that case you have to write the state last line that is when it is others output is having high impedance on this so that is why we written z over here all 8 z right. After that end case once you done with that end process and end architecture so this is the syntax you have to follow to while writing the VHDL module library declaration entity declaration and architecture declaration. Once you done with the VHDL module writing you can verify that with the help of simulation so here this is the simulation output of 3s to 8 decoder now here if you saw see that this one is a undefined input 3 in 3 bit input is undefined so this is not from the possible combinations of the case statement whatever we written in the previous slide so because of that it executes others condition last line of the case statement when others the output z equals to all 8 bits are z having high impedance so that is why sorry so that is why it is having all 8 bits are z. If I change the input from undefined to all input 3 bits are 0 0 0 in that case this one is the possible combination from the case statement which is a first line of the case statement so in that case the z is equals to 0 0 0 0 0 0 1 right similarly you can verify the remaining possible combination like 0 1 0 right over here then 1 1 0 the all 1 over here in that case the last bit is 1 right so using this type of simulation you can verify the VHDL module whatever you generated right these are the references thank you.