 Hello, and welcome to this presentation of the STM32 real-time clock. It covers the main features of this peripheral, which is used to provide a very accurate timebase. The RTC peripheral features an ultra-low power calendar with alarms, which run in all low power modes. Additionally, when it is clocked by the low-speed external oscillator, or LSE, at 32.768 kHz, the RTC is functional even when the main supply is off, and when the VBAT domain is supplied by a backup battery. The RTC embeds 128 bytes of backup registers used to preserve data when the main supply is off. These backup registers can be used to store secure data, as they are erased when a tamper event is detected on the tamper pins. The RTC consumes 225 nanoamps at 1.2 volts, including the LSE power consumption. The hardware calendar is provided in binary-coded decimal or BCD format to reduce software load, particularly when the date and time must be displayed. The anti-tamper circuitry includes ultra-low power digital filtering, avoiding false tamper detections. The key features of the RTC are seconds, minutes, hours, weekday, date, month, and year, provided in a binary-coded decimal format. Subseconds are provided in binary format. Add or remove one hour on the fly to the calendar in order to manage daylight savings. Two programmable alarms, which can wake up the microprocessor from all low-power modes. An embedded auto-reload timer, which can be used to generate a periodic flag or interrupt with wake-up capability. The resolution of this timer is programmable. The calendar can be calibrated thanks to a reference clock source, which is the mains at 50 or 60 Hz. A digital calibration circuit allowing compensation of the crystal accuracy with 0.95 ppm resolution. A timestamp function to save calendar contents in timestamp registers, depending on an external event. And 128 bytes of backup registers split into 32 32-bit backup registers. These registers are preserved in all low-power modes and in VBAT mode and are erased when a tamper detection event occurs on any one of the three tamper pins. All tamper pins are available in VBAT mode. Here is the RTC block diagram. The RTC has two clock sources. The RTC clock or RTC CLK is used for the RTC timer counter and the APB clock is used for RTC register read and write accesses. The RTC clock can use either the high-speed external oscillator or HSE divided by a programmable factor from 2 to 63, the low-speed external oscillator or LSE, or the low-speed internal oscillator or LSI. To be functional in stop or standby mode, the RTC clock must use the LSE or LSI. To be functional in VBAT mode, the RTC clock must use the LSE. The RTC clock is first divided by a 7-bit programmable asynchronous prescaler which provides the CKAPRE clock. Most of the RTC is clocked at the CKAPRE frequency. So in order to reduce power consumption, it is recommended to set a high asynchronous division value. The default value is 128. Then a 15-bit programmable synchronous prescaler provides the CKSPRE clock. CKSPRE must be 1 hertz in order to update the time and date BCD registers in one second increments. The sub-second register resolution is defined by the CKAPRE frequency. By default, it is 256 hertz. The SSR register resolution is increased by reducing the asynchronous prescaler value. The asynchronous prescaler can also be bypassed. In this case, the sub-second register resolution is defined by the RTC clock frequency. The RTC is initialized using a secure method. The RTC registers are right protected to avoid any possible parasitic right accesses. First, the disabled backup domain protection bit must be set in the power controller control register in order to enable RTC right accesses. Then a specific sequence must be written in the RTC right protection register. Initialization mode must be entered in order to change the clock prescaler values or the calendar value. The RTC calendar keeps running in all low power modes, in VBAT mode, and during reset. Initialization of the time and date registers is performed through their shadow registers, which are in the APB clock domain. The sub-second register cannot be initialized. The calendar sub-second, time and date registers content can be read in two different modes. When the bypass shadow registers control bit is cleared, the shadow registers are read. The advantage of this mode is that it guarantees that all three registers are consistent. When the time register is read, the date register is frozen until it is read. When the sub-second register is read, the time and date registers are frozen until the date register is read. The disadvantage of this mode is that when exiting stop, standby, or shutdown mode, the software must wait for a synchronization delay to ensure that the shadow registers are updated with the last calendar register values. This synchronization delay can be up to two RTC clock periods. When the bypass shadow registers control bit is set, the actual calendar registers are read directly. The advantage of this mode is that there is no need to wait for the synchronization delay. The disadvantage is that the read values can be false or not consistent due to synchronization issues. So they must be read twice and compared with previous read values to ensure they are correct and coherent. This slide presents the main calendar features. Daylight savings can be managed by software with automatic one-hour addition or subtraction. It is possible to synchronize the RTC clock to a remote clock by adding or subtracting an offset to the sub-second register on the fly with CKAPRE clock resolution. This feature is commonly used in RF applications. A reference clock, means at 50 or 60 hertz, can be used to enhance long-term calendar precision. The reference clock is automatically detected and used to update the calendar when it is present. When the reference clock is not available, the LSE clock is automatically used to update the calendar. This feature is not available in standby, shutdown, and VBAT modes. A timestamp function is available. The calendar values, sub-second, time, and date registers are saved in timestamp registers when an event occurs on the timestamp IO. A timestamp event can also occur when a switch to VBAT occurs. The digital calibration is used to compensate crystal inaccuracy and accuracy variations with temperature and aging. It consists in masking or adding a programmable number of RTC clock cycles, fairly well distributed in a configurable window. The calibration value can be changed on the fly, depending on detected temperature changes, for instance. A 1 hertz calibration output signal is provided to measure the crystal frequency before and after applying the calibration value. The accuracy shown here is the resolution of the digital calibration. The calibration window size is configurable between 8, 16, and 32 seconds. For a 32 second calibration window, the accuracy is plus or minus 0.48 ppm. The total correction range is from minus 480 to 480 ppm. The accuracy resolution scales with the calibration window size. Final accuracy in the application will depend on the crystal parameter precision, temperature detection precision, how often the software calibration procedure is launched, etc. In order to reach the precision of the calibration window, the measurement window must be a multiple of the calibration window. The RTC embeds two flexible alarms based on comparison with the calendar value. The alarm flags are set if the calendar sub seconds, seconds, minutes, hours, or date match the value programmed in the alarm registers. The alarms event can wake up the device from all low power modes. The alarms event can also be routed to the specific output pin RTC out with configurable polarity. The calendar alarm sub seconds, seconds, minutes, hours, or date fields can be independently masked or not masked for the comparison. When the masks are used, periodic alarms are generated. In addition to the calendar and alarms, another 16-bit auto reload counter can generate periodic events with wake up from low power modes capability. This counter cannot be read. Depending on the software configuration, the wake up timer clock can be the RTC clock divided by 2, 4, 8, or 16, or the output of the synchronous pre-scaler. With the divided RTC clock, the wake up period can be from 122 microseconds to 32 seconds when the RTC clock frequency is 32.768 kilohertz. The resolution is down to 61 microseconds in this case. With the CK SPRE clock, the wake up period can be from 1 second to 36 hours when the CK SPRE clock is at 1 hertz. The RTC embeds ultra low power tamper detection circuitry. The purpose is to detect physical tampering in a secure application and to automatically erase sensitive data in case of intrusion. Three tamper pins and events are supported and are functional in all low power modes and in VBAT mode. The tamper 3 event detection is generated either by an event on I.O. or by an over or under voltage of the RTC power supply domain or by an over or under temperature detection. These voltage and temperature monitor detections are enabled in the PWR C2R control register. The detection can be edge or level triggered and the active edge or level is configurable for each event. Backup registers content are erased when a tamper event is detected. In addition, a tamper event prevents any read access to the backup SRAM until its erase operation is finished. A tamper event can generate a timestamp event. The tamper detection circuit includes an ultra low power digital filter. The internal I.O. pull-up can be used to detect the anti-tamper switch state. The I.O. pull-up is applied only during the pre-charging pulse in order to avoid any consumption if the tamper pin is at a low level. Pre-charging pulse duration is configurable to support different capacitance values and can be one, two, four or eight RTC clock signals. The pin level is sampled at the end of the pre-charging pulse. A filter can be applied to the tamper pins. It consists of detecting a given number of consecutive identical events before issuing an interrupt to wake up the device. This number is configurable and can be one, two, four or eight events at a programmable sampling rate from one to 128 Hz. This figure illustrates tamper detection using the internal pull-up. The internal pull-up can be applied for one, two, four or eight cycles. If the switch is opened, the level is pulled up by the resistor. If the switch is closed, the level remains low. The input voltage is sampled at the end of the pre-charge pulse. Several RTC events can generate an interrupt. All interrupts can wake the microprocessor up from all low power modes. The Alarm A interrupt is set when the calendar value matches the Alarm A value. Similarly, the Alarm B interrupt is set when the calendar value matches the Alarm B value. The wake-up timer interrupt is set when the wake-up auto-reload timer reaches zero. The timestamp interrupt is set when a timestamp event occurs. The tamper one, two and three interrupts are set when a tamper event is detected respectively on the RTC TAMP 1, RTC TAMP 2 or RTC TAMP 3 pin. The RTC peripheral is active in all low power modes and the RTC interrupts cause the device to exit the low power mode. In stop and standby modes, only the LSE or LSI clocks can be used to clock the RTC. Note that only the LSE is functional in VBAT mode. A bit is available in the MCU debug interface in order to stop the RTC counter when the core is halted for debugging. This is a list of peripherals related to the real-time clock. Please refer to these peripheral trainings for more information if needed. Reset and clock control, power control and extended interrupt controller. Thank you.