 In this video we are going to describe how the instructions in the AVR architecture are encoded. So we are going to describe the instruction format. Remember this AVR architecture is a risk architecture, in other words it offers a reduced set of instructions, each of them fairly simple. So a couple of special features to take into account. This processor represents instructions with 16-bit format, but not all of them, we'll see some exceptions, and some of them go to 32-bits of length. But most of them have this 16-bit format. This is also an example of a microprocessor that could be considered fixed length instruction. And the instructions have all the following structure. There is an operation code that tells us what the instruction is going to do and then typically one or two operands, never more than two. So these are the operands and this is the operation code. This second operand in some instructions is optional and is not present. So let's get examples of the formats that are supported by the microprocessor. The first one is, let's consider these 16-bits, is divided into four fields. The first field has six bits to encode the operation code. The second one is only two bits, I'll go back to that in a second, and then two additional fields, four bits each, to encode the operand one and operand two. So this is one possible way of encoding the format that I just described here with, as I said, 16-bits. Now this architecture offers 32 general purpose registers. If we want to allow the instructions to manipulate any of these 32 general purpose registers, we need to encode the number of the register, which is an number between 0 and 31. This translates into a field here that requires five bits if we want to encode as operand one, one of these registers, and as operand two, one of these registers. Five bits, this is the reason why we have here all these fields. And this field over here is to make sure that operand one and operand two can be encoded with five bits. So the five bits that encode the second operand is four bits from here plus one bit from here. And the five bits that encode the first register operand would be something like this. So remember, we're going to need five bits to encode 32 registers. So this format is the one that the microprocessor typically uses to encode those instructions that have two operands like in here with two registers. But it's not the only format. Another one, used in some instruction, again with 16 bits, contains the following division. We have eight bits here for the operation code. And then we have two fields of two bits here, each, and finally a four-bit field. Now these four-bit fields and two-bit fields are used to encode a constant. And this two-bit field is used to encode a register. Now this is a very interesting format because it tells us a few things. This instruction is going to perform certain operation over a constant and a register. And we should know that the register is only allowed to be encoded with two bits. Therefore, the limitation of this instruction that is going to derive from this encoding is that we will not be able to specify any of the 32 registers in this instruction because this instruction only allows us two bits to encode the register. Therefore, only some of the registers will be allowed. In exchange, what we have is the possibility to use six bits to specify one of these constants. So here, the common to make is that the register can only have four possible values. A third format that is used by the microprocessor is this one. Let's call it Format 3, in which we have four bits, again, of operation code. We have another four bits here, which we are going to use for a constant. Four bits for the destination register and the remaining four bits again for the constant. So this is another interesting format because the fact that we want to keep the instructions reduced to 16 bits forces us to restrictions. The constant is represented with eight bits and therefore we will be restricted on the range of values that we can use there. And the register, it's going to be encoded with only four bits, which means that we will only be able to refer to 16 out of 32 bits of the microprocessor. Let's see examples of this encoding. Let's start with this instruction that adds the content of register 31 to register 0. And let's see how is this instruction encoded. So this instruction will have a size 16, 16 bits. And the way it is encoded is first with the operation code, which in this case will occupy six bits and is 0, 0, 0, 0, 1, 1. That would correspond to the add. Then we have here two bits, 1 and 0, which will explain what they represent. And then we have 0, 0, 0, 0 and 1, 1, 1, 1. So this would be the representation in 16 bits of this instruction, which is part of the instruction set of the AVR architecture. And this format corresponds to this scheme that we just described here. We see here the example. We have six bits to encode this instruction. Two bits, which we know one of them is for the source and the other one is for the destination. The following four bits are encoding the destination together with this fifth bit here. And therefore, what we can see is how these five bits encode number 0, which correspond to register 0. And finally, these four bits we have here. Plus this one over here encode register 31. What this means is that this instruction will be represented in memory by these 16 bits. Or a more comfortable way for us to manipulate every member, we use hexadecimal representation to pack these bits into groups of four. And from here we obtain the encoding 0, E, 0, F. Let's see another example of another instruction. In this case, let's take CPI R16 255. And again, let's explore its representation with 16 bits. In this case, the format that we are using is, first we're going to use four bits only for the instruction code. In this case, CPI, which is 0, 0, 1, 1. Then we will have four bits to encode a part of this constant, which will be 1, 1, 1, 1. Next four bits to encode this register, which happens to be encoded as 0, 0, 0, 0. And finally, four additional bits, 1, 1, 1, 1, that encode also the constant. So these four bits are the instruction code. These four bits are encoding R16. And these two groups of eight bits are encoding the number 255. So this is an example of the format number two. In this case, what we have is the constant is made out of these four bits concatenate with these four bits. We have four bits for the instruction and the remaining four bits encode a register. Now these, as I said before, translates into a restriction. For the instruction CPI, we're only allowed to use registers from R16 to R32, sorry, 31. In other words, if we write the instruction CPI R0, R1, R2, or any value between R0 and R15, the translator will tell us that that's an illegal instruction because it cannot be encoded. The convention is that the four bits are used to encode the register from R16 to R31. This constant, on the other hand, will have a maximum of eight bits, and therefore the value can only be between 0 and 255. In memory, again, this instruction will be represented by these 16 bits, or for us, its equivalent hexadecimal code is 3F0F. Let's look at a third example. This is a little bit of an exception of what I mentioned here. Some of the instructions, or most of the instructions of this architecture, occupy 16 bit, but some of them occupy 32. So let's take a look at an example of an instruction that occupies 32 bits. And this is the instruction, LDS R12 12565. This instruction is going to go to memory to the address specified here, is going to get the information that is stored in that cell and load it into register R12. So this is a data transfer instruction. This previous instruction I didn't mention is simply comparing the value of R16 with the value 255, which internally what it means is that there is a subtraction that is performed R16 minus 255. So going back to this example, as I said, we're going to go to memory to this address and obtain a data that is going to be stored in R12. How is this encoded in this format? Well, this instruction, as I said, is a little bit of an exception because instead of 16 bits, it's going to use 32. And the reason for that is because the second operand, which is a memory address, needs in itself 16 bits to be represented. So the first 16 bits are going to be encoding the operation and the register. The second 16 bits are going to be devoted to encode the memory address or this value. So this is the format that the microprocessor uses. It uses seven bits to encode the operation LDS. 1, 0, 0, 1, 0, 0, 0. Then there are four bits, five bits to encode the register, 1, 1, 1, 0, 0. And the remaining four are also part of the operation code. So the operation code here is fragmented between this field and this field. This is the register, in this case R12. And finally, these 16 bits here, which are 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, represents the R12,565. So as you can see, in this case, the instruction that is executed requires two memory cells to be accessed, the first one with this value. What typically occurs with a microprocessor is it starts parsing these bits and it realizes that it's an LDS instruction and therefore it needs to go back to memory and take another extra 16 bits, which it does and then performs the operation once both groups of 16 bits are here. In this case, the instruction would be encoded in memory, not occupying two bytes as the ones before, but this one would occupy four bytes and the hexadecimal representation is 9.1 C0 3.1 1.5